JPH0416939B2 - - Google Patents
Info
- Publication number
- JPH0416939B2 JPH0416939B2 JP10382782A JP10382782A JPH0416939B2 JP H0416939 B2 JPH0416939 B2 JP H0416939B2 JP 10382782 A JP10382782 A JP 10382782A JP 10382782 A JP10382782 A JP 10382782A JP H0416939 B2 JPH0416939 B2 JP H0416939B2
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- silicon film
- etching
- impurity concentration
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 40
- 239000012535 impurity Substances 0.000 claims description 27
- 239000004065 semiconductor Substances 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- 230000001590 oxidative effect Effects 0.000 claims 1
- 239000010408 film Substances 0.000 description 47
- 238000005530 etching Methods 0.000 description 32
- 238000000034 method Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 2
- 238000000992 sputter etching Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Weting (AREA)
Description
本発明は半導体装置の製造方法に関し、詳しく
は、２層以上の多結晶シリコン膜の微細加工にと
くに有用な、半導体装置の製造方法に関する。
周知のように、多結晶シリコン膜の加工方法に
は、エツチングに方向性のない等方性エツチング
法と、エツチングに方向性を有する異方性エツチ
ング法に大別される。
代表的な等方法エツチング法は、エツチ液を用
いてエツチする、いわゆるウエツト（湿式）エツ
チング法であるが、等方性エツチング法では、微
細なパターンを高い精度で形成するのは困難なこ
とが知られている。
すなわち、第１図は、シリコン基板１上に、
SiO2膜２および多結晶シリコン膜３を積層して
形成し、マスク４を用いて、上記多結晶シリコン
膜３を選択的等方性エツチして得られた、多結晶
シリコン膜３の断面形状を示したものである。
第１図から明らかなように、等方性エツチング
によつて加工を行なうと、マスク４の下部の多結
晶シリコン膜３も横方向にエツチングされる、い
わゆるアンダーカツトが生ずるため、寸法や形状
を高い精度で制御することは困難である。
一方、異方性エツチングは、エツチングに用い
たマスクどおりの寸法で加工することが可能であ
り、高い集積密度を持つたLSIの形成に不可欠な
技術となつている。
しかし、異方性エツチングには、固有の問題が
あり、解決が要望されている。
すなわち、多結晶シリコン膜を異方性エツチン
グによつて加工すると、第２図記号３′で示した
ように、側面がほぼ垂直となる。この多結晶シリ
コン膜３′の表面を酸化して、表面を薄い酸化膜
５で覆い、再び多結晶シリコン膜６を全面に被着
した後、この多結晶シリコン膜６を異方性エツチ
ングによつてエツチする。このようにすると、多
結晶シリコン膜６の膜厚は、上記多結晶シリコン
膜３′の側部で厚くなるため、上方から異方性エ
ツチングを行なうと、第２図に示したように、多
結晶シリコン３′の側部にエツチング残り７が生
じてしまい、微細加工のために大きな障害になつ
ていた。
また、側部がほぼ直角にできることは、微細加
工の点では有利であるが、その上に配線を通した
場合には、断線が生じやすく、好ましくない。
本発明の目的は、上記従来の問題を解決し、エ
ツチンク残りや断線の生ずる恐れのない半導体装
置の製造方法を提供することである。
上記目的を達成するため、本発明は、不純物濃
度の差によつてエツチング速度の相違が生ずるこ
とを利用して断面を台形とすることにより、上記
エツチング残りや断差の発生を防止するものであ
る。
以下、本発明を詳細に説明する。
上記のように、等方性エツチングによつて得ら
れた断面形状は、アンダーカツトのために台形状
になる。この場合、上に多結晶シリコン膜を積層
被着してエツチングを行なつても、エツチング残
りの生ずる恐れはなく、断線の発生も大幅に減少
できる。
等方性エツチングは、加工寸法や形状の制御性
が極めて不良であるため、高集積密度の半導体装
置の形成には不適であるが、高い制御性をもつ
て、断面が台形状の膜を形成することができれ
ば、上記問題はすべて解決されるはずである。
本発明はこのような考えにもとずいて行なわれ
たものであつて、多結晶シリコン膜の上下方向
に、不純物濃度の差を持たせて上部よりも下部の
方が不純物濃度が大きくなるようにする。これを
ドライエツチして所望の形状にバターニングした
後、多結晶シリコン膜の表面を酸化して、断面を
台形状とするものである。
以下、本発明を詳細に説明する。
周知のように、エツチ液を使用する湿式エツチ
ングなど、等方性エツチングによつて、酸化膜や
多結晶シリコン膜などを加工した場合、サイドエ
ツチなどのために、加工精度は極めて低く、高い
集積密度を持つた半導体装置の形成に、湿式エツ
チングを使用することは困難である。
しかし、湿式エツチングによつて加工された酸
化膜などの断面は台形状となるため、この上を横
切るように配線を形成しても、断面が生ずる恐れ
は極めて少ない。
したがつて、加工精度の高い異方性エツチング
によつてパターニングを行ない、かつ、断面を台
形状にすることができれば、断線の恐れが少な
く、集積密度の高い半導体装置の形成が可能とな
る。
本発明は、不純物濃度が、上部では低く、下部
では高い多結晶シリコン膜を、まず、ドライエツ
チングなど異方性エツチによつて所望の形状にパ
ターニングした後、表面を酸化する。
多結晶シリコン膜を、異方性エツチングによつ
てパターニングすると、断面がほぼ垂直な多結晶
シリコン膜が形成され、極めて高い加工精度が得
られる。
つぎに、上記多結晶シリコン膜の表面を酸化す
ると、多結晶シリコン膜の酸化速度は不純物濃度
に依存し、不純物濃度が高いほど酸化速度も大き
くなるから、得られるシリコン酸化膜８は第３図
から明らかなように、上部では薄く、下部では厚
くなる。
その結果、第３図に示したように、多結晶シリ
コン膜３″の断面は逆台形状になるが、全体とし
ての断面は台形となり、その上に配線を横切るよ
うに形成しても、断線の生ずる恐れは極めて少な
い。したがつて、異方性エツチングよる高い加工
精度と、台形状の断面による断線の防止が同時に
達成される。
実施例 １
厚さ3000〓の多結晶シリコン膜を、反応性スパ
ツタエツチングによつてパターニングした後、
750℃の水蒸気中で４時間酸化したときの、得ら
れる酸化膜側面と基板表面の間の角度θ（第３図）
と、上記多結晶シリコン膜中の不純物濃度の関係
を求め、第１表に示す結果を得た。
すなわち、第１表は不純物濃度が上端部から下
端部へ向つて連続的に高くなるような多結晶シリ
コン膜の、上端部における不純物濃度はいずれも
１×1019cm-3以下と、いずれも一定とし、下端部
の不純物濃度を種々に変えて、上記処理を行なつ
た場合の、下端部における不純物濃度と上記角度
θとの関係を表わす。
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device that is particularly useful for microfabrication of two or more layers of polycrystalline silicon films. As is well known, methods for processing polycrystalline silicon films are broadly classified into isotropic etching methods in which the etching is not directional, and anisotropic etching methods in which the etching is directional. A typical isotropic etching method is the so-called wet etching method in which etching is performed using an etchant, but it is difficult to form fine patterns with high precision using the isotropic etching method. Are known. That is, in FIG. 1, on a silicon substrate 1,
Cross-sectional shape of polycrystalline silicon film 3 obtained by laminating SiO 2 film 2 and polycrystalline silicon film 3 and selectively isotropically etching the polycrystalline silicon film 3 using mask 4. This is what is shown. As is clear from FIG. 1, when processing is performed by isotropic etching, the polycrystalline silicon film 3 under the mask 4 is also etched laterally, creating a so-called undercut. It is difficult to control with high precision. On the other hand, anisotropic etching allows processing to match the dimensions of the mask used for etching, and has become an indispensable technology for forming LSIs with high integration density. However, anisotropic etching has inherent problems that need to be solved. That is, when a polycrystalline silicon film is processed by anisotropic etching, the side surfaces become almost vertical, as shown by symbol 3' in FIG. The surface of this polycrystalline silicon film 3' is oxidized, the surface is covered with a thin oxide film 5, a polycrystalline silicon film 6 is again deposited on the entire surface, and then this polycrystalline silicon film 6 is anisotropically etched. Have sex with me. In this way, the thickness of the polycrystalline silicon film 6 becomes thicker at the side portions of the polycrystalline silicon film 3', so when anisotropic etching is performed from above, the polycrystalline silicon film 6 becomes thicker as shown in FIG. Etching residues 7 were formed on the sides of the crystalline silicon 3', posing a major hindrance to microfabrication. Further, although it is advantageous in terms of microfabrication that the side portions can be formed at almost right angles, it is not preferable that wires are easily broken when wires are passed over the side portions. SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional problems and to provide a method for manufacturing a semiconductor device without the risk of etching residue or wire breakage. In order to achieve the above object, the present invention takes advantage of the difference in etching rate caused by the difference in impurity concentration to make the cross section trapezoidal, thereby preventing the occurrence of the etching residue and difference. be. The present invention will be explained in detail below. As mentioned above, the cross-sectional shape obtained by isotropic etching becomes trapezoidal due to the undercut. In this case, even if a polycrystalline silicon film is laminated and etched thereon, there is no risk of etching residue being left, and the occurrence of wire breakage can be greatly reduced. Isotropic etching has extremely poor controllability of processing dimensions and shapes, making it unsuitable for forming semiconductor devices with high integration density. However, it is possible to form films with trapezoidal cross sections with high controllability. If possible, all of the above problems should be solved. The present invention was carried out based on this idea, and involves creating a difference in impurity concentration in the vertical direction of a polycrystalline silicon film so that the impurity concentration is higher in the lower part than in the upper part. Make it. After this is dry-etched and patterned into a desired shape, the surface of the polycrystalline silicon film is oxidized to have a trapezoidal cross section. The present invention will be explained in detail below. As is well known, when oxide films or polycrystalline silicon films are processed by isotropic etching such as wet etching using an etchant, the processing accuracy is extremely low due to side etching, and high integration density is required. It is difficult to use wet etching to form a semiconductor device with a thin film. However, since the cross section of an oxide film processed by wet etching is trapezoidal, even if wiring is formed across this, there is very little possibility that a cross section will occur. Therefore, if patterning can be performed by anisotropic etching with high processing accuracy and the cross section can be made into a trapezoidal shape, there is less risk of disconnection and it becomes possible to form a semiconductor device with high integration density. In the present invention, a polycrystalline silicon film in which the impurity concentration is low in the upper part and high in the lower part is first patterned into a desired shape by anisotropic etching such as dry etching, and then the surface is oxidized. When a polycrystalline silicon film is patterned by anisotropic etching, a polycrystalline silicon film with a substantially vertical cross section is formed, resulting in extremely high processing accuracy. Next, when the surface of the polycrystalline silicon film is oxidized, the oxidation rate of the polycrystalline silicon film depends on the impurity concentration, and the higher the impurity concentration, the higher the oxidation rate, so the obtained silicon oxide film 8 is as shown in FIG. As is clear from this, it is thinner at the top and thicker at the bottom. As a result, as shown in FIG. 3, the cross section of the polycrystalline silicon film 3'' becomes an inverted trapezoid, but the cross section as a whole becomes a trapezoid. There is very little possibility that this will occur. Therefore, high processing accuracy due to anisotropic etching and prevention of wire breakage due to the trapezoidal cross section can be achieved at the same time. Example 1 A polycrystalline silicon film with a thickness of 3000 mm was After patterning by sputter etching,
Angle θ between the side surface of the resulting oxide film and the surface of the substrate when oxidized for 4 hours in water vapor at 750°C (Figure 3)
The relationship between this and the impurity concentration in the polycrystalline silicon film was determined, and the results shown in Table 1 were obtained. In other words, Table 1 shows that for polycrystalline silicon films in which the impurity concentration increases continuously from the top end to the bottom end, the impurity concentration at the top end is 1×10 19 cm -3 or less. The relationship between the impurity concentration at the lower end and the angle θ is shown when the above processing is performed while the impurity concentration at the lower end is held constant and the impurity concentration at the lower end is varied.
【表】
第１表から明らかように、不純物濃度が高くな
るほど、角度θは大きくなり、ゆるやかな傾斜が
得られる。上記条件で処理した場合、下端部の不
純物濃度と角度θの間には第４図に示す関係があ
るから、多結晶シリコン中に添加する不純物濃度
を制御することによつて、所望の傾斜を持つた断
面形状を得ることができる。
実施例 ２
第５図に示すように、シリコン基板１上に
Si3N4膜９、厚さ160nｍのりんドーブ多結晶シリ
コン膜（りん濃度２×1021cm-3）１０および、厚
さ160nｍのノンドーブ多結晶シリコン膜１１を
積層して被着し、上記多結晶シリコン膜１０，１
１を、反応性スパツタエツチングによつてストラ
イプ状にパターニングする。なお、上記多結晶シ
リコン膜は、周知の減圧CVD法により、形成温
度を650℃として形成した。
水蒸気中において、750℃、４時間の熱処理を
行ない、上記多結晶シリコン膜１０，１１の表面
を酸化した。その結果、第５図に示すように、得
られたシリコン酸化膜１２によつて、断面は台形
（θ＝120°）となり、そのため、多結晶シリコン
膜６を全面に被着した後、異方性エツチングによ
つてパターニングを行つても、シリコン酸化膜１
２の側部においても、エツチング残り（第２図記
号７）が生ずることはなく、微細加工を高い精度
で行なうことが可能である。
本発明において、不純物濃度の分布は実施例１
に示したように、上部から下部へ向つて連続的に
高くなることが最も好ましい。しかし、実施例２
に示したように、不純物濃度が階段状に変化する
場合であつても、実質的に台形の断面を得ること
ができ、エツチング残りと断線の防止のためには
極めて有効である。
第４図から明らかなように、不純物濃度がほぼ
１×1019cm-3以下では酸化速度は実質的に増加せ
ず、側面の傾斜をゆるやかにする効果もないか
ら、多結晶シリコン膜下部の不純物濃度は、１×
1019cm-3以上であることが必要である。なお、不
純物濃度を上下方向に連続的に変えるには、下部
に不純物源を配置し、その上に多結晶シリコン膜
を被着して熱処理する、あるいは、不純物とシリ
コンを同時にCVDによつて被着させるなど種種
な方法を用いることができ、いずれの方法を用い
ても良好な結果を得ることができる。[Table] As is clear from Table 1, the higher the impurity concentration, the larger the angle θ becomes, and a gentler slope can be obtained. When processed under the above conditions, there is a relationship between the impurity concentration at the lower end and the angle θ as shown in Figure 4. Therefore, by controlling the impurity concentration added to polycrystalline silicon, the desired slope can be obtained. It is possible to obtain a cross-sectional shape with Example 2 As shown in FIG.
A Si 3 N 4 film 9, a 160 nm thick phosphorous doped polycrystalline silicon film (phosphorous concentration 2×10 21 cm -3 ) 10 and a 160 nm thick nondoped polycrystalline silicon film 11 are stacked and deposited. Polycrystalline silicon film 10,1
1 is patterned into stripes by reactive sputter etching. Note that the polycrystalline silicon film was formed by a well-known low pressure CVD method at a formation temperature of 650°C. Heat treatment was performed in water vapor at 750° C. for 4 hours to oxidize the surfaces of the polycrystalline silicon films 10 and 11. As a result, as shown in FIG. 5, the obtained silicon oxide film 12 has a trapezoidal cross section (θ=120°). Therefore, after depositing the polycrystalline silicon film 6 on the entire surface, Even if patterning is performed by chemical etching, the silicon oxide film 1
No etching residue (symbol 7 in FIG. 2) is generated on the side portions of 2, and microfabrication can be performed with high precision. In the present invention, the impurity concentration distribution is as follows in Example 1.
It is most preferable that the height increases continuously from the top to the bottom as shown in FIG. However, Example 2
As shown in FIG. 2, even when the impurity concentration changes stepwise, a substantially trapezoidal cross section can be obtained, which is extremely effective in preventing etching residue and disconnection. As is clear from Figure 4, when the impurity concentration is approximately 1×10 19 cm -3 or less, the oxidation rate does not substantially increase and there is no effect of making the slope of the side surface gentler. The impurity concentration is 1×
It needs to be 10 19 cm -3 or more. To change the impurity concentration continuously in the vertical direction, place an impurity source at the bottom and deposit a polycrystalline silicon film on top of it and heat treat it, or simultaneously coat the impurity and silicon by CVD. Various methods can be used, such as attaching the resin, and good results can be obtained using any of the methods.
第１図は等方性エツチングによつてアンダーカ
ツトが生ずることを説明するための模式図、第２
図は従来の方法によつてエツチング残りが生ずる
ことを示す模式図、第３図および第５図は、それ
ぞれ本発明の異なる実施例を示す図、第４図は、
多結晶シリコン膜下部の不純物濃度と側面の傾斜
角度の関係を示す曲線図である。
１……シリコン基板、２，５，８，１２……シ
リコン酸化膜、３，３′，３″，６，１０，１１…
…多結晶シリコン膜、４……マスク、７……エツ
チング残り、９……Si3N4膜。
Figure 1 is a schematic diagram to explain that undercuts occur due to isotropic etching;
The figure is a schematic diagram showing that etching residue is produced by the conventional method, Figures 3 and 5 are diagrams each showing different embodiments of the present invention, and Figure 4 is
FIG. 3 is a curve diagram showing the relationship between the impurity concentration at the bottom of the polycrystalline silicon film and the inclination angle of the side surface. 1... Silicon substrate, 2, 5, 8, 12... Silicon oxide film, 3, 3', 3'', 6, 10, 11...
...Polycrystalline silicon film, 4...mask, 7...etching residue, 9...Si 3 N 4 film.
Claims (1)
が上部の不純物濃度より高い多結晶シリコン膜を
酸化することにより、上記多結晶シリコン膜を覆
い、かつ下部の厚さが上部の厚さより大きいシリ
コン酸化膜を形成する工程を含むことを特徴とす
る半導体装置の製造方法。 ２ 上記多結晶シリコン膜内の上記不純物濃度
は、上部から下部へ連続的に高くなつている特許
請求の範囲第１項記載の半導体装置の製造方法。 ３ 上記多結晶シリコン膜内の上記不純物濃度
は、上部から下部へ段階的に高くなつている特許
請求の範囲第１項記載の半導体装置の製造方法。[Claims] 1. Oxidizing a polycrystalline silicon film that has a desired shape and has a lower impurity concentration higher than an upper impurity concentration, thereby covering the polycrystalline silicon film and reducing the thickness of the lower part. 1. A method of manufacturing a semiconductor device, comprising the step of forming a silicon oxide film having a thickness greater than that of an upper portion. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the impurity concentration in the polycrystalline silicon film increases continuously from the top to the bottom. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the impurity concentration in the polycrystalline silicon film increases stepwise from the top to the bottom.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10382782A JPS58222527A (en) | 1982-06-18 | 1982-06-18 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10382782A JPS58222527A (en) | 1982-06-18 | 1982-06-18 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58222527A JPS58222527A (en) | 1983-12-24 |
| JPH0416939B2 true JPH0416939B2 (en) | 1992-03-25 |
Family
ID=14364244
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10382782A Granted JPS58222527A (en) | 1982-06-18 | 1982-06-18 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58222527A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2827041B1 (en) * | 2001-07-03 | 2003-12-12 | Commissariat Energie Atomique | PIEZORESISTIVE DEVICE AND METHODS OF MAKING THE DEVICE |
-
1982
- 1982-06-18 JP JP10382782A patent/JPS58222527A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58222527A (en) | 1983-12-24 |
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