JPH04163907A - Semiconductor substrate - Google Patents
Semiconductor substrateInfo
- Publication number
- JPH04163907A JPH04163907A JP29119390A JP29119390A JPH04163907A JP H04163907 A JPH04163907 A JP H04163907A JP 29119390 A JP29119390 A JP 29119390A JP 29119390 A JP29119390 A JP 29119390A JP H04163907 A JPH04163907 A JP H04163907A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- substrate
- film
- hydrofluoric acid
- element forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 63
- 239000004065 semiconductor Substances 0.000 title claims description 8
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims abstract description 34
- 230000001681 protective effect Effects 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 abstract description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 8
- 230000002093 peripheral effect Effects 0.000 abstract description 8
- 229910052710 silicon Inorganic materials 0.000 abstract description 8
- 239000010703 silicon Substances 0.000 abstract description 8
- 239000000428 dust Substances 0.000 abstract description 4
- 238000011109 contamination Methods 0.000 abstract description 3
- 239000010453 quartz Substances 0.000 abstract description 2
- 239000010410 layer Substances 0.000 abstract 11
- 235000012239 silicon dioxide Nutrition 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract 3
- 239000000377 silicon dioxide Substances 0.000 abstract 3
- 229910052682 stishovite Inorganic materials 0.000 abstract 3
- 229910052905 tridymite Inorganic materials 0.000 abstract 3
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 239000011241 protective layer Substances 0.000 abstract 1
- 229920006268 silicone film Polymers 0.000 abstract 1
- 229960002050 hydrofluoric acid Drugs 0.000 description 13
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 12
- 238000000034 method Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000010306 acid treatment Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000005498 polishing Methods 0.000 description 3
- YCIMNLLNPGFGHC-UHFFFAOYSA-N catechol Chemical compound OC1=CC=CC=C1O YCIMNLLNPGFGHC-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- PIICEJLVQHRZGT-UHFFFAOYSA-N Ethylenediamine Chemical compound NCCN PIICEJLVQHRZGT-UHFFFAOYSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000002378 acidificating effect Effects 0.000 description 1
- 239000012670 alkaline solution Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Element Separation (AREA)
- Weting (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
絶縁膜の上に素子形成層を設けた半導体基板に関し、
フン酸処理を行っても素子形成層の周縁の接着状態を変
化させないことを目的とし、
絶縁層の上に形成した素子形成層と、少なくとも前記絶
縁層の側部を覆う耐フン酸性保ｉｔｓとを含み構成する
。[Detailed Description of the Invention] [Summary] Regarding a semiconductor substrate in which an element formation layer is provided on an insulating film, the purpose of this invention is to prevent the adhesion state of the periphery of the element formation layer from changing even when subjected to hydrochloric acid treatment. The structure includes an element forming layer formed on the layer, and a hydrochloric acid-resistant insulating film that covers at least the side portions of the insulating layer.
〔産業上の利用分野］
本発明は、半導体基板に関し、より詳しくは、絶縁膜の
上に素子形成層を設けた半導体基板に関する。[Industrial Application Field] The present invention relates to a semiconductor substrate, and more particularly to a semiconductor substrate in which an element formation layer is provided on an insulating film.
Ｓ Ｏｒ （ｓｉｌｉｃｏｎ ｏｎ １ｎｓｕｌａｔｏ
ｒ）基板を形成する場合には、例えば第３図（ａ）〜（
ｃ）に示すように、シリコン支持基板１の表面に形成し
たＳｉＯ□膜２の上にシリコンよりなる素子形成基板３
を貼合わせ、この後に素子形成基板３を数μｍ以下に薄
層化するという方法が提案されている。S Or (silicon on 1nsulato
r) When forming a substrate, for example, FIGS. 3(a) to (
As shown in c), an element forming substrate 3 made of silicon is placed on the SiO□ film 2 formed on the surface of the silicon support substrate 1.
A method has been proposed in which the element forming substrate 3 is laminated to a thickness of several μm or less.
ところで、支持基板ｌ及び素子形成基板３は、予め面取
り処理が施されており、取扱中にそれらの縁部に欠けが
生じないように処理されている。Incidentally, the supporting substrate 1 and the element forming substrate 3 are chamfered in advance to prevent their edges from being chipped during handling.
このため、薄層化された素子形成基板３の周縁はＳｉＯ
□膜２から浮き上がった状態となり、僅かな衝撃により
その周縁部が欠けてしまうことになる。Therefore, the periphery of the thinned element forming substrate 3 is made of SiO
□It will be in a state where it is lifted from the membrane 2, and its peripheral edge will be chipped by a slight impact.
そして、この欠けが素子形成工程において発生すると、
その塵埃が素子形成基板３表面に付着し、これが素子形
成基板３の上に形成される膜にピンホールを発生させる
原因になる。If this chipping occurs during the element formation process,
The dust adheres to the surface of the element forming substrate 3, which causes pinholes to be generated in the film formed on the element forming substrate 3.
このため、Ｓ○■蟇板の周面を面取りして素子形成基板
３の未接着部分を除去したものが、特開昭６１−２５６
６２１号公報、特開平１−２２７４４１号公報において
提案されている（第３図（ｄ））。For this reason, JP-A-61-256 discloses a method in which the peripheral surface of the S○■ toad plate is chamfered and the unbonded portion of the element forming substrate 3 is removed.
This method has been proposed in Japanese Patent Publication No. 621 and Japanese Unexamined Patent Publication No. 1-227441 (FIG. 3(d)).
しかし、このようなＳ○■基板においは、その側部から
ＳｉＯ□１！！２が露出しているために、半導体素子を
形成する過程で使用されるフッ酸によってＳｉＯ□膜２
が側方からエツチングされ、素子形成基板３の周囲に再
び未接着部分が形成されてしまうといった問題が生じる
。However, this S○■ substrate smell comes from the sides of the SiO□1! ! Because SiO□ film 2 is exposed, hydrofluoric acid used in the process of forming semiconductor elements
A problem arises in that the wafer is etched from the side, and an unbonded portion is again formed around the element forming substrate 3.
本発明はこのような問題に鑑みてなされたものであって
、フン酸処理を行っても素子形成層の周縁の接着状態を
変化させないことができる半導体基板を提供することを
目的とする。The present invention has been made in view of these problems, and an object of the present invention is to provide a semiconductor substrate in which the adhesion state of the periphery of an element formation layer does not change even when subjected to hydrochloric acid treatment.
上記した課題は、第１図に例示するように、絶縁層１２
の上に形成した素子形成層Ｉ３と、少なくとも前記絶縁
層１２の側部を覆う耐フツ酸性保護膜１４とを有するこ
とを特徴とする半導体基板によって達成する。The above problem is solved by the insulating layer 12 as illustrated in FIG.
This is achieved by using a semiconductor substrate characterized by having an element forming layer I3 formed thereon and a hydrofluoric acid-resistant protective film 14 covering at least the side portions of the insulating layer 12.
本発明によれば、基板の側部から露出する絶縁層１２を
耐フツ酸性の保ＷＥ膜１４によって覆っている。例えば
、ＳｔＯ□により絶縁膜１２を形成する場合には、多結
晶シリコン膜、窒化膜等を基板の側部に形成するように
する。According to the present invention, the insulating layer 12 exposed from the side of the substrate is covered with the hydrofluoric acid-resistant WE retaining film 14. For example, when forming the insulating film 12 using StO□, a polycrystalline silicon film, a nitride film, or the like is formed on the side of the substrate.
したがって、フッ酸処理の際に絶縁層１２の側部はエツ
チングされずに残り、素子形成層１３の未接着部分の発
生は防止されるため、素子形成層１３の周縁部は欠けに
くくなり、欠けによって発生する塵埃による基板の汚染
はなくなる。Therefore, during the hydrofluoric acid treatment, the side portions of the insulating layer 12 remain unetched, and the generation of unbonded portions of the element forming layer 13 is prevented, so the peripheral edge of the element forming layer 13 is less likely to chip. This eliminates contamination of the substrate due to dust generated by the process.
そこで、以下に本発明の詳細を図面に基づいて説明する
。Therefore, the details of the present invention will be explained below based on the drawings.
（ａ）本発明の第１実施例の説明
第１図は、本発明の第１実施例装置を示す断面図である
。(a) Description of the first embodiment of the present invention FIG. 1 is a sectional view showing an apparatus according to the first embodiment of the present invention.
図中符号ｌＯに示すＳＯＩ基板は、支持層１１表面のＳ
ｉＯ□層工２層上２シリコンよりなる素子形成層１３を
形成して構成されており、その側部から底面にかけた領
域には耐フツ酸性の保護膜１４、例えば多結晶シリコン
膜が形成されている。The SOI substrate indicated by the symbol lO in the figure has S on the surface of the support layer 11.
It is constructed by forming an element forming layer 13 made of two silicon layers on two layers of iO□, and a hydrofluoric acid-resistant protective film 14, for example, a polycrystalline silicon film, is formed in the region from the side to the bottom surface. ing.
このようなＳｏｌ基板１０において、素子形成層１３の
上に別なＳｉＯ□膜を積層してこれをフン酸によりエツ
チングする場合に、フッ酸によって支持層ｌｌ上のＳｉ
０１層１２がエツチングされることはなく、素子形成層
１３の周縁に未接着部分は生じない。In such a Sol substrate 10, when another SiO□ film is laminated on the element formation layer 13 and this is etched with hydrofluoric acid, the Si on the support layer ll is etched with hydrofluoric acid.
The 01 layer 12 is not etched, and no unbonded portions are formed around the periphery of the element forming layer 13.
特に、５ｉＯｚ層１２が、ドープした酸化膜である場合
にはその効果は大きくなる。In particular, the effect becomes greater when the 5iOz layer 12 is a doped oxide film.
したがって、例えば石英バスケット内にＳｏｌ基板１０
を収納する際に、僅かな衝撃が素子形成層１３の側部に
加わったとしても、その周縁部分が容易に欠けることは
ない。Therefore, for example, the Sol substrate 10 is placed in a quartz basket.
Even if a slight impact is applied to the side portions of the element forming layer 13 during storage, the peripheral edge portions will not be easily chipped.
なお、素子形成層１３の上に形成された膜をフッ酸によ
りエツチングする工程としては、例えば、ＭＯＳ）ラン
ジスタのゲート電極を形成した後にその両側の５ｉＯｚ
膜を除去する工程や、素子形成層１３に溝を形成してこ
の中にＳｉＯ□膜を充填する場合に、素子形成層の上の
積層されたＳｉ０ｇ膜を除去する工程等がある。Note that the step of etching the film formed on the element forming layer 13 with hydrofluoric acid is, for example, after forming the gate electrode of a MOS transistor, etching 5iOz on both sides thereof.
There is a step of removing the film, and a step of removing the Si0g film stacked on the element forming layer when a groove is formed in the element forming layer 13 and filled with the SiO□ film.
（ｂ）本発明の第２の実施例の説明
第２図は、本発明の第２実施例装置の製造工程を示す断
面図である。(b) Description of the second embodiment of the present invention FIG. 2 is a sectional view showing the manufacturing process of the second embodiment of the present invention.
まず、第２図に示すように、シリコンよりなる支持基板
１５の表面を熱酸化して５ｔ（ｈ膜１６を形成した後に
、シリコンよりなる素子形成基板１７をそのＳｉＯ□膜
１６に貼合わせ、約１０００℃の温度で加熱する（第２
図（ａ））。First, as shown in FIG. 2, after thermally oxidizing the surface of a support substrate 15 made of silicon to form a 5T (h film 16), an element forming substrate 17 made of silicon is bonded to the SiO□ film 16. Heat at a temperature of about 1000℃ (second
Figure (a)).
次に、素子形成基板１７を機械的・化学的に研磨して数
μｍ程度の厚さとなるように薄層化する。Next, the element forming substrate 17 is mechanically and chemically polished to be thinned to a thickness of about several μm.
これに続いて、素子形成基板１７の上にフォトレジスト
１８を塗布し、これを露光、現像して素子形成基板１７
のうち５ｉＯ１膜Ｉ６と接しない領域を露出させる（第
２図（ｂ））。Subsequently, a photoresist 18 is applied onto the element forming substrate 17, and this is exposed and developed to form a photoresist 18 on the element forming substrate 17.
Among them, a region not in contact with the 5iO1 film I6 is exposed (FIG. 2(b)).
この後に、フォトレジスト１８から露出した素子形成基
板１７の周縁をエツチングしてＳｉＯ□膜１６との未接
着部分を除去する（第２図（Ｃ））。この場合のエツチ
ングは、例えばエチレンジアミンとピロカテコールの混
合液のようなアルカリ系の溶液を用いたウェットエツチ
ング、或いはフッ素系のエツチングガスを用いた反応性
イオンエツチング法によって行い、ＳｉＯｚＭ １６に
対する選択性を確保する。Thereafter, the peripheral edge of the element forming substrate 17 exposed from the photoresist 18 is etched to remove the portion not bonded to the SiO□ film 16 (FIG. 2(C)). Etching in this case is performed by wet etching using an alkaline solution such as a mixed solution of ethylenediamine and pyrocatechol, or by reactive ion etching using a fluorine-based etching gas, to increase the selectivity for SiOzM 16. secure.
ついで、フォトレジスト１日を除去した後に、ＣＶＤ法
によって、支持基板１５、ＳｉＯ□膜１６及び素子形成
基板１７の露出面の全体に多結晶シリコン１１１９を形
成しく第２図（ｄ））、この後に、支持基板１５の上の
多結晶シリコンｌｌ１１９を研磨によって除去して素子
形成基板１７を露出させ、これによりＳＯＩ基板が完成
する（第２図（ｅ） ）。Next, after removing the photoresist for one day, polycrystalline silicon 1119 is formed on the entire exposed surfaces of the supporting substrate 15, the SiO□ film 16, and the element forming substrate 17 by the CVD method (FIG. 2(d)). Afterwards, the polycrystalline silicon 119 on the supporting substrate 15 is removed by polishing to expose the element forming substrate 17, thereby completing the SOI substrate (FIG. 2(e)).
以上のような工程を経て形成されたＳＯｒ基板において
は、素子形成基板１７の上面を除いた部分が多結晶シリ
コン膜に覆われており、素子形成基板１７の下のＳｉＯ
□膜１６の側部は多結晶シリコンＭ１９によって外部か
ら隔離される。In the SOr substrate formed through the steps described above, the parts other than the upper surface of the element formation substrate 17 are covered with a polycrystalline silicon film, and the SiO
□The sides of the membrane 16 are isolated from the outside by polycrystalline silicon M19.
この結果、素子形成基板１７に素子を形成する場合のフ
ッ酸処理の工程においてフッ酸によりＳｉＯ□Ｗ１．１
６がエツチングされることはなく、素子形成基板１７と
の未接着部分が生じない。As a result, in the process of hydrofluoric acid treatment when forming elements on the element forming substrate 17, SiO□W1.1
6 is not etched, and no portion is left unbonded to the element forming substrate 17.
（ｃ）本発明の第３実施例の説明
第３図は、本発明の第３実施例装置の製造工程を示す断
面図である。(c) Description of Third Embodiment of the Present Invention FIG. 3 is a sectional view showing the manufacturing process of a device according to a third embodiment of the present invention.
まず、第２実施例と同様にして、支持基板２１の回りに
形成されたＳｉＯ□＃２２と素子形成基板２３とを貼合
わせるとともに、素子形成基板２３を研磨して薄くする
（第３図（ａ））。First, in the same manner as in the second embodiment, the SiO□#22 formed around the supporting substrate 21 and the element forming substrate 23 are bonded together, and the element forming substrate 23 is polished to be thin (see FIG. 3). a)).
この後に、研摩砥石等を使用して、素子形成基板２３、
ＳｉＯ□膜２２及び支持基板２１の周縁部分を研磨して
面取りする（第３図（ｂ））。After this, using a grindstone or the like, the element forming substrate 23,
The peripheral edges of the SiO□ film 22 and the support substrate 21 are polished and chamfered (FIG. 3(b)).
この後に、第１実施例と同様にして、支持基板２１、
Ｓｉｎｇ膜２２及び素子形成基板２３の露出面全体に多
結晶シリコン膜２４を形成しく第３図（Ｃ））、この後
に、支持基板２１の上の多結晶シリコン膜２４を研磨に
よって除去し、素子形成基板２３を露出させる（第３図
（ｄ））。After this, in the same manner as in the first embodiment, the support substrate 21,
A polycrystalline silicon film 24 is formed on the entire exposed surface of the Sing film 22 and the element formation substrate 23 (FIG. 3(C)). After this, the polycrystalline silicon film 24 on the support substrate 21 is removed by polishing, and the element formation substrate 23 is removed by polishing. The formation substrate 23 is exposed (FIG. 3(d)).
以上のような工程によって形成されたＳｏｌ基板は、第
１実施例と同じく、素子形成基板２４の下の５ｆＯＪ１
２２の側部が耐フン酸性のある多結晶シリコンｌ！２４
によって保護されることになる。The Sol substrate formed by the above steps is similar to the first embodiment, with the 5fOJ1 under the element forming substrate 24
The side part of 22 is made of polycrystalline silicon that is resistant to hydrochloric acid! 24
will be protected by.
（ｄ）その他の実施例の説明
上記した実施例では、耐フツ酸性の保護膜として多結晶
シリコン膜を形成したが、シリコン窒化膜、スパッタ法
によるシリコン膜等を用いてもよい。(d) Description of other embodiments In the embodiments described above, a polycrystalline silicon film was formed as a hydrofluoric acid-resistant protective film, but a silicon nitride film, a silicon film formed by sputtering, or the like may also be used.
また、上記した実施例では、支持層と素子形成層の間の
ＳｉＯ□膜を耐フツ酸性保護膜によって覆う場合につい
て説明したが、この他の例としては、ガラスよりなる支
持層の上にシリコン素子形成層を形成して基板を構成す
る場合に、そのガラス支持層のＰ′Ｉ囲を耐フツ酸性保
護膜で覆うと、ガラス支持層の側部がフッ酸によりエツ
チングされることが阻止され、素子形成層に未接着部分
が生じなくなる。Further, in the above embodiment, a case was explained in which the SiO When forming a substrate by forming an element forming layer, covering the P'I area of the glass support layer with a hydrofluoric acid-resistant protective film prevents the sides of the glass support layer from being etched by hydrofluoric acid. , there will be no unbonded portions in the element forming layer.
〔発明の効果］
以上述べたように本発明によれば、基板の側部から露出
する絶縁膜を耐フン酸性の保ｒ！ＩＷＩによって覆うよ
うにしたので、フン酸処理の際に絶縁層の側部はエツチ
ングされずに残り、素子形成層の未接着部分の発生は防
止されるため、素子形成層の周縁部は欠けにくくなり、
欠けによって発生する塵埃による基板の汚染を未然に防
止することができる。[Effects of the Invention] As described above, according to the present invention, the insulating film exposed from the side of the substrate can be kept fluoric acid resistant! Since it is covered with IWI, the sides of the insulating layer remain unetched during the hydrochloric acid treatment, and the generation of unbonded parts of the element forming layer is prevented, so the peripheral edge of the element forming layer is less likely to chip. Become,
It is possible to prevent contamination of the substrate due to dust generated by chipping.
第１図は、本発明の第１実施例装置を示す断面図、
第２図は、本発明の第２実施例装置の製造工程を示す断
面図、
第３図は、本発明の第３実施例装置の製造工程を示す断
面図、
第４図は、従来装置の製造工程を示す断面図である。
（符号の説明）
１０・・・ＳＯＩ基板、
１１・・・支持層、
１２・・・ＳｉＯ□層（絶縁層）、
１３・・・素子形成層、
１４・・・多結晶シリコン膜（耐フン酸性保護膜）、１
５．２１・・・支持基板（支持層）、１６．２２・・・
ＳｉＯ□膜（絶縁膜）、１７．２３・・・素子形成基板
（素子形成層）、１９．２４・・・多結晶シリコン膜
（耐フン酸性保護膜）。
出 願 人 富士通株式会社FIG. 1 is a cross-sectional view showing a device according to a first embodiment of the present invention, FIG. 2 is a cross-sectional view showing the manufacturing process of a device according to a second embodiment of the present invention, and FIG. FIG. 4 is a cross-sectional view showing the manufacturing process of the example device. FIG. 4 is a cross-sectional view showing the manufacturing process of the conventional device. (Explanation of symbols) 10...SOI substrate, 11...Supporting layer, 12...SiO□ layer (insulating layer), 13...Element formation layer, 14...Polycrystalline silicon film (foul resistant) acidic protective film), 1
5.21...Supporting substrate (supporting layer), 16.22...
SiO□ film (insulating film), 17.23... element forming substrate (element forming layer), 19.24... polycrystalline silicon film (hydrochloric acid-resistant protective film). Applicant Fujitsu Limited
Claims (1)
保護膜（１４）とを有することを特徴とする半導体基板
。[Claims] The device is characterized by comprising an element forming layer (13) formed on the insulating layer (12), and a hydrofluoric acid-resistant protective film (14) that covers at least the side portions of the insulating layer (12). A semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29119390A JPH04163907A (en) | 1990-10-29 | 1990-10-29 | Semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29119390A JPH04163907A (en) | 1990-10-29 | 1990-10-29 | Semiconductor substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04163907A true JPH04163907A (en) | 1992-06-09 |
Family
ID=17765666
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29119390A Pending JPH04163907A (en) | 1990-10-29 | 1990-10-29 | Semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04163907A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2769406A1 (en) * | 1997-10-06 | 1999-04-09 | Mitsubishi Electric Corp | SEMICONDUCTOR SUBSTRATE HAVING A BURIED OXIDE FILM AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE |
| EP1009021A1 (en) * | 1998-12-10 | 2000-06-14 | Siemens Aktiengesellschaft | Method and assembly for preventing formation of black silicon on edges of wafers |
| JP2007005596A (en) * | 2005-06-24 | 2007-01-11 | Seiko Epson Corp | Method for manufacturing semiconductor device |
| CN103560106A (en) * | 2013-11-22 | 2014-02-05 | 上海新傲科技股份有限公司 | Method for manufacturing semiconductor substrate with low warping degree |
| JPWO2012111616A1 (en) * | 2011-02-15 | 2014-07-07 | 住友電気工業株式会社 | Composite substrate with protective film and method for manufacturing semiconductor device |
| WO2015074479A1 (en) * | 2013-11-22 | 2015-05-28 | 上海新傲科技股份有限公司 | Low-warpage semiconductor substrate and method of preparing same |
| JP2019068011A (en) * | 2017-10-05 | 2019-04-25 | 株式会社東芝 | Semiconductor device |
-
1990
- 1990-10-29 JP JP29119390A patent/JPH04163907A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2769406A1 (en) * | 1997-10-06 | 1999-04-09 | Mitsubishi Electric Corp | SEMICONDUCTOR SUBSTRATE HAVING A BURIED OXIDE FILM AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE |
| US6150696A (en) * | 1997-10-06 | 2000-11-21 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor substrate and method of fabricating semiconductor device |
| US6335267B1 (en) | 1997-10-06 | 2002-01-01 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor substrate and method of fabricating semiconductor device |
| EP1009021A1 (en) * | 1998-12-10 | 2000-06-14 | Siemens Aktiengesellschaft | Method and assembly for preventing formation of black silicon on edges of wafers |
| JP2007005596A (en) * | 2005-06-24 | 2007-01-11 | Seiko Epson Corp | Method for manufacturing semiconductor device |
| JP4613709B2 (en) * | 2005-06-24 | 2011-01-19 | セイコーエプソン株式会社 | Manufacturing method of semiconductor device |
| JPWO2012111616A1 (en) * | 2011-02-15 | 2014-07-07 | 住友電気工業株式会社 | Composite substrate with protective film and method for manufacturing semiconductor device |
| CN103560106A (en) * | 2013-11-22 | 2014-02-05 | 上海新傲科技股份有限公司 | Method for manufacturing semiconductor substrate with low warping degree |
| WO2015074479A1 (en) * | 2013-11-22 | 2015-05-28 | 上海新傲科技股份有限公司 | Low-warpage semiconductor substrate and method of preparing same |
| US20160372424A1 (en) * | 2013-11-22 | 2016-12-22 | Shanghai Simgui Tehcnology Co., Ltd. | Low-warpage semiconductor substrate and method for preparing same |
| US20170018454A1 (en) * | 2013-11-22 | 2017-01-19 | Shanghai Simgui Tehcnology Co., Ltd. | Method for preparing low-warpage semiconductor substrate |
| JP2019068011A (en) * | 2017-10-05 | 2019-04-25 | 株式会社東芝 | Semiconductor device |
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