JPH04162454A - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPH04162454A JPH04162454A JP28636690A JP28636690A JPH04162454A JP H04162454 A JPH04162454 A JP H04162454A JP 28636690 A JP28636690 A JP 28636690A JP 28636690 A JP28636690 A JP 28636690A JP H04162454 A JPH04162454 A JP H04162454A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- board
- plate
- metal plate
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002184 metal Substances 0.000 claims abstract description 31
- 239000004065 semiconductor Substances 0.000 abstract description 22
- 239000000853 adhesive Substances 0.000 abstract description 6
- 230000001070 adhesive effect Effects 0.000 abstract description 6
- 239000011368 organic material Substances 0.000 abstract description 5
- 229910045601 alloy Inorganic materials 0.000 abstract description 2
- 239000000956 alloy Substances 0.000 abstract description 2
- 239000011347 resin Substances 0.000 description 9
- 229920005989 resin Polymers 0.000 description 9
- 230000008602 contraction Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Die Bonding (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は配線基板に半導体素子及び受動素子等の電子部
品を搭載した混成集積回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a hybrid integrated circuit device in which electronic components such as semiconductor elements and passive elements are mounted on a wiring board.
［従来の技術］
第４図は従来のこの種の混成集積回路装置を示す平面図
、第５図はそのＩＶ−ＩＶ線による断面図である。[Prior Art] FIG. 4 is a plan view showing a conventional hybrid integrated circuit device of this type, and FIG. 5 is a cross-sectional view thereof taken along the line IV--IV.
ガラスエポキシ等からなる配線基板１は平面視で矩形状
をなし、その端面に断面半円形状の複数のスルーホール
が配線基板１をその厚さ方向に貫通するようにして形成
されている。そして、前記スルーホールの内面にはスル
ーホール電極２が被着形成されている。配線基板１の上
面の中央部には矩形状の第１の凹部が形成されており、
更にこの第１の凹部の底面の中央部には矩形状の第２の
凹部が形成されている。前記第１の凹部の底面の周縁部
上には配線パターン６が設けられていて、この配線パタ
ーン６はスルーホール電極２に電気的に接続されている
。半導体素子（又は受動素子）４は前記第２の凹部の底
面の中央部上に導電性又は絶縁性の接着剤７を介して搭
載されており、この接着剤７を加熱して硬化させること
により配線基板１と半導体素子４とが相互に機械的に固
定されている。半導体素子４の上面に設けられた電極（
図示せず）と配線パターン６との間には、ワイヤボンデ
ィング法により金属細線５が設けられており、これによ
り双方が電気的に接続されている。A wiring board 1 made of glass epoxy or the like has a rectangular shape in plan view, and a plurality of through holes each having a semicircular cross section are formed in the end face thereof so as to penetrate through the wiring board 1 in its thickness direction. A through-hole electrode 2 is formed on the inner surface of the through-hole. A rectangular first recess is formed in the center of the upper surface of the wiring board 1.
Furthermore, a rectangular second recess is formed in the center of the bottom surface of the first recess. A wiring pattern 6 is provided on the peripheral edge of the bottom surface of the first recess, and this wiring pattern 6 is electrically connected to the through-hole electrode 2. The semiconductor element (or passive element) 4 is mounted on the center of the bottom of the second recess via a conductive or insulating adhesive 7, and by heating and curing this adhesive 7. Wiring board 1 and semiconductor element 4 are mechanically fixed to each other. The electrode provided on the top surface of the semiconductor element 4 (
A thin metal wire 5 is provided between the wiring pattern 6 (not shown) and the wiring pattern 6 by a wire bonding method, thereby electrically connecting the two.
また、配線基板１の前記第１及び第２の凹部内に外装樹
脂を注入した後、これを凝固させて外装樹脂層３を形成
することにより、半導体素子４が気密約に封止されてい
る。Further, by injecting an exterior resin into the first and second recesses of the wiring board 1 and solidifying it to form an exterior resin layer 3, the semiconductor element 4 is hermetically sealed. .
このように構成される混成集積回路装置においては、半
導体素子４は外装樹脂層３により電気的且つ機械的に保
護されている。また、半導体素子４は金属細線５、配線
パターン６及びスルーホール電極２を介して外部に電気
的に引き出されている。In the hybrid integrated circuit device configured as described above, the semiconductor element 4 is electrically and mechanically protected by the outer resin layer 3. Furthermore, the semiconductor element 4 is electrically led out to the outside via the thin metal wire 5, the wiring pattern 6, and the through-hole electrode 2.
［発明が解決しようとする課題］
しかしながら、上述した従来の混成集積回路装置におい
ては、配線基板１はガラスエポキシ等の有機材料等によ
り構成されており、その熱伝導率が約０．０００４ｃａ
ｌ／ｓｅｅ ＠ ｃｒｎ ＊ ’Ｃであって熱抵抗が大
きいため、この配線基板１上に消費電力が比較的大きな
半導体素子４及び受動素子等の電子部品を搭載すること
ができないという問題点がある。[Problems to be Solved by the Invention] However, in the conventional hybrid integrated circuit device described above, the wiring board 1 is made of an organic material such as glass epoxy, and its thermal conductivity is about 0.0004 ca.
l/see @ crn * 'C and has a large thermal resistance, so there is a problem that electronic components such as semiconductor elements 4 and passive elements, which consume relatively large power, cannot be mounted on this wiring board 1. .
また、有機材料等からなる配線基板１は熱膨張係数カ月
５Ｘ １０−”乃至２０ＸｌＯ−”／’Ｃであるのに対
し、外装樹脂層３は熱膨張係数が２５Ｘ １０−６乃至
３０×１０−”／’Ｃであるため、双方の熱膨張係数の
差による熱収縮力により混成集積回路装置に機械的歪み
が生じやすい。これにより、配線基板１が反り返ると、
混成集積回路装置を実装することが困難になるという問
題点がある。なお、このような配線基板１の反り返りは
、配線基板１を大きくするにつれて拡大される。Further, the wiring board 1 made of an organic material or the like has a thermal expansion coefficient of 5X 10-" to 20XlO-"/'C, whereas the outer resin layer 3 has a thermal expansion coefficient of 25X 10-6 to 30X10-"/'C. ''/'C, mechanical distortion is likely to occur in the hybrid integrated circuit device due to the thermal contraction force caused by the difference in the coefficient of thermal expansion between the two.As a result, when the wiring board 1 is warped,
There is a problem that it becomes difficult to implement the hybrid integrated circuit device. Note that such warpage of the wiring board 1 increases as the wiring board 1 becomes larger.
本発明はかかる問題点に鑑みてなされたものであって、
従来よりも消費電力が大きな電子部品を搭載することが
できると共に、配線基板が変形することを防止できる混
成集積回路装置を提供することを目的とする。The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a hybrid integrated circuit device that can mount electronic components that consume more power than conventional devices and that can prevent a wiring board from deforming.
［課題を解決するための手段］
本発明に係る混成集積回路装置は、配線基板に埋設され
た金属板と、前記金属板に到達する開口部を前記配線基
板に設けた後に前記開口部内の前記金属板上に搭載され
た電子部品とを有することを特徴とする。[Means for Solving the Problems] A hybrid integrated circuit device according to the present invention includes a metal plate embedded in a wiring board, and an opening in the opening that reaches the metal plate after the wiring board is provided with an opening that reaches the metal plate. It is characterized by having an electronic component mounted on a metal plate.
［作用］
本発明においては、半導体素子及び受動素子等の電子部
品は金属板上に搭載されている。この金属板は有機材料
等からなる配線基板に比して熱抵抗が小さく、前記電子
部品に発生した熱を効率良く放散することができる。従
って、従来のように配線基板上に電子部品を搭載する場
合とは異なって、消費電力が更に一層大きな電子部品を
搭載することができる。[Function] In the present invention, electronic components such as semiconductor elements and passive elements are mounted on a metal plate. This metal plate has a lower thermal resistance than a wiring board made of an organic material or the like, and can efficiently dissipate heat generated in the electronic component. Therefore, unlike the conventional case where electronic components are mounted on a wiring board, it is possible to mount electronic components with even higher power consumption.
また、配線基板には前記金属板が埋設されているため、
前記配線基板の機械的強度を向上させることができる。In addition, since the metal plate is embedded in the wiring board,
The mechanical strength of the wiring board can be improved.
このため、外装樹脂層により前記電子部品を封止した場
合、前記配線基板と外装樹脂層との間の熱膨張係数の差
によって混成集積回路装置に熱収縮力が生じても、この
熱収縮力により前記配線基板が変形することを防止でき
る。これにより、混成集積回路装置に実装上の不都合が
生じることを防止できる。Therefore, when the electronic component is sealed with an exterior resin layer, even if a thermal contraction force is generated in the hybrid integrated circuit device due to the difference in thermal expansion coefficient between the wiring board and the exterior resin layer, this thermal contraction force This can prevent the wiring board from deforming. This can prevent mounting problems from occurring in the hybrid integrated circuit device.
［実施例］
次に、本発明の実施例について添付の図面を参照して説
明する。[Example] Next, an example of the present invention will be described with reference to the accompanying drawings.
第１図は本発明の第１の実施例に係る混成集積回路装置
を示す平面図、第２図はそのＩ−Ｉ線による断面図であ
る。FIG. 1 is a plan view showing a hybrid integrated circuit device according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line I--I.
有機材料等からなる配線基板１は平面視で矩形状をなし
、その端面に断面半円形状の複数のスルーホールが配線
基板１をその厚さ方向に貫通するようにして形成されて
いる。そして、前記スルーホールの内面にはスルーホー
ル電極２が被着形成されている。配線基板１の内層には
、多層プリント基板の製造技術により、４２合金（Ｎｉ
；４２重量％、Ｆｅ；残部）又はＣｕ合金等からなる金
属板８が埋設されている。この金属板８はその熱伝導率
が例えば約０．０４乃至０．４ｃａｌ／ｓｅｅ ＠ｃｍ
＠ °Ｃである。A wiring board 1 made of an organic material or the like has a rectangular shape in plan view, and a plurality of through holes each having a semicircular cross section are formed in the end face thereof so as to penetrate through the wiring board 1 in the thickness direction. A through-hole electrode 2 is formed on the inner surface of the through-hole. The inner layer of the wiring board 1 is made of 42 alloy (Ni
A metal plate 8 made of 42% by weight, Fe (balance) or a Cu alloy is embedded. This metal plate 8 has a thermal conductivity of, for example, about 0.04 to 0.4 cal/see @cm.
@°C.
配線基板１の上面の中央部には矩形状の凹部が形成され
ている。更に、この凹部の底面の中央部には、金属板８
に達する矩形状の開口部が形成されている。前記凹部の
底面の周縁部上には配線パターン６が設けられていて、
この配線パターン６はスルーホール電極２に電気的に接
続されている。A rectangular recess is formed in the center of the upper surface of the wiring board 1 . Furthermore, a metal plate 8 is placed in the center of the bottom of this recess.
A rectangular opening reaching . A wiring pattern 6 is provided on the peripheral edge of the bottom surface of the recess,
This wiring pattern 6 is electrically connected to the through-hole electrode 2.
なお、スルーホール電極２及び配線パターン６は、Ｃｕ
箔等を下地とした電気メツキ法によって、配置線基板１
にＣｕメツキを施すことにより例えば約３０乃至３５μ
ｍ（Ｃｕ箔の厚さを含む）の厚さで形成するこ吉ができ
る。また、金属細線５が接続される部分の配線パターン
６上には、メツキ処理により厚さが例えば約５乃至８μ
ｍのＮｉメツキ層及び厚さが例えば約０．３乃至０，５
μｍのＡｕメツキ層を設ける。これにより、配線抵抗を
低減することができる。半導体素子（又は受動素子）４
は前記開口部内に露出した金属板８上に接着剤７を介し
て搭載されており、この接着剤７を例えば約１５０乃至
２００°Ｃに加熱して硬化させることにより、金属板８
と半導体素子４とが相互に機械的に固定されている。半
導体素子４の上面に設けられた電極（図示せず）と配線
パターン６との間には、ワイヤボンディング法により直
径が例えば約２５乃至３０μｍの金属細線５が設けられ
ており、これにより双方が電気的に接続されている。ま
た、ボッティング法又はトランスファモールド法等によ
り配線基板１の前記凹部内及び前記開口部内に外装樹脂
を注入した後、これを凝固させて外装樹脂層３を形成す
ることにより、半導体素子４が気密的に封止されている
。Note that the through-hole electrode 2 and the wiring pattern 6 are made of Cu.
Layout line board 1 is formed by electroplating using foil or the like as a base.
For example, by applying Cu plating to about 30 to 35μ
A kokichi can be formed with a thickness of m (including the thickness of the Cu foil). Furthermore, the thickness of the wiring pattern 6 at the portion to which the thin metal wire 5 is connected is, for example, approximately 5 to 8 μm by plating.
m of the Ni plating layer and the thickness is, for example, about 0.3 to 0.5 m.
A μm thick Au plating layer is provided. Thereby, wiring resistance can be reduced. Semiconductor element (or passive element) 4
is mounted on the metal plate 8 exposed in the opening via an adhesive 7, and by heating and curing the adhesive 7 to, for example, about 150 to 200°C, the metal plate 8
and semiconductor element 4 are mechanically fixed to each other. A thin metal wire 5 having a diameter of, for example, about 25 to 30 μm is provided between the electrode (not shown) provided on the upper surface of the semiconductor element 4 and the wiring pattern 6 by a wire bonding method. electrically connected. Furthermore, by injecting an exterior resin into the recess and the opening of the wiring board 1 by a botting method, a transfer molding method, or the like, and solidifying this to form an exterior resin layer 3, the semiconductor element 4 is airtight. is sealed.
本実施例においては、半導体素子４は接着剤７を介して
金属板８上に搭載されており、この金属板８はその熱伝
導率が約０．０４乃至０．４ｃａｌ／ｓｅｃ ＠ｃｍ
＊°Ｃであって熱抵抗が小さく、半導体素子４に発生し
た熱を効率良く放散することができる。このため、熱伝
導率が約０．０００４ｃａｌ／ｓｅｅ ＊ Ｃｍ ＊
°Ｃの配線基板上に半導体素子を搭載する従来の混成集
積回路装置とは異なって、本発明に係る混成集積回路装
置は消費電力が更に一層大きな半導体素子（又は受動素
子）４を搭載することができる。In this embodiment, the semiconductor element 4 is mounted on a metal plate 8 via an adhesive 7, and this metal plate 8 has a thermal conductivity of about 0.04 to 0.4 cal/sec @cm.
*°C, has low thermal resistance, and can efficiently dissipate heat generated in the semiconductor element 4. Therefore, the thermal conductivity is approximately 0.0004 cal/see * Cm *
Unlike the conventional hybrid integrated circuit device which mounts a semiconductor element on a wiring board at 30°C, the hybrid integrated circuit device according to the present invention mounts a semiconductor element (or passive element) 4 with even higher power consumption. I can do it.
また、配線基板１の内層には金属板８が埋設されている
ため、配線基板１の機械的強度を向上させることができ
る。このため、配線基板１と外装樹脂層３との間の熱膨
張係数の差によって混成集積回路装置に熱収縮力が生じ
ても、この熱収縮力により配線基板１が反り返ることを
防止できる。Further, since the metal plate 8 is embedded in the inner layer of the wiring board 1, the mechanical strength of the wiring board 1 can be improved. Therefore, even if thermal contraction force is generated in the hybrid integrated circuit device due to the difference in thermal expansion coefficient between wiring board 1 and exterior resin layer 3, wiring board 1 can be prevented from warping due to this thermal contraction force.
これにより、混成集積回路装置に実装上の不都合が生じ
ることを防止できる。This can prevent mounting problems from occurring in the hybrid integrated circuit device.
第３図は本発明の第２の実施例に係る混成集積回路装置
を示す断面図である。なお、本実施例は半導体素子を配
線基板の両面に搭載したものであるため、第３図におい
て第１図と同一物には同一符号を付してその部分の詳細
な説明は省略する。FIG. 3 is a sectional view showing a hybrid integrated circuit device according to a second embodiment of the present invention. Note that, in this embodiment, semiconductor elements are mounted on both sides of a wiring board, so in FIG. 3, the same parts as in FIG.
金属板８が埋設された配線基板１の上面及び下面の中央
部には夫々凹部が形成されており、更に前記各凹部の底
面の中央部には金属板８に達する開口部が形成されてい
る。そして、この各開口部内の金属板８上には半導体素
子４が固着されている。Recesses are formed in the center of the upper and lower surfaces of the wiring board 1 in which the metal plate 8 is embedded, and an opening reaching the metal plate 8 is formed in the center of the bottom of each recess. . A semiconductor element 4 is fixed onto the metal plate 8 within each opening.
本実施例によれば、配線基板１の両面に消費電力が従来
よりも大きな半導体素子４を搭載することができると共
に、熱収縮力により配線基板１が反り返ることを防止で
き、混成集積回路装置に実装上の不都合が生じることを
防止できる。According to this embodiment, it is possible to mount semiconductor elements 4 with larger power consumption than conventional ones on both sides of the wiring board 1, and it is also possible to prevent the wiring board 1 from warping due to thermal shrinkage force, making it possible to improve the hybrid integrated circuit device. Inconveniences in implementation can be prevented.
なお、本実施例においては、多層プリント基板の製造技
術により複数の金属板８及び複数の配線パターン６を配
線基板１に容易に埋設することができる。In this embodiment, a plurality of metal plates 8 and a plurality of wiring patterns 6 can be easily embedded in the wiring board 1 using multilayer printed circuit board manufacturing technology.
［発明の効果］
以上説明したように本発明によれば、配線基板に金属板
を埋設し、露出させた部分の前記金属板上に半導体素子
及び受動素子等の電子部品を搭載するから、電子部品に
発生する熱を効率良く放散することができる。従って、
本発明に係る混成集積回路装置は、消費電力が従来より
も大きな電子部品を搭載することができる。[Effects of the Invention] As explained above, according to the present invention, a metal plate is embedded in a wiring board, and electronic components such as semiconductor elements and passive elements are mounted on the exposed portion of the metal plate. Heat generated in parts can be efficiently dissipated. Therefore,
The hybrid integrated circuit device according to the present invention can mount electronic components whose power consumption is larger than that of conventional devices.
また、配線基板に金属板が埋設されているため、配線基
板の機械的強度を向上させることかでき、熱収縮力によ
る配線基板の変形を防止することができる。これにより
、混成集積回路装置に実装上の不都合が生じることを防
止できる。Furthermore, since the metal plate is embedded in the wiring board, the mechanical strength of the wiring board can be improved, and deformation of the wiring board due to thermal shrinkage force can be prevented. This can prevent mounting problems from occurring in the hybrid integrated circuit device.
第１図は本発明の第１の実施例に係る混成集積回路装置
を示す平面図、第２図はそのＩ−Ｉ線による断面図、第
３図は本発明の第２の実施例に係る混成集積回路装置を
示す断面図、第４図は従来のこの種の混成集積回路装置
を示す平面図、第５図はそのＩＶ−ＩＶ線による断面図
である。FIG. 1 is a plan view showing a hybrid integrated circuit device according to a first embodiment of the present invention, FIG. 2 is a sectional view taken along line I-I, and FIG. 3 is a plan view showing a hybrid integrated circuit device according to a second embodiment of the present invention. 4 is a plan view showing a conventional hybrid integrated circuit device of this type, and FIG. 5 is a sectional view taken along line IV--IV thereof.
Claims (1)
達する開口部を前記配線基板に設けた後に前記開口部内
の前記金属板上に搭載された電子部品とを有することを
特徴とする混成集積回路装置。(1) A metal plate embedded in a wiring board, and an electronic component mounted on the metal plate inside the opening after an opening reaching the metal plate is provided in the wiring board. hybrid integrated circuit device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28636690A JPH04162454A (en) | 1990-10-24 | 1990-10-24 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28636690A JPH04162454A (en) | 1990-10-24 | 1990-10-24 | Hybrid integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04162454A true JPH04162454A (en) | 1992-06-05 |
Family
ID=17703454
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28636690A Pending JPH04162454A (en) | 1990-10-24 | 1990-10-24 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04162454A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0661300A (en) * | 1991-08-08 | 1994-03-04 | Sun Microsyst Inc | Multichip module |
| JPH1117349A (en) * | 1997-06-27 | 1999-01-22 | Nec Corp | High-frequency integrated circuit device and manufacture thereof |
| JP2001110941A (en) * | 1999-10-06 | 2001-04-20 | Meito Chin | Semiconductor device |
-
1990
- 1990-10-24 JP JP28636690A patent/JPH04162454A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0661300A (en) * | 1991-08-08 | 1994-03-04 | Sun Microsyst Inc | Multichip module |
| JPH0748546B2 (en) * | 1991-08-08 | 1995-05-24 | サン・マイクロシステムズ・インコーポレーテッド | Multi-chip module |
| JPH1117349A (en) * | 1997-06-27 | 1999-01-22 | Nec Corp | High-frequency integrated circuit device and manufacture thereof |
| US5991162A (en) * | 1997-06-27 | 1999-11-23 | Nec Corporation | High-frequency integrated circuit device and manufacture method thereof |
| JP2001110941A (en) * | 1999-10-06 | 2001-04-20 | Meito Chin | Semiconductor device |
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