JPH04154383A - Horizontal synchronizing signal protecting circuit - Google Patents
Horizontal synchronizing signal protecting circuitInfo
- Publication number
- JPH04154383A JPH04154383A JP2279745A JP27974590A JPH04154383A JP H04154383 A JPH04154383 A JP H04154383A JP 2279745 A JP2279745 A JP 2279745A JP 27974590 A JP27974590 A JP 27974590A JP H04154383 A JPH04154383 A JP H04154383A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- signal
- frequency division
- timing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010355 oscillation Effects 0.000 claims description 9
- 230000005684 electric field Effects 0.000 abstract description 3
- 230000007257 malfunction Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 5
- 230000002776 aggregation Effects 0.000 description 1
- 238000004220 aggregation Methods 0.000 description 1
Landscapes
- Synchronizing For Television (AREA)
- Studio Circuits (AREA)
- Processing Of Color Television Signals (AREA)
Abstract
Description
【発明の詳細な説明】
°〔産業上の利用分野〕
本発明は、水平同期信号保護回路に関し、特にテレビジ
ョン表示画面上に時刻・チャンネルナンバ等の文字を表
示するオンスクリーン・キャラクタ・デイスプレィ用の
水平同期信号保護回路に関する。[Detailed Description of the Invention] ° [Field of Industrial Application] The present invention relates to a horizontal synchronization signal protection circuit, particularly for on-screen character displays that display characters such as time and channel numbers on a television display screen. This invention relates to a horizontal synchronization signal protection circuit.
従来、この種のオンスクリーン・キャラクタ・デイスプ
レィ回路においては、入力端子から入力される水平同期
入力信号が、他の入力端子から入力される水平方向タイ
ミング発生用クロックと共にテレビジョン表示画面上に
おける時刻、チャンネルナンバ等の文字表示の水平位1
を制御する水平方向出力タイミング発生回路に直接入力
され、水平方向の出力タイミングを制御する構成となっ
ていた。Conventionally, in this type of on-screen character display circuit, a horizontal synchronization input signal inputted from an input terminal, together with a horizontal timing generation clock inputted from another input terminal, determines the time on the television display screen. Horizontal position 1 of character display such as channel number
The signal was directly input to the horizontal output timing generation circuit that controlled the output timing in the horizontal direction.
上述した従来の回路においては、表示位置を制御する出
力タイミング発生回路に水平同期入力信号が直接入力さ
れる構成となっているため、水平同期入力信号に弱電界
等の影響により、同期信号の欠落やゆれが生じ、このよ
うな水平同期信号により水平方向出力タイミング発生回
路が誤動作して、テレビジョン表示画面上における文字
表示位置がずれたり、ゆれたりするという欠点がある。In the conventional circuit described above, the horizontal synchronization input signal is directly input to the output timing generation circuit that controls the display position, so the synchronization signal may be missing due to the influence of a weak electric field etc. on the horizontal synchronization input signal. Such a horizontal synchronizing signal causes the horizontal output timing generation circuit to malfunction, causing the character display position on the television display screen to shift or sway.
本発明の目的は、このような欠点を除き、同期信号の欠
落やゆれを除き、表示画面上の表示のずれをなくした水
平同期信号保護回路を提供するこ画面上に所定の文字、
絵などを表示するオンスクリーン・ディスプレイのタイ
ミングを出力する出力タイミング発生回路の前段に設け
られ水平同期信号の周波数f、の0倍の周波数で発振す
る発振回路と、この発振回路の8カをカウントする1次
可変分数カウンタと、この1次可変分周カウンタの出力
変化を前記水平同期信号と比較して判別するタイミング
判別回路と、このタイミング判別回路の判別結果を計数
する制御信号計数回路と、この制御信号計数回路の計数
結果により分周比を制御され前記発振回路の出力をカウ
ントする2次可変分周回路とを備え、この2次可変分周
カウンタで作られるダミー水平同期信号を前記出力タイ
ミング発生回路に入力することを特徴とする。An object of the present invention is to provide a horizontal synchronization signal protection circuit which eliminates such drawbacks, eliminates synchronization signal loss and fluctuation, and eliminates display deviations on a display screen.
There is an oscillation circuit that oscillates at a frequency 0 times the frequency f of the horizontal synchronization signal, which is installed before the output timing generation circuit that outputs the timing of the on-screen display that displays pictures, etc., and 8 circuits of this oscillation circuit are counted. a timing discrimination circuit that compares and discriminates the change in the output of the first variable frequency division counter with the horizontal synchronization signal; and a control signal counting circuit that counts the discrimination results of the timing discrimination circuit. and a secondary variable frequency divider circuit whose frequency division ratio is controlled by the counting result of the control signal counting circuit and counts the output of the oscillation circuit, and outputs a dummy horizontal synchronization signal generated by the secondary variable frequency divider counter. It is characterized by being input to a timing generation circuit.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例を示すブロック図であり、発
振回路10.1次可変分周カウンタ20.2次可変分周
カウンタ23、タイミング判別回路21、制御信号計数
回路22、出力タイミング発生回路25で構成される。FIG. 1 is a block diagram showing an embodiment of the present invention, including an oscillation circuit 10, a first variable frequency division counter 20, a second variable frequency division counter 23, a timing discrimination circuit 21, a control signal counting circuit 22, and an output timing. It is composed of a generating circuit 25.
また、発振回路10は、入力端子1からビデオ信号色副
搬送波を入力とし、ビデオ信号色副搬送波周波数の2倍
の周波数で発振する電圧制御発振器11を含み、この電
圧制御発振器11とビデオ信号色副搬送波との位相を一
致させるPLL手段となっている。The oscillation circuit 10 also includes a voltage controlled oscillator 11 that receives the video signal color subcarrier from the input terminal 1 and oscillates at a frequency twice the video signal color subcarrier frequency. This is a PLL means that matches the phase with the subcarrier.
ビデオ信号色副搬送波周波数をfsc、水平同期り、電
圧制御発振器11の周波数を2 X f scとしてい
るため周波数f)Iを作るためには455分周すれば水
平同期タイミングを得ることができる。Since the video signal color subcarrier frequency is fsc, horizontal synchronization, and the frequency of the voltage controlled oscillator 11 is 2×fsc, horizontal synchronization timing can be obtained by dividing the frequency by 455 to create the frequency f)I.
この455分周カウンタには1次可変分周カウンタ20
と、2次可変分周カウンタ23との2種類があり、それ
ぞれ454〜456分周までの分周比が変化可能とし、
分周比は分周比制御信号32〜35により制御される。This 455 frequency division counter has a primary variable frequency division counter of 20
There are two types, 1 and 23, and a secondary variable frequency division counter 23, each with a variable division ratio from 454 to 456,
The frequency division ratio is controlled by frequency division ratio control signals 32-35.
1次可変分周カウンタ20と2次分周カウンタ23とは
、初期設定用リセット端子3からのリセット信号により
リセットがかあり、その後電圧制御発振器11の出力を
カウントする。1次可変分周カウンタ2oは、水平同期
信号入力端子2がらの水平同期入力信号37とのタイミ
ング比較用信号31をタイミング判別回路21へ出力し
、このタイミング判別回路21は、水平同期入力信号3
7とタイミング比較用信号31とを比較する。連続M周
期(M;23.4・・・)以上水平同期入力信号37が
タイミング比較用信号31より早ければ、分周比を45
4に設定する分周比制御信号32を1次可変分周カウン
タ20へ出力し、以後1次可変分周カウンタ20は1回
454分周し、タイミング比較用信号31を早く出力さ
せる。The primary variable frequency division counter 20 and the secondary frequency division counter 23 are reset by a reset signal from the initial setting reset terminal 3, and then count the output of the voltage controlled oscillator 11. The primary variable frequency division counter 2o outputs a signal 31 for timing comparison with the horizontal synchronization input signal 37 from the horizontal synchronization signal input terminal 2 to the timing discrimination circuit 21, and this timing discrimination circuit 21
7 and the timing comparison signal 31 are compared. If the horizontal synchronization input signal 37 is earlier than the timing comparison signal 31 by more than M consecutive cycles (M; 23.4...), the frequency division ratio is set to 45.
The frequency division ratio control signal 32 set to 4 is output to the primary variable frequency division counter 20, and thereafter the primary variable frequency division counter 20 divides the frequency by 454 once to output the timing comparison signal 31 earlier.
同様に連続M周期以上水平同期入力信号37が、タイミ
ング比較用信号31より遅ければ、分周比を456に設
定する分周比制御信号33を1次可変分周カウンタへ出
力する。以後、1次可変分周カウンタ20は1回456
分周し、タイミング比較用信号31を遅く出力させる。Similarly, if the horizontal synchronization input signal 37 is slower than the timing comparison signal 31 for more than M continuous periods, a frequency division ratio control signal 33 that sets the frequency division ratio to 456 is output to the primary variable frequency division counter. After that, the primary variable frequency division counter 20 will be counted once as 456.
The frequency is divided and the timing comparison signal 31 is outputted later.
この動作により、タイミング比較用信号31は常に水平
同期入力信号の位夏を捕えることがてきる。This operation allows the timing comparison signal 31 to always capture the position of the horizontal synchronization input signal.
また、分周比制御信号32.33を入力とする制御信号
計数回路22は、分周比制御信号32゜33を計数し、
信号32が信号33の信号出力の無い間に2周期以上出
力されれば、分周比を454に設定する分周比制御信号
34を2次可変分層カウンタ23へ出力する。これ以後
、2次可変分周カウンタ23は1回454分周する。Further, the control signal counting circuit 22 which receives the frequency division ratio control signals 32 and 33 counts the frequency division ratio control signals 32 and 33,
If the signal 32 is output for two or more cycles while the signal 33 is not output, a frequency division ratio control signal 34 for setting the frequency division ratio to 454 is output to the secondary variable layer division counter 23. After this, the secondary variable frequency division counter 23 divides the frequency by 454 once.
同様に、制御信号計数回路22において、信号33が信
号32の信号出力の無い間に2周期以上出力されれば、
分周比を456に設定する分周比制御信号35を2次可
変分周カウンタ23へ出力し、以f! 2次可変分集カ
ウンタ23は1回456分周する。信号34.35が出
力されない時、2次可変分周カウンタ23は455分周
することになる。この動作により、2次可変分周カウン
タ23の出力であるダミー水平同期信号36のタイミン
グは水平同期入力信号37に一致し、さらに電圧制御発
振器11の(2Xfosc)の1/455分周出力であ
るため、水平同期入力信号37が欠落した場合でも正常
な出力をする。よって、ダミー水平同期信号36を入力
としている出力タイミング発生回路24において誤動作
の無い安定動作を得ることができる。Similarly, in the control signal counting circuit 22, if the signal 33 is output for two or more cycles while the signal 32 is not output,
The frequency division ratio control signal 35 that sets the frequency division ratio to 456 is output to the secondary variable frequency division counter 23, and then f! The secondary variable aggregation counter 23 divides the frequency by 456 once. When the signal 34.35 is not output, the secondary variable frequency dividing counter 23 will divide the frequency by 455. Due to this operation, the timing of the dummy horizontal synchronization signal 36, which is the output of the secondary variable frequency division counter 23, matches the horizontal synchronization input signal 37, and furthermore, the timing of the dummy horizontal synchronization signal 36, which is the output of the secondary variable frequency division counter 23, coincides with the horizontal synchronization input signal 37. Therefore, even if the horizontal synchronization input signal 37 is missing, normal output is performed. Therefore, stable operation without malfunction can be obtained in the output timing generation circuit 24 which receives the dummy horizontal synchronization signal 36 as input.
本実施例のタイミング図を第2図に示す。第2図(a>
は水平同期入力信号37が1次可変分周カウンタ20か
らのタイミング比較用信号31よりも早い場合の例であ
り、X印の状態がM周期以上続くと、分周比制御信号3
2を出力する。第2図(b)は水平同期入力信号37が
タイミング比較用信号31よりも遅い例である。第2図
(c)は分周比制御信号32.33と信号34.35の
関係を示す図であり、分周比制御信号32が2周期以上
出力される時に分周比制御信号34を、分周比制御信号
33が2周期以上出力される時に分周比制御信号35を
出力する。A timing diagram of this embodiment is shown in FIG. Figure 2 (a>
is an example in which the horizontal synchronization input signal 37 is earlier than the timing comparison signal 31 from the primary variable frequency division counter 20, and if the state of the X mark continues for more than M periods, the frequency division ratio control signal 3
Outputs 2. FIG. 2(b) is an example in which the horizontal synchronization input signal 37 is slower than the timing comparison signal 31. FIG. 2(c) is a diagram showing the relationship between the frequency division ratio control signal 32.33 and the signal 34.35. When the frequency division ratio control signal 32 is output for two or more cycles, the frequency division ratio control signal 34 is When the frequency division ratio control signal 33 is output for two or more cycles, the frequency division ratio control signal 35 is output.
タイミング判別回路21の計数Mにより、水平同期入力
信号のゆれ周期、欠落数に対応できる。The count M of the timing determination circuit 21 can correspond to the fluctuation period and number of omissions of the horizontal synchronization input signal.
以上説明したように本発明は、特にオンスクリーン・キ
ャラクタデイスプレィに使用した場合、弱電界等の影響
による水平同期入力信号のゆれや欠落が存在する状況下
においても、出力タイミング発生回路が安定なダミー水
平同期信号を出力するため、テレビジョン表示画面上に
おける文字表示位置かずれたり、ゆれたりしない見やす
い画面を得ることができる効果がある。As explained above, the present invention enables the output timing generation circuit to be stable even in situations where the horizontal synchronization input signal fluctuates or is missing due to the influence of weak electric fields, especially when used for on-screen character displays. Since the dummy horizontal synchronization signal is output, it is possible to obtain an easy-to-read screen that does not shift or shake the character display position on the television display screen.
第1図は本発明の一実施例のブロック図、第2図(a)
、(b)、(c)はそれぞれ前記一実施例におけるタイ
ミング図である。
1・・ビデオ信号色副搬送波入力端子、2・・・水平同
期信号入力端子、3・・初期状態設定端子、4・水平タ
イミング発生用クロック入力端子、5・出力端子、10
・・・発振回路(PLL手段)、11・電圧制御発振器
、12・・・分周器、13・位相比較器、14・・積分
器、21・ タイミング判別回路、22・・・制御信号
計数回路、232次可変分周カウンタ、24・・出力タ
イミング発生回路、31・・タイミング比較用信号、3
2〜35・・分周比制御信号、36・・ダミー水平同期
信号、37・・水平同期入力信号。Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2(a)
, (b) and (c) are timing diagrams in the above embodiment, respectively. 1. Video signal color subcarrier input terminal, 2. Horizontal synchronization signal input terminal, 3. Initial state setting terminal, 4. Clock input terminal for horizontal timing generation, 5. Output terminal, 10
...Oscillation circuit (PLL means), 11. Voltage controlled oscillator, 12.. Frequency divider, 13. Phase comparator, 14.. Integrator, 21. Timing discrimination circuit, 22.. Control signal counting circuit. , 232nd order variable frequency division counter, 24... Output timing generation circuit, 31... Timing comparison signal, 3
2 to 35: Frequency division ratio control signal, 36: Dummy horizontal synchronization signal, 37: Horizontal synchronization input signal.
Claims (1)
ーン・ディスプレイのタイミングを出力する出力タイミ
ング発生回路の前段に設けられ水平同期信号の周波数f
_Hのn倍の周波数で発振する発振回路と、この発振回
路の出力をカウントする1次可変分数カウンタと、この
1次可変分周カウンタの出力変化を前記水平同期信号と
比較して判別するタイミング判別回路と、このタイミン
グ判別回路の判別結果を計数する制御信号計数回路と、
この制御信号計数回路の計数結果により分周比を制御さ
れ前記発振回路の出力をカウントする2次可変分周回路
とを備え、この2次可変分周カウンタで作られるダミー
水平同期信号を前記出力タイミング発生回路に入力する
ことを特徴とする水平同期信号保護回路。The frequency f of the horizontal synchronizing signal is provided before the output timing generation circuit that outputs the timing of the on-screen display that displays predetermined characters, pictures, etc. on the display screen.
An oscillation circuit that oscillates at a frequency n times higher than _H, a primary variable fractional counter that counts the output of this oscillation circuit, and a timing for comparing the output change of this primary variable frequency division counter with the horizontal synchronization signal to determine the timing. a discrimination circuit; a control signal counting circuit that counts the discrimination results of the timing discrimination circuit;
and a secondary variable frequency divider circuit whose frequency division ratio is controlled by the counting result of the control signal counting circuit and counts the output of the oscillation circuit, and outputs a dummy horizontal synchronization signal generated by the secondary variable frequency divider counter. A horizontal synchronization signal protection circuit characterized in that it is input to a timing generation circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2279745A JPH04154383A (en) | 1990-10-18 | 1990-10-18 | Horizontal synchronizing signal protecting circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2279745A JPH04154383A (en) | 1990-10-18 | 1990-10-18 | Horizontal synchronizing signal protecting circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04154383A true JPH04154383A (en) | 1992-05-27 |
Family
ID=17615312
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2279745A Pending JPH04154383A (en) | 1990-10-18 | 1990-10-18 | Horizontal synchronizing signal protecting circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04154383A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR19990001545A (en) * | 1997-06-16 | 1999-01-15 | 윤종용 | Synchronization Signal Generator in Image Processing System |
US5929711A (en) * | 1997-01-30 | 1999-07-27 | Yamaha Corporation | PLL circuit with pseudo-synchronization control device |
JP2005223639A (en) * | 2004-02-05 | 2005-08-18 | Matsushita Electric Works Ltd | Image interphone device |
CN103248794A (en) * | 2013-05-06 | 2013-08-14 | 四川虹微技术有限公司 | Line-field synchronizing signal generating device with adjustable resolution |
-
1990
- 1990-10-18 JP JP2279745A patent/JPH04154383A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5929711A (en) * | 1997-01-30 | 1999-07-27 | Yamaha Corporation | PLL circuit with pseudo-synchronization control device |
KR19990001545A (en) * | 1997-06-16 | 1999-01-15 | 윤종용 | Synchronization Signal Generator in Image Processing System |
JP2005223639A (en) * | 2004-02-05 | 2005-08-18 | Matsushita Electric Works Ltd | Image interphone device |
CN103248794A (en) * | 2013-05-06 | 2013-08-14 | 四川虹微技术有限公司 | Line-field synchronizing signal generating device with adjustable resolution |
CN103248794B (en) * | 2013-05-06 | 2016-01-13 | 四川虹微技术有限公司 | The row field sync signal generation device that a kind of resolution is adjustable |
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