JPH04154133A - Prevention of short circuit of bonding wire - Google Patents

Prevention of short circuit of bonding wire

Info

Publication number
JPH04154133A
JPH04154133A JP2277840A JP27784090A JPH04154133A JP H04154133 A JPH04154133 A JP H04154133A JP 2277840 A JP2277840 A JP 2277840A JP 27784090 A JP27784090 A JP 27784090A JP H04154133 A JPH04154133 A JP H04154133A
Authority
JP
Japan
Prior art keywords
wire
insulating film
bonding
chip
bonding operation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2277840A
Other languages
Japanese (ja)
Inventor
Ryuichi Kyomasu
隆一 京増
Toshihiro Sato
佐藤　利博
Hisaki Yoshida
吉田　寿樹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kiyuuritsuku & Sofua Japan Kk
Original Assignee
Kiyuuritsuku & Sofua Japan Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kiyuuritsuku & Sofua Japan Kk filed Critical Kiyuuritsuku & Sofua Japan Kk
Priority to JP2277840A priority Critical patent/JPH04154133A/en
Publication of JPH04154133A publication Critical patent/JPH04154133A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/787—Means for aligning
    • H01L2224/78743—Suction holding means
    • H01L2224/78744—Suction holding means in the lower part of the bonding apparatus, e.g. in the apparatus chuck
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

PURPOSE:To prevent an electric short circuit in a process after a wire bonding operation and to eliminate a defect due to a wire by a method wherein, after the wire bonding operation, an insulating film is applied to the wire. CONSTITUTION:At an ordinary wire bonding operation, a bare bonding wire 2 on which an insulating film 1 has been formed is used and an IC chip 3 which has been fixed to a lead frame 4 is bonded. In this method, the surface of the wire 2 whose bonding operation has been finished is coated immediately with the insulating film 1. As a result, immediately after the bonding operation has been finished, a semiconductor device A including the chip 3 is sandwiched between a spray 6 and a vacuum suction apparatus 7, connected to a filter not shown in the figure, which have been installed in the upper part and the lower part. The semiconductor device A including the chip 3 is step-fed, and the insulating film 1 is applied to the wire 2 by using an insulating agent. At this time, an insulating-agent jet stream apparatus which executes the above operations collectively may be used without using the spray 6 and the like. Thereby, even sharp edges of the chip 3 and the frame 4 can be coated.

Description

【発明の詳細な説明】 〈産業上の利用分野〉 この発明は、ワイヤボンディング後の工程における電気
的短絡を防止することにより、不良の発生を防止する７
ためのボンディングワイヤの短絡防止方法に関する。[Detailed Description of the Invention] <Industrial Application Field> This invention prevents the occurrence of defects by preventing electrical short circuits in the process after wire bonding.
The present invention relates to a method for preventing short circuits in bonding wires.

〈従来の技術〉 近年、ＬＳＩの集積化に伴い、その組み立てにおけるワ
イヤの間隔が狭くなっているため、ループ曲がりやルー
プ垂れによるワイヤ間の短絡、ワイヤとリードフレーム
の間の短絡が問題となっている。具体的には、ワイヤボ
ンディング中にワイヤ間の短絡が発生する場合と、ワイ
ヤボンディング工程に続く工程で半導体装置を取り扱う
場合に短絡が発生するという問題である。<Prior art> In recent years, as LSIs have become more integrated, the spacing between wires in their assembly has become narrower, causing problems such as short circuits between wires due to loop bending or loop sagging, and short circuits between wires and lead frames. ing. Specifically, the problem is that a short circuit occurs between wires during wire bonding, and when a semiconductor device is handled in a process subsequent to the wire bonding process.

この問題を解決するため、従来は、表面を絶縁剤で被覆
したワイヤを用いてボンディングすることが行われてい
る。To solve this problem, bonding has conventionally been carried out using wires whose surfaces are coated with an insulating agent.

すなわち、第４図に示すように、予めワイヤの周面が絶
縁皮膜で被覆されている絶縁被覆ボンデイングワイヤ１
１を使用し、ボンディング時に一次側接続部１２と二次
側接続部１３の被覆を放電によるプラズマや、機械的手
法を用いて除去してからボンディングする方法である。That is, as shown in FIG. 4, an insulated bonding wire 1 whose peripheral surface is coated with an insulating film in advance
In this method, the coatings of the primary side connection part 12 and the secondary side connection part 13 are removed using plasma caused by discharge or a mechanical method, and then bonding is performed.

〈発明が解決しようとする課題〉 しかし、上記従来の方法においては、−次側接続部の被
覆の除去はボール形成時の電気放電により比較的容易に
行われるが、二次側接続部の被覆の除去については有効
な方法が知られていなかった。そこで、そのままこすり
つけて接合面からはみ出すことを期待する方法等が実験
されているが、接合の信頼性は被覆を完全に除去した場
合と比べて劣るものである。<Problems to be Solved by the Invention> However, in the above conventional method, the coating on the secondary side connection part is relatively easily removed by electric discharge during ball formation, but the coating on the secondary side connection part is removed relatively easily. No effective method was known for removing it. Therefore, experiments have been conducted to try to rub the coating as it is and expect it to protrude from the bonding surface, but the reliability of the bond is inferior to the case where the coating is completely removed.

また、被覆が除去されても、被覆を接合面から除去する
ことによって発生する皮膜等の塵埃を除去処理する必要
があるため、煩瑣な作業を強いられるとともに、作業に
時間がかかるという欠点があった。さらに、塵埃の除去
作業に長時間を要することから、高価な組み立て装置（
ワイヤボンダ）に遊休状態が発生することが避けられず
、装置の稼働能率が低下するという問題があった。In addition, even if the coating is removed, it is necessary to remove dust such as a film generated by removing the coating from the bonding surface, which has the disadvantage of being a tedious and time-consuming process. Ta. Furthermore, since it takes a long time to remove dust, expensive assembly equipment (
There is a problem in that the wire bonder (wire bonder) is unavoidably idle, and the operating efficiency of the device is reduced.

一方、現在では性能のよいワイヤボンダの開発により、
ワイヤボンディング工程における短絡の発生はきわめて
少なくなってきているのが現状であり、むしろワイヤボ
ンディング工程後の取り扱いの際に発生する短絡の防止
が課題とされている。On the other hand, with the development of high-performance wire bonders,
The current situation is that the occurrence of short circuits in the wire bonding process has become extremely rare, and rather the prevention of short circuits that occur during handling after the wire bonding process is an issue.

そこでこの発明は、上記従来技術の問題点に鑑み、ワイ
ヤ接合の信頼性を損なうことなく、ワイヤの短絡を完全
に、しかも容易に防止する方法を提供することを目的と
して発明されたものである。Therefore, in view of the above-mentioned problems of the prior art, the present invention was invented for the purpose of providing a method for completely and easily preventing wire short circuits without impairing the reliability of wire bonding. .

〈課題を解決するための手段〉 上記の目的を達成するために、この発明の方法は、ワイ
ヤボンディング後にボンディングワイヤに絶縁皮膜を形
成することを特徴としている。絶縁皮膜の形成は、絶縁
剤をスプレーで塗布する方法または要被覆部を被覆剤に
浸漬する方法によって行われる。また、ワイヤボンディ
ング後に、ＩＣチップ、リードフレーム及びボンディン
グワイヤの全体に絶縁皮膜を形成することも有効な手段
である。<Means for Solving the Problems> In order to achieve the above object, the method of the present invention is characterized in that an insulating film is formed on the bonding wire after wire bonding. The insulating film is formed by spraying an insulating agent or by dipping the portion to be coated in the coating agent. It is also an effective means to form an insulating film over the entire IC chip, lead frame, and bonding wire after wire bonding.

〈作用〉 上記手段は、ワイヤボンディング工程が終了した後に、
ボンディングワイヤ（またはＩＣチップ、リードフレー
ム及びボンディングワイヤ）に絶縁皮膜を被せる工程を
追加することによって実施される。ワイヤボンディング
工程で使用されるボンディングワイヤは被覆のない従来
のワイヤであり、ボンディング工程の後に絶縁剤を塗布
するだけであるから、作業も簡単であり、絶縁皮膜の形
成により短絡が有効に防止される。なお、半導体装置全
体に絶縁皮膜を形成すれば、ＩＣチップやリードフレー
ムの鋭いエツジがコーティングされるため、モールド時
にワイヤが擦られて、ワイヤに形成された皮膜が剥離す
ることもない。<Operation> The above means, after the wire bonding process is completed,
This is carried out by adding a step of covering the bonding wire (or IC chip, lead frame, and bonding wire) with an insulating film. The bonding wire used in the wire bonding process is a conventional wire without sheathing, and the work is simple as it only needs to be coated with an insulating agent after the bonding process, and the formation of an insulating film can effectively prevent short circuits. Ru. Note that if an insulating film is formed over the entire semiconductor device, the sharp edges of the IC chip or lead frame will be coated, so that the wire will not be rubbed during molding and the film formed on the wire will not peel off.

〈実施例〉 以下、図面に示された実施例に基づいてこの発明の方法
を詳細に説明する。<Example> Hereinafter, the method of the present invention will be explained in detail based on the example shown in the drawings.

第１図は、この発明の方法によってＩＣチップ３、リー
ドフレーム４及びボンディングワイヤ２に絶縁皮膜１を
コーティングした状態を示している。コーティングは、
短絡防止のため、ボンディングワイヤのみを対象として
行ってもよい。FIG. 1 shows an IC chip 3, a lead frame 4, and a bonding wire 2 coated with an insulating film 1 by the method of the present invention. The coating is
To prevent short circuits, this may be performed only on the bonding wires.

この発明の方法は、従来のワイヤボンディング工程の後
に、短絡防止用の皮膜を形成する工程を追加することに
よって行われる。The method of the present invention is performed by adding a step of forming a short-circuit prevention film after the conventional wire bonding step.

ワイヤボンディング工程は、絶縁皮膜が形成されていな
いワイヤを用い、通常と同様に行われる。The wire bonding process is performed in the same manner as usual using a wire on which an insulating film is not formed.

その後、ボンディングされたワイヤに対して１色縁剤を
塗布してその後の工程における短絡を防止するが、絶縁
剤の塗布には以下のような方法が考えられる。After that, a one-color edging agent is applied to the bonded wires to prevent short circuits in subsequent steps, and the following method can be considered for applying the insulating agent.

（イ）スプレーを用いて噴霧する方法 第２図に示すように、ワイヤボンディング工程が終了し
た半導体装ＷＡをステップ送りしながら、絶縁剤５をス
プレー６で噴霧する方法である。スプレー６の下部には
、籾数した絶縁剤を捕集するために、フィルターと連結
された真空吸引装置７が配設されている。(a) Method of spraying using a spray As shown in FIG. 2, this is a method of spraying the insulating agent 5 with a spray 6 while step-feeding the semiconductor device WA that has undergone the wire bonding process. A vacuum suction device 7 connected to a filter is disposed below the sprayer 6 to collect the insulating agent that has separated from the grains.

（ロ）要被覆部を直接被覆剤に浸す方法第３図に示すよ
うに、内筒１０と外筒９を同心的に立設した絶縁剤噴流
装置８を用いて、内筒１０内から絶縁剤５を盛り上がる
ように噴流させ、被覆加工されるべき半導体装ＷＢを表
裏逆さまにした状態でステップ送りしながら、噴流する
絶縁剤５に直接、半導体装置Ｂの要被覆部分を接触させ
る方法である。(b) Directly immersing the parts requiring coating in the coating agent As shown in Figure 3, insulation is insulated from inside the inner tube 10 using an insulating agent jet device 8 in which the inner tube 10 and the outer tube 9 are installed concentrically. This is a method in which the insulating agent 5 is jetted in a rising manner, and the part of the semiconductor device B that needs to be coated is brought into direct contact with the jetted insulating agent 5 while step-feeding the semiconductor device WB to be coated with the semiconductor device WB upside down. .

また、第３図に示す方法のほかに、ワイヤボンディング
工程が終了した半導体装置の上方から絶縁剤を流して被
覆する方法でもよい。In addition to the method shown in FIG. 3, a method may also be used in which an insulating agent is poured from above the semiconductor device after the wire bonding process is completed.

なお、ワイヤボンディングを行った半導体装置は、手荒
い扱いをすると容易に変形・破損し不良品となるため、
上記絶縁皮膜を付与する工程は、ボンディング工程の直
後にあることが望ましい。Note that semiconductor devices that have undergone wire bonding can easily become deformed or damaged if handled roughly, resulting in defective products.
It is desirable that the step of applying the insulating film be performed immediately after the bonding step.

従って、ワイヤボンダと一体に構成するか、またはワイ
ヤボンダに接続して設置されることが望ましい。Therefore, it is desirable that the device be integrated with the wire bonder or connected to the wire bonder.

〈発明の効果〉 上記のように構成されるこの発明の方法によれば以下の
ような種々の効果を奏する。<Effects of the Invention> According to the method of the present invention configured as described above, the following various effects can be achieved.

■ワイヤボンディング時には被覆のない通常のワイヤを
使用するため、接合面に被覆材料が入り込むことがなく
、接合の信転性が確保される。■Since regular uncoated wire is used during wire bonding, the coating material does not get into the bonding surface, ensuring reliability of the bond.

■ワイヤボンディング時にワイヤから被覆を除去する必
要がないため、煩瑣な作業を強いられることがなく、被
覆を除去するための時間が節約される。従って、高価な
ワイヤボンダの稼働率が低下することもなく、経済的で
ある。■Since there is no need to remove the coating from the wire during wire bonding, no complicated work is required and time for removing the coating is saved. Therefore, the operating rate of the expensive wire bonder does not decrease, and it is economical.

■ＩＣチップやリードフレームなどをワイヤと共に絶縁
剤でコーティングすれば、ワイヤとＩＣチップやリード
フレームとの接合部分の絶縁破壊が生じにくくなるとと
もに、適当な材料を用いることにより、モールド後にワ
イヤの接合に掛かる応力を減することができる。■Coating IC chips and lead frames together with wires with an insulating agent will prevent dielectric breakdown at the joints between wires and IC chips and lead frames, and by using an appropriate material, wires can be bonded together after molding. It is possible to reduce the stress applied to

■ＩＣチップやリードフレームの鋭いエツジがコーティ
ングされるため、モールド時にワイヤが擦られて皮膜が
剥離されることもない。■Since the sharp edges of IC chips and lead frames are coated, the coating will not peel off due to wire rubbing during molding.

■ＩＣチップやリードフレームの鋭いエツジがコーティ
ングにより消滅するため、モールド材料が半田づけ時の
熱応力の集中によってクランクを起こすことも少なくな
る。■Since sharp edges on IC chips and lead frames are eliminated by coating, the mold material is less likely to crank due to concentration of thermal stress during soldering.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図乃至第３図はこの発明の方法の１実施例を示し、
第１図は、この発明の方法によって皮膜が形成された半
導体装置の一部拡大断面図、第２図及び第３図は皮膜形
成の方法を示す説明図、第４図は従来技術によった場合
の半導体装置の一部拡大側面図である。 １：絶縁皮膜　　　　２：ボンディングヮイヤ３：ＩＣ
チップ　　　４：リードフレーム５：絶縁剤1 to 3 show an embodiment of the method of the present invention,
FIG. 1 is a partially enlarged sectional view of a semiconductor device in which a film is formed by the method of the present invention, FIGS. 2 and 3 are explanatory diagrams showing the method of film formation, and FIG. FIG. 2 is a partially enlarged side view of a semiconductor device according to the present invention. 1: Insulating film 2: Bonding layer 3: IC
Chip 4: Lead frame 5: Insulating material

Claims (3)

【特許請求の範囲】[Claims] （１）ワイヤボンディング後にボンディングワイヤに絶
縁皮膜を形成することを特徴とするボンディングワイヤ
の短絡防止方法(1) A bonding wire short-circuit prevention method characterized by forming an insulating film on the bonding wire after wire bonding. （２）被覆剤をスプレーを用いて塗布することにより絶
縁皮膜が形成されることを特徴とする請求項第１記載の
ボンディングワイヤの短絡防止方法(2) The method for preventing short circuits in bonding wires according to claim 1, characterized in that the insulating film is formed by applying the coating agent using a spray. （３）要被覆部を被覆剤に浸漬することによって絶縁皮
膜が形成されることを特徴とする請求項第１記載のボン
ディングワイヤの短絡防止方法（４）ワイヤボンディン
グ後に、ＩＣチップ、リードフレーム及びボンディング
ワイヤの全体に絶縁皮膜を形成することを特徴とするボ
ンディングワイヤの短絡防止方法(3) A method for preventing a short circuit of a bonding wire according to claim 1, characterized in that an insulating film is formed by immersing a portion requiring coating in a coating agent. (4) After wire bonding, an IC chip, a lead frame and A bonding wire short-circuit prevention method characterized by forming an insulating film over the entire bonding wire.
JP2277840A 1990-10-18 1990-10-18 Prevention of short circuit of bonding wire Pending JPH04154133A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2277840A JPH04154133A (en) 1990-10-18 1990-10-18 Prevention of short circuit of bonding wire

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2277840A JPH04154133A (en) 1990-10-18 1990-10-18 Prevention of short circuit of bonding wire

Publications (1)

Publication Number Publication Date
JPH04154133A true JPH04154133A (en) 1992-05-27

Family

ID=17589000

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2277840A Pending JPH04154133A (en) 1990-10-18 1990-10-18 Prevention of short circuit of bonding wire

Country Status (1)

Country Link
JP (1) JPH04154133A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08330346A (en) * 1995-05-31 1996-12-13 Nec Kyushu Ltd Manufacture of semiconductor device
WO2021251219A1 (en) * 2020-06-11 2021-12-16 株式会社村田製作所 Module

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08330346A (en) * 1995-05-31 1996-12-13 Nec Kyushu Ltd Manufacture of semiconductor device
WO2021251219A1 (en) * 2020-06-11 2021-12-16 株式会社村田製作所 Module

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