JPH04150030A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH04150030A JPH04150030A JP27450690A JP27450690A JPH04150030A JP H04150030 A JPH04150030 A JP H04150030A JP 27450690 A JP27450690 A JP 27450690A JP 27450690 A JP27450690 A JP 27450690A JP H04150030 A JPH04150030 A JP H04150030A
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- field insulating
- silicon substrate
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims abstract description 35
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 27
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 27
- 239000010703 silicon Substances 0.000 claims abstract description 27
- 238000005530 etching Methods 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 241000293849 Cordylanthus Species 0.000 abstract description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052782 aluminium Inorganic materials 0.000 abstract description 6
- 230000002093 peripheral effect Effects 0.000 abstract 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 229910004205 SiNX Inorganic materials 0.000 description 4
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 4
- 229910052681 coesite Inorganic materials 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011259 mixed solution Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 125000003158 alcohol group Chemical group 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000035936 sexual power Effects 0.000 description 1
- SCPYDCQAZCOKTP-UHFFFAOYSA-N silanol Chemical compound [SiH3]O SCPYDCQAZCOKTP-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
ＬＯＣＯ５法による素子間分離絶縁膜の形成方法の改善
に関し、
シリコン基板表面の段差を解消させて平坦化することを
目的とし、
ＬＯＣＯＳ法によってシリコン基板表面を選択的に熱酸
化してフィールド絶縁膜を生成する工程と、
次いで、シリコン基板表面より凸状に盛り上がった前記
フィールド絶縁膜をエッチバックして、基板面を平坦に
する工程と、
次いで、ＳＯＧ膜を塗布し固化させた後、該ＳＯＧ膜を
エッチバックして、前記フィールド絶縁膜周縁の凹部に
のみ該ＳＯＧ膜を残存させ、前記フィールド絶縁膜を含
むシリコン基板全面を平坦化する工程とが含まれること
を特徴とする。[Detailed Description of the Invention] [Summary] Regarding the improvement of the method of forming an isolation insulating film between elements using the LOCOS method, the present invention aims to flatten the surface of a silicon substrate by eliminating steps on the surface of the silicon substrate. a step of selectively thermally oxidizing a field insulating film, a step of etching back the field insulating film raised from the surface of the silicon substrate to flatten the substrate surface, and a step of forming a SOG film. After applying and solidifying the SOG film, the SOG film is etched back so that the SOG film remains only in the recessed portion around the edge of the field insulating film, and the entire surface of the silicon substrate including the field insulating film is planarized. It is characterized by being
本発明は半導体装置の製造方法のうち、特にＬｏｃｏｓ
法による素子間分離絶縁膜の形成方法の改善に関する。The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device.
The present invention relates to an improvement in a method for forming an inter-element isolation insulating film using a method.
ＬＳＩなどの半導体デバイスの製造方法においては、従
前より素子間分離絶縁膜（フィールド絶縁膜）を形成す
る方法としてＬＯＣＯＳ法と呼ばれる選択酸化法が特に
著名であり、現在もなお汎用されている。BACKGROUND ART In manufacturing methods for semiconductor devices such as LSIs, a selective oxidation method called the LOCOS method has been particularly well-known as a method for forming an element isolation insulating film (field insulating film), and is still widely used today.
第２図（ａｌ、 （ｂｌはそのＬＯＣＯＳ法による従来
の製造方法の工程順断面図を示しており、その概要を説
明すると、
第２図（ａ）参照；まず、シリコン基板１上に膜厚７０
０人程度の窒化シリコン（ＳｉＮｘ）膜２を化学気相成
長（ＣＶ Ｄ）法で被着し、これをフォトプロセスでパ
ターンニングして選択的に形成する。Figure 2 (al, (bl) shows a cross-sectional view of the conventional manufacturing method using the LOCOS method in the order of steps, and the outline thereof is explained as follows: See Figure 2 (a); First, the film thickness is 70
A silicon nitride (SiNx) film 2 having a thickness of about 100 nm is deposited by chemical vapor deposition (CVD), and is selectively formed by patterning by a photo process.
この５ｉＮＸ膜２の被覆部分が素子形成領域を保護する
マスクとなる。なお、本例はＳ ｉ Ｎ ｘ膜２を直接
シリコン基板１に被着した例で説明しているが、シリコ
ン基板とＳｉＮｘ膜との間にストレスを緩衝するために
膜厚数百人の酸化シリコン（ＳｉＯｚ）膜を介在させて
、ＳｉＣ２膜とＳｉＮｘ膜とを積層したマスクを選択的
に形成する方法も採られている。The covered portion of the 5iNX film 2 serves as a mask for protecting the element formation region. In this example, the SiNx film 2 is directly deposited on the silicon substrate 1, but in order to buffer the stress between the silicon substrate and the SiNx film, an oxidation film of several hundred layers is added. There is also a method of selectively forming a mask in which a SiC2 film and a SiNx film are laminated with a silicon (SiOz) film interposed therebetween.
第２図（ｂ）参照；次いで、その５ｉＮ）、膜２をマス
クとして酸化雰囲気中で１１００℃程度の高温度で熱酸
化して、露出部分に膜厚６０００人のＳｉＣ２膜からな
るフィールド絶縁膜３を生成する。Refer to FIG. 2(b); Next, using the film 2 as a mask, thermal oxidation is carried out at a high temperature of about 1100°C in an oxidizing atmosphere, and a field insulating film made of SiC2 film with a thickness of 6000 nm is formed on the exposed part. Generate 3.
しかる後、５ｉＮＸ膜２を除去して、素子を形成するた
めの製造工程に移行する。Thereafter, the 5iNX film 2 is removed and a manufacturing process for forming an element is started.
しかしながら、上記のような製造方法によればシリコン
基板を熱酸化して５ｉ０ｚ膜に変成した際に、シリコン
が酸化シリコンになって体積が膨張し、そのため、シリ
コン基板表面からＳｉＯ□膜が盛り上がって、平坦な基
板表面に段差が生じる。However, according to the above manufacturing method, when the silicon substrate is thermally oxidized and transformed into a 5i0z film, the silicon becomes silicon oxide and expands in volume, and as a result, the SiO□ film rises from the surface of the silicon substrate. , a step appears on the flat substrate surface.
例えば、膜厚６０００人の５ｉｎ２膜からなるフィール
ド絶縁膜３を生成すると、５ｉＯｚ膜が２５００〜３０
００人の高さに盛り上がった段差を発生する。For example, when producing a field insulating film 3 consisting of a 5in2 film with a film thickness of 6000, the 5iOz film will
A raised step rises to the height of 00 people.
従来、この程度の段差は余り問題とセずに、素子の製造
工程を実施していたが、半導体素子（チップ）の高集積
化が益々進行して、且つ、ＬＳＩ。In the past, the device manufacturing process was carried out without such a level difference being a problem, but semiconductor devices (chips) are becoming increasingly highly integrated, and LSIs are becoming more and more integrated.
ＶＬＳ Ｉとチップが大型化してきた現在、上記のよう
なＬＯＣＯＳ法で生じたフィールド絶縁膜３の段差も出
来るだけ小さくすることが要望されている。それはウェ
ハープロセスの初期製造工程に発生した段差は以降の製
造工程にも残存して、高集積化・微細化が進むにつれて
、例えば終了近い工程で被着したアルミニウム配線も輻
較した多層配線になり、且つ、微細化されて、スパツク
したアルミニウム配線はカバーレイジ（被覆性）が良く
ないために、従来よりも一層断線や短絡の危険が増大し
てきたからである。Nowadays, as VLSI chips and chips become larger, it is desired that the step difference in the field insulating film 3 caused by the above-mentioned LOCOS method be made as small as possible. This is because the steps that occur in the initial manufacturing process of the wafer process remain in subsequent manufacturing processes, and as the integration and miniaturization progress, for example, the aluminum wiring deposited near the end of the process becomes a congested multilayer wiring. In addition, the finer, spattered aluminum wiring has poor coverage, which has increased the risk of wire breakage and short circuits even more than in the past.
本発明はこのような問題点を低減させ、シリコン基板表
面の段差を解消させて平坦化することを目的とした製造
方法を提案するものである。The present invention proposes a manufacturing method aimed at reducing such problems and flattening the surface of a silicon substrate by eliminating steps.
その課題は、ＬＯＣＯ５法によってシリコン基板表面を
選択的に熱酸化してフィールド絶縁膜を生成する工程と
、
次いで、シリコン基板表面より凸状に盛り上がった前記
フィールド絶縁膜をエッチハックして、基板面を平坦に
する工程と、
次いで、ＳＯＣ膜を塗布し固化させた後、該ＳＯＧ膜を
エッチバンクして、前記フィールド絶縁膜周縁の凹部に
のみ該ＳＯＧ膜を残存させ、前記フィールド絶縁膜を含
むシリコン基板全面を平坦化する工程が含まれる製造方
法によって解決される。The task was to selectively thermally oxidize the surface of the silicon substrate using the LOCO5 method to generate a field insulating film, and then etch-hack the field insulating film that was raised above the surface of the silicon substrate to remove the surface of the substrate. Next, after applying and solidifying the SOC film, the SOG film is etched banked so that the SOG film remains only in the concave portion at the periphery of the field insulating film, and the SOG film including the field insulating film is flattened. This problem is solved by a manufacturing method that includes a step of flattening the entire surface of the silicon substrate.
即ち、本発明は、ＬＯＣＯＳ法によって５ｉＯｚ膜（フ
ィールド絶縁膜）を生成した後、基板表面から盛り上が
って形成されたＳｉＯ□膜をエッチバック除去して平坦
にする。その時、フィールド絶縁膜の周縁のバーズビー
ク部分はエッチバンク後はエツチングされて凹部になる
ため、それをＳ○Ｇ膜で埋めて基板全面を一様に平坦化
する。That is, in the present invention, after a 5iOz film (field insulating film) is produced by the LOCOS method, the SiO□ film that has been formed protruding from the substrate surface is removed by etching back to make it flat. At this time, the bird's beak portion at the periphery of the field insulating film is etched after the etch bank and becomes a recess, so the recess is filled with the S○G film to uniformly planarize the entire surface of the substrate.
そうすれば、フィールド絶縁膜を形成した後のシリコン
基板表面が平坦になり、後工程で形成されるアルミニウ
ム配線のカハーレイジ等が改善されて、高信頼化された
半導体デバイスが得られる。By doing so, the surface of the silicon substrate after the field insulating film is formed becomes flat, and the damage, etc. of the aluminum wiring formed in the subsequent process is improved, and a highly reliable semiconductor device can be obtained.
以下、図面を参照して実施例によって詳細に説明すると
、第１図ｆａｌ〜（ｄｌは本発明にかかる製造方法の工
程順断面図を示している。DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail by way of examples with reference to the drawings. FIGS.
第１図（ａ）参照；周知のＬＯＣＯ５法によってシリコ
ン基板１を熱酸化して膜厚１００００人の５１０２膜か
らなるフィールド絶縁膜３ （従来よりも膜厚の厚い絶
縁膜）を選択的に生成する。そうすると、ＳｉＯ２膜は
体積が膨張するためにシリコン基板表面ＩＳからＳｉＯ
□膜部分が盛り上がって形成されて段差が発生する。Refer to FIG. 1(a); The silicon substrate 1 is thermally oxidized by the well-known LOCO5 method to selectively produce a field insulating film 3 (thicker insulating film than conventional ones) consisting of 5102 films with a film thickness of 10,000. do. Then, since the volume of the SiO2 film expands, the SiO2 film expands from the silicon substrate surface IS to the SiO2 film.
□The membrane portion is formed to be raised and a step is generated.
第１図（１））参照；次いで、これを弗酸と弗化アンモ
ンとの混合液に浸漬し、ＳｉＯ□膜３を厚さ５０００人
程度エソチハックして、５ｉＯｚ膜の表面をシリコン基
板表面ＩＳと同一の高さにする。このエツチング量の調
節はエッチバックの時間制御によっておこなうことがで
きる。Refer to Figure 1 (1)); Next, this is immersed in a mixed solution of hydrofluoric acid and ammonium fluoride, and the SiO□ film 3 is hacked to a thickness of about 5,000 to make the surface of the 5iOz film similar to the silicon substrate surface IS. Make it the same height as. The amount of etching can be adjusted by controlling the etchback time.
第１図（Ｃ１参照；次いで、ＳＯＧ膜４を塗布して高温
熱処理（酸素ガス中で９５０℃、３０分程度の処理）し
て固化させ、膜厚１ｓｏｏ人程度のＳＯＧ膜４を被着す
る。ＳＯＧ膜はスピンオンガラス（ＳｐｉｎＯｎ Ｇｌ
ａｓｓ）膜の略で、シラノールをアルコールを主成分と
する有機溶剤に溶解してあり、これを塗布して熱処理す
ると溶剤が飛散してＳｉＯ□膜のみ固着する。このＳＯ
Ｃ膜４を塗布する理由は、上記のＬＯＣＯＳ法によって
フィールド絶縁膜３を生成した際、フィールド絶縁膜３
の周縁にノ＼−ズビーク（鳥の嘴）が生しているが、こ
の部分も同し厚みだけエッチバックされて、その部分が
凹部になるために、そのバーズビーク部分を埋没させる
ものである。FIG. 1 (See C1; Next, the SOG film 4 is coated and solidified by high-temperature heat treatment (processing in oxygen gas at 950° C. for about 30 minutes), and the SOG film 4 with a film thickness of about 1 soum is deposited. .The SOG film is made of spin-on glass (SpinOn Gl).
Abbreviation for ASS) film, in which silanol is dissolved in an organic solvent whose main component is alcohol, and when this is applied and heat treated, the solvent scatters and only the SiO□ film is fixed. This S.O.
The reason for applying the C film 4 is that when the field insulating film 3 is produced by the above-mentioned LOCOS method, the field insulating film 3 is
A bird's beak (bird's beak) is formed around the periphery, but this part is also etched back by the same thickness and becomes a recess, thereby burying the bird's beak.
第１図（ｄｌ参照；次いで、再び弗酸と弗化アンモンと
の混合液に浸漬してＳＯＧ膜４を厚さ１５００人程度エ
ンチハックしてフィールド絶縁膜３およびシリコン基板
表面ＩＳを露出させ、バーズビーク部分のみをＳＯＧ膜
４で埋めて、シリコン基板全表面を平坦化させる。FIG. 1 (see dl; next, the SOG film 4 is immersed again in a mixed solution of hydrofluoric acid and ammonium fluoride, and the SOG film 4 is etch-hacked to a thickness of about 1,500 mm to expose the field insulating film 3 and the silicon substrate surface IS. Only that portion is filled with the SOG film 4 to planarize the entire surface of the silicon substrate.
このようなフィールド絶縁膜の製造方法を実施すればウ
ェハープロセスにおける初期工程の表面段差をなくする
ことが可能になり、半導体デバイスの高信頼化に役立つ
。If such a method for manufacturing a field insulating film is implemented, it becomes possible to eliminate surface steps in the initial steps in the wafer process, which helps improve the reliability of semiconductor devices.
なお、上記例はエッチハックをウェットエツチングでお
こなう実施例で説明したが、弗素系ガスを用いるドライ
エツチングでおこなっても構わない。In the above example, the etch hack is performed by wet etching, but dry etching using fluorine gas may also be used.
以上の説明から明らかなように、本発明にかかる製造方
法によればフィールド絶縁膜を形成した後のシリコン基
板表面が平坦化されて、アルミニウム配線のカハーレイ
ジが改善される等、半導体デバイスの信転性向上に顕著
な効果があるものである。As is clear from the above description, according to the manufacturing method of the present invention, the surface of the silicon substrate after forming the field insulating film is flattened, and the reliability of semiconductor devices is improved, such as improving the coverage of aluminum wiring. It has a remarkable effect on improving sexual performance.
第１図（ａｌ〜（ｄｉは本発明にかかる製造方法の工程
順断面図、
第２図ｔａ＋、 （ｂｌは従来の製造方法の工程順断面
図である。
図において、
１はシリコン基板、
２は５ｉＮＸ膜、
３は５ｉＯｚ膜からなるフィールド絶縁膜、４はＳＯＣ
膜、
ＩＳはシリコン基板表面
を示している。
４ ＳＯＧ鴫菓
／
不発朗＋５ｒＦｊ製造籏しぽバｉＬ情の第１ｍ！Figures 1 (al to (di) are step-by-step cross-sectional views of the manufacturing method according to the present invention, and Figures 2 (ta+, (bl) are step-by-step cross-sectional views of the conventional manufacturing method. In the figures, 1 is a silicon substrate, 2 is a 5iNX film, 3 is a field insulating film made of a 5iOz film, and 4 is a SOC
Film, IS indicates the silicon substrate surface. 4 SOG Shika/Fudatsuro+5rFj manufacturing 籏しPOBAiLjo's 1st m!
Claims (1)
化してフィールド絶縁膜を生成する工程と、 次いで、シリコン基板表面より凸状に盛り上がった前記
フィールド絶縁膜をエッチバックして、基板面を平坦に
する工程と、 次いで、ＳＯＧ膜を塗布し固化させた後、該ＳＯＧ膜を
エッチバックして、前記フィールド絶縁膜周縁の凹部に
のみ該ＳＯＧ膜を残存させ、前記フィールド絶縁膜を含
むシリコン基板全面を平坦化する工程とが含まれてなる
ことを特徴とする半導体装置の製造方法。[Claims] A step of selectively thermally oxidizing the surface of a silicon substrate by a LOCOS method to generate a field insulating film, and then etching back the field insulating film that is raised in a convex shape from the surface of the silicon substrate. a step of flattening the substrate surface, and then, after applying and solidifying the SOG film, the SOG film is etched back to leave the SOG film only in the recessed portions around the field insulating film, and the field insulating film A method for manufacturing a semiconductor device, comprising the step of planarizing the entire surface of a silicon substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27450690A JPH04150030A (en) | 1990-10-12 | 1990-10-12 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27450690A JPH04150030A (en) | 1990-10-12 | 1990-10-12 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04150030A true JPH04150030A (en) | 1992-05-22 |
Family
ID=17542649
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27450690A Pending JPH04150030A (en) | 1990-10-12 | 1990-10-12 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04150030A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5393694A (en) * | 1994-06-15 | 1995-02-28 | Micron Semiconductor, Inc. | Advanced process for recessed poly buffered locos |
| US5432118A (en) * | 1994-06-28 | 1995-07-11 | Motorola, Inc. | Process for forming field isolation |
| US5672538A (en) * | 1995-12-04 | 1997-09-30 | Taiwan Semiconductor Manufacturing Company, Ltd | Modified locus isolation process in which surface topology of the locos oxide is smoothed |
| US5728622A (en) * | 1996-03-18 | 1998-03-17 | Winbond Electronics Corporation | Process for forming field oxide layers in semiconductor devices |
| US5858860A (en) * | 1996-02-08 | 1999-01-12 | Samsung Electronics Co., Ltd. | Methods of fabricating field isolated semiconductor devices including step reducing regions |
| KR19990004609A (en) * | 1997-06-28 | 1999-01-15 | 김영환 | Method of forming device isolation film of semiconductor device |
-
1990
- 1990-10-12 JP JP27450690A patent/JPH04150030A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5393694A (en) * | 1994-06-15 | 1995-02-28 | Micron Semiconductor, Inc. | Advanced process for recessed poly buffered locos |
| US5432118A (en) * | 1994-06-28 | 1995-07-11 | Motorola, Inc. | Process for forming field isolation |
| US5985736A (en) * | 1994-06-28 | 1999-11-16 | Motorola, Inc. | Process for forming field isolation |
| US5672538A (en) * | 1995-12-04 | 1997-09-30 | Taiwan Semiconductor Manufacturing Company, Ltd | Modified locus isolation process in which surface topology of the locos oxide is smoothed |
| US5858860A (en) * | 1996-02-08 | 1999-01-12 | Samsung Electronics Co., Ltd. | Methods of fabricating field isolated semiconductor devices including step reducing regions |
| US5728622A (en) * | 1996-03-18 | 1998-03-17 | Winbond Electronics Corporation | Process for forming field oxide layers in semiconductor devices |
| KR19990004609A (en) * | 1997-06-28 | 1999-01-15 | 김영환 | Method of forming device isolation film of semiconductor device |
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