JPH0414887B2 - - Google Patents
Info
- Publication number
- JPH0414887B2 JPH0414887B2 JP25489285A JP25489285A JPH0414887B2 JP H0414887 B2 JPH0414887 B2 JP H0414887B2 JP 25489285 A JP25489285 A JP 25489285A JP 25489285 A JP25489285 A JP 25489285A JP H0414887 B2 JPH0414887 B2 JP H0414887B2
- Authority
- JP
- Japan
- Prior art keywords
- input
- signal
- output
- gate
- section
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000001514 detection method Methods 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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- Manipulation Of Pulses (AREA)
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体集積回路装置、特にCMOSで
構成された信号断検出回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to a semiconductor integrated circuit device, and particularly to a signal disconnection detection circuit constructed of CMOS.
従来の技術
従来論理回路をCMOSで構成した半導体集積
回路装置は、半導体基板上にMOSトランジスタ
等を配置し、おのおのを導体で結線して所望の機
能を構成している。この場合信号断についての対
策がとられていなかつた。BACKGROUND ART Conventionally, a semiconductor integrated circuit device in which a logic circuit is constructed using CMOS has MOS transistors and the like arranged on a semiconductor substrate, each of which is connected with a conductor to provide a desired function. In this case, no measures were taken to prevent signal interruption.
発明が解決しようとする問題点
上述した従来のCMOSで構成された半導体集
積回路装置の場合、入力信号等が断となりゲート
回路の入力信号が不定になると、ゲート回路に貫
通電流が流れ、特にクロツク信号等FAN OUT
が多い信号が不定になつた場合、正常動作時の電
流に対し大幅に電源電流が増加するという欠点を
有していた。Problems to be Solved by the Invention In the case of the semiconductor integrated circuit device configured with the conventional CMOS described above, when the input signal etc. is cut off and the input signal to the gate circuit becomes unstable, a through current flows through the gate circuit, and especially when the clock Signal, etc. FAN OUT
When a signal with a large number of signals becomes unstable, the power supply current increases significantly compared to the current during normal operation.
そのため装置の電源部が容量オーバーになり、
最悪の場合には装置全体の機能が停止したり、ま
たそれを防ぐために電源部を必要以上に大きくす
る必要があつた。 As a result, the power supply section of the device exceeds its capacity.
In the worst case scenario, the entire device would stop functioning, and to prevent this, it was necessary to make the power supply section larger than necessary.
問題点を解決するための手段
２入力NORゲート３の第１の入力側を入力部
４に接続し、入力側が入力部４に接続された第１
のインバータ１の出力側をNORゲート３の第２
の入力側に接続し、NORゲート３の出力側を第
２のインバータ２の入力側に接続し、インバータ
２の出力側を出力部５に接続して信号断検出回路
を構成した。Means for solving the problem A first input side of the two-input NOR gate 3 is connected to the input part 4, and a first input side of the two-input NOR gate 3 is connected to the input part 4.
The output side of inverter 1 is connected to the second output side of NOR gate 3.
The output side of the NOR gate 3 was connected to the input side of the second inverter 2, and the output side of the inverter 2 was connected to the output section 5 to form a signal disconnection detection circuit.
実施例
次に本発明の実施例について図面を参照し説明
する。Embodiments Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明による信号断検出回路の一実施
例での回路図である。 FIG. 1 is a circuit diagram of an embodiment of a signal disconnection detection circuit according to the present invention.
入力部４に信号が入力されると、入力レベルが
ハイレベルの場合もロウレベルの場合も２入力
NORゲート３の出力は常にロウレベルとなる。
その結果入力部４に信号が入力されている限り出
力部５にはハイレベルが出力される。 When a signal is input to input section 4, there are two inputs regardless of whether the input level is high level or low level.
The output of NOR gate 3 is always at a low level.
As a result, as long as the signal is input to the input section 4, a high level is output to the output section 5.
次に信号が断となつた場合の状態を説明する。 Next, the situation when the signal is disconnected will be explained.
入力部４の信号が断となり電位が中間電位にな
ると、インバータ１，２および２入力NORゲー
ト３を構成するＰチヤネルおよびＮチヤネルトラ
ンジスタがすべてオンとなり、それぞれの出力電
位も中間電位となる。この場合、インバータ２の
スレツシヨルド電圧を低くし、出力電位が十分ハ
イレベルとなるようにインバータ２のＰチヤネル
トランジスタとＮチヤネルトランジスタを設定す
ることにより、入力信号が断の場合のみ出力部に
ロウレベルが出力される。 When the signal at the input section 4 is cut off and the potential becomes an intermediate potential, all the P-channel and N-channel transistors constituting the inverters 1 and 2 and the two-input NOR gate 3 are turned on, and their respective output potentials also become the intermediate potential. In this case, by lowering the threshold voltage of inverter 2 and setting the P-channel transistor and N-channel transistor of inverter 2 so that the output potential is at a sufficiently high level, the output section will have a low level only when the input signal is disconnected. Output.
第２図は本発明による信号断検出回路の応用例
である。図において、６が第１図で示した信号断
検出回路である。入力部８にクロツク信号が印加
されている場合は、信号断検出回路の出力５は常
にハイレベルとなり、セレクタ７はＢ側を選択
し、出力部９にはクロツク信号がそのまま出力さ
れる。 FIG. 2 is an application example of the signal disconnection detection circuit according to the present invention. In the figure, 6 is the signal disconnection detection circuit shown in FIG. When a clock signal is applied to the input section 8, the output 5 of the signal disconnection detection circuit is always at a high level, the selector 7 selects the B side, and the clock signal is output as is to the output section 9.
次にクロツク信号が断になつた場合には、信号
断検出回路の出力５はロウレベルとなり、セレク
タ７はＡ側を選択し、出力部９にはロウレベルが
出力される。その結果クロツク信号が不定となり
大電流が流れることを防いでいる。 Next, when the clock signal is disconnected, the output 5 of the signal disconnection detection circuit becomes a low level, the selector 7 selects the A side, and the output section 9 outputs a low level. As a result, the clock signal becomes unstable, preventing large current from flowing.
発明の効果
以上の説明から明らかなように、本発明による
信号断検出回路を用いることにより、半導体回路
内の任意の点の信号断を検出することが可能であ
り、その情報を直接出力することが可能である。Effects of the Invention As is clear from the above explanation, by using the signal disconnection detection circuit according to the present invention, it is possible to detect a signal disconnection at any point in a semiconductor circuit, and the information can be directly output. is possible.
また信号断が原因なる電源電流の増加を防止す
ることも可能である。 It is also possible to prevent an increase in power supply current caused by signal interruption.
第１図は本発明の一実施例の回路図であり、第
２図は本発明の応用例の回路図である。
１，２……インバータ、３……２入力NORゲ
ート、４，８……入力部、５，９……出力部、６
……信号断検出回路、７……２入力セレクタ。
FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a circuit diagram of an applied example of the present invention. 1, 2... Inverter, 3... 2-input NOR gate, 4, 8... Input section, 5, 9... Output section, 6
... Signal disconnection detection circuit, 7 ... 2-input selector.
Claims (1)
力部４に接続され、前記２入力NORゲート３の
第２の入力端子が第１のインバータ１を介して入
力部４に接続され、前記２入力NORゲート３の
出力端子がスレツシヨルド電圧を低くした第２の
インバータ２の入力端子に接続され、この第２の
インバータ２の出力端子が出力部５に接続されて
いることを特徴とする信号断検出回路。1 A first input terminal of the two-input NOR gate 3 is connected to the input section 4, a second input terminal of the two-input NOR gate 3 is connected to the input section 4 via the first inverter 1, and the second input terminal of the two-input NOR gate 3 is connected to the input section 4 via the first inverter 1. A signal disconnector characterized in that the output terminal of the input NOR gate 3 is connected to the input terminal of a second inverter 2 whose threshold voltage is lowered, and the output terminal of this second inverter 2 is connected to the output section 5. detection circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25489285A JPS62116012A (en) | 1985-11-15 | 1985-11-15 | Signal cut detecting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25489285A JPS62116012A (en) | 1985-11-15 | 1985-11-15 | Signal cut detecting circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62116012A JPS62116012A (en) | 1987-05-27 |
| JPH0414887B2 true JPH0414887B2 (en) | 1992-03-16 |
Family
ID=17271289
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25489285A Granted JPS62116012A (en) | 1985-11-15 | 1985-11-15 | Signal cut detecting circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62116012A (en) |
-
1985
- 1985-11-15 JP JP25489285A patent/JPS62116012A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62116012A (en) | 1987-05-27 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |