JPH0414869A - Semiconductor memory - Google Patents
Semiconductor memoryInfo
- Publication number
- JPH0414869A JPH0414869A JP2118156A JP11815690A JPH0414869A JP H0414869 A JPH0414869 A JP H0414869A JP 2118156 A JP2118156 A JP 2118156A JP 11815690 A JP11815690 A JP 11815690A JP H0414869 A JPH0414869 A JP H0414869A
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- bit line
- line
- contact hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 239000010408 film Substances 0.000 claims abstract description 38
- 239000010409 thin film Substances 0.000 claims abstract description 8
- 239000011229 interlayer Substances 0.000 abstract description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 11
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052710 silicon Inorganic materials 0.000 abstract description 10
- 239000010703 silicon Substances 0.000 abstract description 10
- 239000010410 layer Substances 0.000 abstract description 8
- 239000000758 substrate Substances 0.000 abstract description 5
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 abstract description 3
- 229910021342 tungsten silicide Inorganic materials 0.000 abstract description 3
- 239000003990 capacitor Substances 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 5
- 229910052698 phosphorus Inorganic materials 0.000 description 5
- 239000011574 phosphorus Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 235000014121 butter Nutrition 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体記憶装置に関し、特にＤＲＡＭセルに関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a DRAM cell.
従来のスタックドキャパシタとスイッチングトランジス
タで構成されたＤＲＡＭセルの断面図を第４図に示す。FIG. 4 shows a cross-sectional view of a conventional DRAM cell composed of stacked capacitors and switching transistors.
このＤＲＡＭセルは平面型セルと比べ、小さい面積で大
きな静電容量が得られる。This DRAM cell can obtain a large capacitance with a small area compared to a planar cell.
それはキャパシタの蓄積電極１２がワード線８上に積み
重ねられているからである。This is because the storage electrode 12 of the capacitor is stacked on the word line 8.
しかし、高集積化に従って、小さなセル面積でスタック
ドキャパシタの静電容量を大きくとるために、更に改良
されたスタックドキャパシタとスイッチングトランジス
タで構成されたＤ ＲＡ Ｍセルが提案された。その１
例を第５図に示す。このＤＲＡＭセルはワード線８およ
びビット線３より上に蓄積電極１２を有する（例えば月
刊Ｓｅｍ１ｃｏｎｄｕｃｔｏｒ Ｗｏｒｌｄ増刊号′９
０最新半導体プロセス技術）。その為、第４図に示した
ＤＲＡＭセルよりも、蓄積電極１２のマスク上の面積を
大きくとれ、蓄積電極１２の膜厚を大きくしても第２コ
ンタクトホール１１の７スベクト比を大きくすることは
ない。However, in order to increase the capacitance of a stacked capacitor with a small cell area as the integration becomes higher, a DRAM cell including an improved stacked capacitor and a switching transistor has been proposed. Part 1
An example is shown in FIG. This DRAM cell has a storage electrode 12 above the word line 8 and bit line 3 (for example, in the monthly Sem1conductor World special issue '9).
0 latest semiconductor process technology). Therefore, the area of the storage electrode 12 on the mask can be larger than that of the DRAM cell shown in FIG. There isn't.
これらの従来のスタックドキャパシタとスイッチングト
ランジスタで構成された］ｉ） Ｒ，Ａ、 Ｍセルは、
スイッチングトランジスタよりＪ９、にスタック容ｉと
ビット線３を有する為、スタック容ｌｌ二にビット線３
を右する構造（第４図）で１才蓄積電極１２のマスク」
二での面積が小さくなり、ピッＩ・線３より１−にスタ
ック容量を有する構造（第５図）ではマスク上、ビット
線３Ｃ，第１コンタクトホール５を重ねることができな
いので１．第１コンタクトホール５とビット線３の間に
マージンを設けてセル面積を大さくするか、セル面積を
小さくする為ｉｃ第１コンタクトホール５をビット線３
に刻してセル゛ノアラ・インに形成し、で製造を困難に
しＣ１，、まり。These conventional stacked capacitors and switching transistors] i) R, A, M cells are:
Since the switching transistor J9 has the stack capacitor i and the bit line 3, the stack capacitor ll2 has the bit line 3.
With the structure (Fig. 4) to the right, there is a mask for the storage electrode 12.
In the structure (FIG. 5) that has a stack capacitance in 1- from the pin I/line 3, the bit line 3C and the first contact hole 5 cannot be overlapped on the mask. Either provide a margin between the first contact hole 5 and the bit line 3 to increase the cell area, or connect the IC first contact hole 5 to the bit line 3 to increase the cell area.
It is carved into C1, and formed into a cell line, making it difficult to manufacture.
また、通常Ｉ）１（、ＡＭは外部入力信号のア′／ダ・
−シュー１−にＪ、るセル情報破壊な防ぐ為に、基板バ
イアスをかける（４Ｍ ＤＲＡＭで一３Ｖ）、、−ｔ
の為、）・ランジスタのショートチャンネル効果の１つ
であるしきい値電圧低°′ト特性が顕著になる（！：い
う問題点があった。Also, normally I)1(, AM is the external input signal A'/da
- Apply a substrate bias to shoe 1- to prevent cell information destruction (-3V for 4M DRAM), -t
As a result, the threshold voltage low characteristic, which is one of the short channel effects of transistors, becomes noticeable (!).
本発明の半導体記憶装置は、薄膜ｌ−Ｅンジスタをスイ
ッチングトランジスタとし、スタック容量を有する半導
体記憶装置におい〔、薄膜トランジスタのｆに、絶縁膜
を介してヒツト線を有し１、薄膜トランジスタとビット
線は、絶縁膜に形成されたコ゛／タクトホールを介１．
て接続することを特徴とす゛る。The semiconductor memory device of the present invention uses a thin film L-E transistor as a switching transistor, and has a stack capacitance. 1. Through core/tact holes formed in the insulating film.
It is characterized by the fact that it can be connected by
［［実施例：１ 次に本発明に一ついて図面を参照して説明する。[[Example: 1 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の第１の実施例の縦断面図である。■）
型シリコン基板］」−二に例えば酸化シリコンの第１層
間絶縁膜２が設けられ、第１層間絶縁膜２１−に例えば
［１１２ｏ ｏ ｏ人のタングステンシリサイドのビッ
ト線３が設けられ、ビット線３および第１層間絶縁ｉ
２ 、、、Ｊ：＝に例えば膜厚１０００人の酸化シリコ
ンの第２層間絶縁膜４が設けられ、第２層間絶縁膜４に
形成された第１コンタクトポール５ヶ介してビット線３
と接続するように例えば膜厚１００人のシリコン層６が
所定の領域（・こ設けられ、シリコン層６の表面に例え
ば膜厚２００人のゲート酸化膜７が設けられ、シリコン
層６の所定の領域を横断するように例えばＷ、厚２００
０λの燐をＩ Ｘ １０ ”ｃａｎ−’程度ドープした
多結晶・シリコンのワー ド線８が設けられ、ワード線
８の両側のシリコ゛／層６に、例えば砒素のようなＮ型
不純物Ｉ Ｘ Ｉ Ｑ ”ｃｍ−”程度ｌζ−ブしたソ
ース、ドレイン領域９が設けられ、ワード線８及びケー
用・酸化膜７を覆うように、例えば膜厚２０００人の酸
化シリコンの第３層間絶縁膜１０が設けられ、第３層間
絶縁膜１０及びゲート酸化膜７に形成された第２コンタ
クトホール１１を介してソース、ドレイン領域９と接続
するように例えば燐をｌＸｌ０”に−゛２程度ドープし
５た多結晶シリコンの蓄積電極１２が設けられ、蓄積電
極を覆うように例資ば酸化シリコンと窒化シリコンの複
合摸の容量膜１３が設けられ、容１′膜を覆うように例
えば燐を１×１０”ｃｍ−”程度ドープした多結晶シリ
コンのプレート電極１４が設けられている。FIG. 1 is a longitudinal sectional view of a first embodiment of the invention. ■)
A first interlayer insulating film 2 made of silicon oxide, for example, is provided on the first interlayer insulating film 21, and a bit line 3 made of, for example, tungsten silicide of [112o o o and first interlayer insulation i
A second interlayer insulating film 4 of silicon oxide with a thickness of 1,000, for example, is provided on J:=, and the bit line 3 is connected to the bit line 3 through five first contact poles formed on the second interlayer insulating film 4.
A silicon layer 6 with a thickness of, for example, 100 nm is provided in a predetermined area (. For example, W, thickness 200 mm across the area.
A word line 8 of polycrystalline silicon doped with 0λ phosphorus to an extent of I x 10 can-' is provided, and the silicon/layer 6 on both sides of the word line 8 is doped with an N-type impurity I x I such as arsenic, for example. A source and drain region 9 having a dielectric strength of about 1 cm is provided, and a third interlayer insulating film 10 made of silicon oxide, for example, with a thickness of 2000 μm is formed so as to cover the word line 8 and the oxide film 7. For example, phosphorus is doped to lXl0'' to an extent of -2 to connect to the source and drain regions 9 through the second contact holes 11 formed in the third interlayer insulating film 10 and the gate oxide film 7. A storage electrode 12 made of polycrystalline silicon is provided, and a capacitive film 13 made of a composite material of silicon oxide and silicon nitride, for example, is provided to cover the storage electrode. A plate electrode 14 of polycrystalline silicon doped to about "cm-" is provided.
第２図（ａ）〜、（ｃ）は本発明の第１の実施例の製造
方法な説明する為に１６程順に示した縦断面図である。FIGS. 2(a) to 2(c) are vertical cross-sectional views shown in order to explain the manufacturing method of the first embodiment of the present invention.
例えばＰ型シリコン基板ｌの表面を酸化１〜゛ｒ、酸化
シリコンの第１層間絶縁膜２を形成ｔ７、例えばタング
ステンシリサイドをスパッタし、バター４−ソゲしてビ
ット線３を形成し、全面に例えば膜厚１０００人の酸化
シリコンの第２層間絶縁膜４を形成し２、フォトエツチ
ング工程により、第２層間絶縁膜４に第１”７゛／タク
）・ボール５を形成し、全面にシリコン層６を形成して
バター；ングして第２図（ａ）に示す構造を得る。For example, the surface of a P-type silicon substrate 1 is oxidized 1 to 150°C, a first interlayer insulating film 2 of silicon oxide is formed t7, and tungsten silicide is sputtered, for example, and the bit line 3 is formed by sawing with butter 4, and the entire surface is For example, a second interlayer insulating film 4 of silicon oxide with a thickness of 1,000 thick is formed 2, a first 7"/tack) ball 5 is formed on the second interlayer insulating film 4 by a photoetching process, and the entire surface is covered with silicon. Layer 6 is formed and buttered to obtain the structure shown in FIG. 2(a).
次にシリコン層６の表面を酸化し１、ゲート酸化膜７を
形成し７、全角］に例えば多結晶シリコンを形成し、燐
をドープ上１バター；ングしてワード線８を形成し、全
面に砒素のようなＮ型不純物をイオン注入し、てシリコ
ン層６にソース、ドレイン領域９を形成し、全面に酸化
シリコンの第１層間絶縁膜２Ｏを形成し５．フォトエツ
チング工程により、第３層間絶縁膜１０およびゲート酸
化膜７に第２コンタクトポール１１を形成し２て第２図
（１１）に示す構造を得る。Next, the surface of the silicon layer 6 is oxidized 1, a gate oxide film 7 is formed 7, polycrystalline silicon, for example, is formed on the full-width surface, and a word line 8 is formed by doping phosphorus on the surface. 5. Ion-implant an N-type impurity such as arsenic to form source and drain regions 9 in the silicon layer 6, and form a first interlayer insulating film 2O of silicon oxide on the entire surface.5. A second contact pole 11 is formed in the third interlayer insulating film 10 and the gate oxide film 7 by a photoetching process, thereby obtaining the structure shown in FIG. 2 (11).
次に全面に多結晶シリコンを形成し７、燐をドーブして
バターニングし蓄積電極１２を形成し、蓄積電極１２の
表面に窒化シリコンを形成し酸化して”容量膜１３を形
成し、全面に多結晶シリコンを形成し燐をドープしてバ
ターニングしてプレート電極１４を形成し、第２図（ｃ
、）に示す構造を得る。Next, polycrystalline silicon is formed on the entire surface 7, doped with phosphorus and buttered to form the storage electrode 12, silicon nitride is formed on the surface of the storage electrode 12 and oxidized to form a capacitive film 13, and the entire surface is A plate electrode 14 is formed by forming polycrystalline silicon, doping it with phosphorus, and buttering it.
We obtain the structure shown in ).
第３図は本発明の第２の実施例の縦断面図である。ワー
ド線８の側面に、例えば３０００人の酸化シリコンの側
壁１５が設けられている。また、ソース、ドレイン領域
９がワード線８に対してオフセットになっている。その
為、スイッチングトランジスタのオフ電流が第１の実施
例に比へ１けた小さくなり、ホールド時間が長くなる。FIG. 3 is a longitudinal sectional view of a second embodiment of the invention. On the sides of the word lines 8, side walls 15 of silicon oxide, for example 3000, are provided. Further, the source and drain regions 9 are offset with respect to the word line 8. Therefore, the off-state current of the switching transistor becomes one order of magnitude smaller than that in the first embodiment, and the hold time becomes longer.
製造方法としては、ワード線８形成後、全面にＨＴＯを
３０００人形成し、全面エッチバックして側壁１５を形
成した後、例えば砒素のようなＮ型不純物をイオン注入
することによって得られる。As a manufacturing method, after forming the word line 8, forming 3000 HTO on the entire surface, etching back the entire surface to form the sidewall 15, and then ion-implanting an N-type impurity such as arsenic.
以上説明したように本発明は、薄膜トランジスタをスイ
ッチングトランジスタとし、スタック容量を有する半導
体記憶装置において、薄膜トランジスタの下に絶縁膜を
介してビット線を有し、薄膜トランジスタとビット線は
絶縁膜に形成されたコンタクトホールを介して接続した
ので、蓄積電極のマスク上での面積が大きくとれ、セル
ファラインコンタクトを用いずにセル面積を小さくする
ことができるという効果を有する。As explained above, the present invention provides a semiconductor memory device in which a thin film transistor is used as a switching transistor and has a stack capacitance, in which a bit line is provided under the thin film transistor via an insulating film, and the thin film transistor and the bit line are formed in the insulating film. Since the connection is made through the contact hole, the area of the storage electrode on the mask can be increased, and the cell area can be reduced without using a self-line contact.
例えば第４図に示した構造に比べ、蓄積電極のマスク上
での面積を約１．５倍にすることができる。For example, compared to the structure shown in FIG. 4, the area of the storage electrode on the mask can be made approximately 1.5 times larger.
また、基板バイアスをかける必要がないので、トランジ
スタのショートチャネル効果の１つであるしきい値電圧
低下特性がおさえられる。Furthermore, since there is no need to apply a substrate bias, the threshold voltage drop characteristic, which is one of the short channel effects of transistors, can be suppressed.
第１図は本発明の第１の実施例の断面図、第２図（ａ）
〜（ｃ）は本発明の第１の実施例の製造方法を説明する
為に工程順に示した縦断面図、第３図は本発明の第２の
実施例の縦断面図、第４図、第５図は従来のスタックド
キャパシタとスイッチングトランジスタで構成されたＤ
ＲＡＭセルの縦断面図である。
ｌ・・・・・・シリコン基板、２・・・・・・第２層間
絶縁膜、３・・・・・・ヒツト線、４・・・・・・第２
層間絶縁膜、５・・・・・・第１コンタクトホール、６
・・山・シリコン層、７・・・・・・ケート酸化膜、８
・・・・・・ワード線、９・・・・・・ソース、ドレイ
ン領域、１０・・・・・・第３層間絶縁膜、１１・・・
・・・第２コンタクトホール、１２・・・・・・蓄積電
極、１３・・・・・・容量膜、１４・・・・・・プレー
ト電極、１５・・・・・・側壁、１６・・・・・・フィ
ールド酸化膜。
代理人 弁理士 内 原 晋
＋ｓ
第、弓ド」
δ
７′
第ｓ図ｊFig. 1 is a sectional view of the first embodiment of the present invention, Fig. 2(a)
~(c) are longitudinal cross-sectional views shown in order of steps to explain the manufacturing method of the first embodiment of the present invention, FIG. 3 is a longitudinal cross-sectional view of the second embodiment of the present invention, FIG. Figure 5 shows a conventional stacked capacitor and a switching transistor.
FIG. 3 is a longitudinal cross-sectional view of a RAM cell. l...Silicon substrate, 2...Second interlayer insulating film, 3...Hit wire, 4...Second
Interlayer insulating film, 5...First contact hole, 6
...Mountain/silicon layer, 7...Kate oxide film, 8
...Word line, 9...Source, drain region, 10...Third interlayer insulating film, 11...
...Second contact hole, 12...Storage electrode, 13...Capacitive film, 14...Plate electrode, 15...Side wall, 16... ...Field oxide film. Agent Patent Attorney Susumu Uchihara + s.
Claims (1)
タック容量を有する半導体記憶装置において、前記薄膜
トランジスタの下に絶縁膜を介してビット線を有し、前
記薄膜トランジスタと前記ビット線は前記絶縁膜に形成
されたコンタクトホールを介して接続することを特徴と
する半導体記憶装置。In a semiconductor memory device in which a thin film transistor is used as a switching transistor and has a stack capacitance, a bit line is provided below the thin film transistor through an insulating film, and the thin film transistor and the bit line are connected through a contact hole formed in the insulating film. A semiconductor memory device characterized by being connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2118156A JPH0414869A (en) | 1990-05-08 | 1990-05-08 | Semiconductor memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2118156A JPH0414869A (en) | 1990-05-08 | 1990-05-08 | Semiconductor memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0414869A true JPH0414869A (en) | 1992-01-20 |
Family
ID=14729485
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2118156A Pending JPH0414869A (en) | 1990-05-08 | 1990-05-08 | Semiconductor memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0414869A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5973343A (en) * | 1995-04-20 | 1999-10-26 | Nec Corporation | Semiconductor memory device having bit line directly held in contact through contact with impurity region in self-aligned manner and process of fabrication thereof |
| US10456755B2 (en) | 2013-05-15 | 2019-10-29 | The Regents Of The University Of California | Polyaniline membranes formed by phase inversion for forward osmosis applications |
-
1990
- 1990-05-08 JP JP2118156A patent/JPH0414869A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5973343A (en) * | 1995-04-20 | 1999-10-26 | Nec Corporation | Semiconductor memory device having bit line directly held in contact through contact with impurity region in self-aligned manner and process of fabrication thereof |
| US6143600A (en) * | 1995-04-20 | 2000-11-07 | Nec Corporation | Method of fabricating a semiconductor memory device having bit line directly held in contact through contact with impurity region in self-aligned manner |
| US10456755B2 (en) | 2013-05-15 | 2019-10-29 | The Regents Of The University Of California | Polyaniline membranes formed by phase inversion for forward osmosis applications |
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