JPH04134855A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04134855A JPH04134855A JP25778690A JP25778690A JPH04134855A JP H04134855 A JPH04134855 A JP H04134855A JP 25778690 A JP25778690 A JP 25778690A JP 25778690 A JP25778690 A JP 25778690A JP H04134855 A JPH04134855 A JP H04134855A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- diffusion layer
- well
- aluminum
- wiring layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 238000009792 diffusion process Methods 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 239000012535 impurity Substances 0.000 claims description 15
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 229910052782 aluminium Inorganic materials 0.000 abstract description 30
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 30
- 230000000694 effects Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 239000013039 cover film Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に負電圧の静電気による
破壊を防止する半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device that prevents damage due to negative voltage static electricity.
従来、半導体装１の入力保護は、一般的に第３図の等価
回路で示すものが用いられている。Conventionally, for input protection of the semiconductor device 1, the equivalent circuit shown in FIG. 3 has generally been used.
この等価回路は、半導体基板と逆導電型の拡散層抵抗Ｒ
と、拡散層抵抗Ｒと半導体基板とのダイオードＤと、ゲ
ートとソースが接地端に、ドレインが抵抗Ｒの終端にそ
れぞれ接続されたトランジスタＱにより構成されている
。This equivalent circuit is a diffusion layer resistance R of a conductivity type opposite to that of the semiconductor substrate.
, a diffusion layer resistor R, a diode D connected to the semiconductor substrate, and a transistor Q whose gate and source are connected to a ground terminal, and whose drain is connected to the terminal end of the resistor R.
拡散層抵抗Ｒは、入力端子Ｐに加えられた入力パルス波
形をなまらせトランジスタＱが導通状態になった際に１
を流を制限することと、ダイオードとして高電圧が加え
られた時にブレイクダウンして基板に電流を流す働きが
ある。トランジスタＱはバンチスルー素子でソース・ド
レイン間に２０Ｖ前後の電圧が加えられると導通し入力
電圧をりランプする働きがある。The diffusion layer resistance R is 1 when the input pulse waveform applied to the input terminal P is blunted and the transistor Q becomes conductive.
It has the function of limiting the current, and as a diode, it breaks down when high voltage is applied and allows current to flow through the board. Transistor Q is a bunch-through element that becomes conductive when a voltage of around 20V is applied between the source and drain and has the function of ramping the input voltage.
上述した従来の入力保護装置は、以下に示す様な問題点
がある。The conventional input protection device described above has the following problems.
Ｐ型半導体基板を用いる場合、第３図において、入力端
子Ｐに負電圧が印加されるとトランジスタＱが導通状態
となる接地端から入力端子に電流が流れ込んでくるが、
入力端子Ｐに異常な負電圧が印加された場合、Ｎ＋型の
拡散層抵抗ＲとＰ型半導体基板のダイオードＤが順方向
となり、大部分の電子が基板中に注入され、パッド周辺
にある接地レベルのＮ＋型型数散層内側回路のトランジ
スタのソース領域）に到達する。その結果、接地レベル
のＮ３型拡散層がら基板を通して入力端子に大電流が流
れることになり、接地レベルのアルミニウム配線とＮ＋
型型数散層コンタクトでアルミニウムスパイクを起こし
接地レベルのアルミニウム配線と基板が短絡してしまう
。When a P-type semiconductor substrate is used, in FIG. 3, when a negative voltage is applied to the input terminal P, the transistor Q becomes conductive, and current flows into the input terminal from the ground terminal.
When an abnormal negative voltage is applied to the input terminal P, the N+ type diffusion layer resistance R and the P type semiconductor substrate diode D become forward-oriented, and most electrons are injected into the substrate and connected to the ground around the pad. (the source region of the transistor of the N+ type scatter layer inner circuit). As a result, a large current flows through the ground-level N3 type diffusion layer to the input terminal through the substrate, and the ground-level aluminum wiring and N+
Aluminum spikes occur in the multilayer contact, resulting in a short circuit between the ground-level aluminum wiring and the board.
〔課題を解決するための手段〕
本発明は、半導体基板と逆導電型の不純物拡散層を有す
る入力保護装置を用いた半導体装１において、前記人力
保護装置と所定の距離を隔てて設けられた、スクライブ
線の基板電位の金属配線層と、前記金属配線層に接続さ
れた、半導体基板と逆導電型の第１の不純物拡散層、前
記第１の不純物拡散層と所定の距離隔てて設けられた半
導体基板と逆導電型のウェル及び前記ウェル内に設けら
れた、接地レベル又は電源レベルの金属配線層に接続さ
れた半導体基板と逆導電型の第２の不純物拡散層を有す
る補助保護装置が設けられているというものである。[Means for Solving the Problems] The present invention provides a semiconductor device 1 using an input protection device having an impurity diffusion layer of a conductivity type opposite to that of a semiconductor substrate, which is provided at a predetermined distance from the human power protection device. , a metal wiring layer of the substrate potential of the scribe line, a first impurity diffusion layer of a conductivity type opposite to that of the semiconductor substrate and connected to the metal wiring layer, and provided at a predetermined distance from the first impurity diffusion layer. The auxiliary protection device includes a well having a conductivity type opposite to that of the semiconductor substrate, and a second impurity diffusion layer having a conductivity type opposite to the semiconductor substrate, which is connected to a metal wiring layer at a ground level or a power supply level provided in the well. It is said that it is set up.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）は本発明の一実施例の全体の構成を示す平
面図、第１図（ｂ）は一実施例の主要部である補助保護
装置を示す平面図、第１図（ｃ）は第１図（ｂ）のＡ−
Ａ線断面図である。FIG. 1(a) is a plan view showing the overall configuration of an embodiment of the present invention, FIG. 1(b) is a plan view showing an auxiliary protection device which is the main part of the embodiment, and FIG. ) is A- in Figure 1(b)
It is an A-line sectional view.
入力保護装置１４（第３図の回路図で示されるの）から
距離ｄｌ（入力保護装置１４と内部回路領域ｌｂ間の距
離ｄ２より大きい）のところに基板電位のアルミニウム
の配線層７が設けられている。すなわち、このアルミニ
ウム配線層７はスクライブ線のＰ＋拡散層８に接続され
ている。An aluminum wiring layer 7 at a substrate potential is provided at a distance dl from the input protection device 14 (as shown in the circuit diagram of FIG. 3) (greater than the distance d2 between the input protection device 14 and the internal circuit area lb). ing. That is, this aluminum wiring layer 7 is connected to the P+ diffusion layer 8 of the scribe line.
アルミニウム配線層７にコンタクト孔６を介して接続さ
れたＮ＋型型数散層５形成されており、そのＮ”型拡散
層５と一定の距離ｄ３を隔ててＮウェル４が形成されて
いる。Ｎウェル４内には、接地レベルのアルミニウム配
線層１にコンタクト孔３を介して接続されたＮ＋型型数
散層２形成されておりＮウェル４を接地レベルに保って
いる。An N+ type diffused layer 5 is formed connected to the aluminum wiring layer 7 through a contact hole 6, and an N well 4 is formed at a constant distance d3 from the N'' type diffused layer 5. In the N well 4, an N+ type scattering layer 2 is formed which is connected to the aluminum wiring layer 1 at the ground level through a contact hole 3, and keeps the N well 4 at the ground level.
Ｎ１型拡散層２．５、Ｐ＋型拡散層８間にはそれぞれ厚
いフィールド酸化Ｍ１１が形成されており、最上層にカ
バー膜９が形成されている。なお、Ｎ４型拡散層５とＮ
ウェル４の距離ｄ３はデバイスの信頼性を考慮すると２
０μｍ程度である。A thick field oxide M11 is formed between the N1 type diffusion layer 2.5 and the P+ type diffusion layer 8, and a cover film 9 is formed on the top layer. Note that the N4 type diffusion layer 5 and the N4 type diffusion layer 5
The distance d3 of well 4 is 2 considering the reliability of the device.
It is about 0 μm.
次に本発明の動作について説明する。Next, the operation of the present invention will be explained.
入力ピンに接地端子に対して負の高電圧が印加された場
合、入力保護部に例えばＮ＋型の拡散層抵抗を使用して
いると、パッドのアルミニウム層に接続されたＮ＋型の
拡散層部から基板に大量の電子が注入され、それらの電
子が経路Ｉを通ってパッド周辺のトランジスタの接地レ
ベルのＮ＋型型数散層到達し、アルミニウム層とＮ１型
拡散層のコンタクトに大電力が流れスパイクを引き起こ
す。そのため、パッドのアルミニウム層とＮ＋型型数散
層コンタクト１５は通常、スクライブ線よりに設けられ
る。When a negative high voltage is applied to the input pin with respect to the ground terminal, if an N+ type diffusion layer resistor is used for the input protection section, the N+ type diffusion layer resistor connected to the aluminum layer of the pad will A large amount of electrons are injected into the substrate, and these electrons pass through path I and reach the N+ type diffused layer at the ground level of the transistor around the pad, causing a large amount of power to flow to the contact between the aluminum layer and the N1 type diffusion layer. cause spikes. Therefore, the aluminum layer of the pad and the N+ type scattered layer contact 15 are usually provided closer to the scribe line.
しかし、本発明の補助保護装置を設けると、拡散層抵抗
部より注入された電子は、パッド周辺のトランジスタの
接地レベルの拡散層に到達するよりも、スクライブ線の
アルミニウム配線層７を通ってＮ“型拡散層５がら再び
基板に抜け、すぐ近くの接地レベルのＮウェル４に到達
する（第１図（ａ）の経路■）、つまり、パッドのアル
ミニウム層と接続されたＮ＋型の拡散層抵抗の部分から
パッドの周辺のトランジスタの接地レベルのＮ＋型型数
散層到達するまでの基板抵抗より、パッドのアルミニウ
ムと接続されたＮ”型の拡散層の部分からスクライブ線
への基板抵抗と、パッドに対応する位買から補助保護領
域までのスクライブ線のアルミニウム配線層７の抵抗と
、Ｎ＋型型数散層５ら基板を通してＮウェル４までの抵
抗との合計の抵抗値の方がかなり小さいので、大部分の
電流は、接地レベルのＮウェル４からパッドに流れ込む
。そのため、パッドの周辺でアルミニウムスパイクが発
生しない。しかも、接地レベルのＮウェル４内には接地
レベルのアルミニウム配線層ｌとＮ＋型型数散層２コン
タクト孔３があるが、アルミニウムスパイクが発生して
も、Ｎウェル４に囲まれているために問題はない。However, when the auxiliary protection device of the present invention is provided, the electrons injected from the diffusion layer resistor pass through the aluminum wiring layer 7 of the scribe line, rather than reaching the diffusion layer at the ground level of the transistor around the pad. “The type diffusion layer 5 passes through the substrate again and reaches the nearby N well 4 at the ground level (route ■ in Fig. 1(a)), that is, the N+ type diffusion layer connected to the aluminum layer of the pad. The substrate resistance from the N'' type diffusion layer connected to the aluminum of the pad to the scribe line is greater than the substrate resistance from the resistor to the N+ type diffused layer at the ground level of the transistor around the pad. , the total resistance value of the resistance of the aluminum wiring layer 7 of the scribe line from the pad corresponding to the pad to the auxiliary protection area and the resistance from the N+ type scattering layer 5 to the N well 4 through the substrate is considerably larger. Since it is small, most of the current flows into the pad from the N-well 4 at ground level. Therefore, aluminum spikes do not occur around the pad. Furthermore, although there is an aluminum wiring layer 1 at the ground level and an N+ type scattering layer 2 contact hole 3 in the N well 4 at the ground level, even if an aluminum spike occurs, it is surrounded by the N well 4. There is no problem.
また、接地レベルのアルミニウム配線層１を電源レベル
のアルミニウム配線に変えれば、電源端子に対して入力
ビンに負の高電圧が印加された場合の保護機能を持つの
はいうまでしない。Moreover, if the aluminum wiring layer 1 at the ground level is replaced with an aluminum wiring at the power supply level, it goes without saying that a protection function is provided when a negative high voltage is applied to the input bin with respect to the power supply terminal.
なお、本発明は、半導体ＩＣのチップ内のどのような所
に設置されても効果は変わらない、また、上記実施例は
Ｐ型半導体基板であったが、不純物拡散層の電導型を反
対にすればＮ型半導体基板でもよい。Note that the present invention has the same effect no matter where it is installed in the chip of a semiconductor IC.Also, although the above embodiment used a P-type semiconductor substrate, it is possible to reverse the conductivity type of the impurity diffusion layer. If so, an N-type semiconductor substrate may be used.
第２図は本発明の一実施例の変形を示す平面図である。FIG. 2 is a plan view showing a modification of one embodiment of the present invention.
スクライブ線の基板電位のアルミニウム配ｗ１７に接続
されているアルミニウム配線１３がコンタクト孔６を介
してＮ＋型型数散層５接続されており、そのＮ”型拡散
層５と一定の距離を隔てて、まわりを囲むようにＮウェ
ル４が形成されている。Ｎウェル４内には、接地レベル
のアルミニウム配線層１にコンタクト孔３を介して接続
されたＮ＋型型数散層２形成された構造となっている。The aluminum wiring 13 connected to the aluminum wiring w17 of the substrate potential of the scribe line is connected to the N+ type diffused layer 5 through the contact hole 6, and is separated from the N'' type diffused layer 5 by a certain distance. , an N well 4 is formed to surround the periphery.In the N well 4, an N+ type scattered layer 2 is formed which is connected to an aluminum wiring layer 1 at a ground level via a contact hole 3. It becomes.
以上説明した様に、本発明はスクライブ線の基板電位の
金属配線層に接続された半導体基板と逆導電型の第１の
不純物拡散層、前記第１の不純物拡散層と所定の距離を
隔てて設けられた半導体基板と逆導電型のウェルおよび
前記ウェル内に設けられた。接地レベル又は電源レベル
の金属配線層に接続された半導体基板と逆導電型の第２
の不純物拡散層を有する補助保護装置を設けることによ
って、入力端子に印加された負の高電圧に対して耐圧を
向上させることができる。また、半導体ＩＣのチップの
どのような場所にも設置できるのでレイアウト的に構成
が容易であるという効果を有する。As explained above, the present invention includes a semiconductor substrate connected to a metal wiring layer at a substrate potential of a scribe line, a first impurity diffusion layer of an opposite conductivity type, and a first impurity diffusion layer separated from the first impurity diffusion layer by a predetermined distance. A well having a conductivity type opposite to that of the provided semiconductor substrate and a well provided within the well. A second conductivity type opposite to the semiconductor substrate connected to the metal wiring layer at the ground level or power supply level.
By providing the auxiliary protection device having the impurity diffusion layer, it is possible to improve the withstand voltage against the negative high voltage applied to the input terminal. Furthermore, since it can be installed at any location on a semiconductor IC chip, it has the effect of simplifying the configuration in terms of layout.
ルミニウム配線層、１４・・・入力保護装置（パッドを
含む）、１５・・・パッドのアルミニウム層とＮ＋型の
拡散層抵抗の接続部、１６・・・内部回路領域、１７・
・・補助保護装置。aluminum wiring layer, 14...input protection device (including pad), 15... connection portion between aluminum layer of pad and N+ type diffusion layer resistor, 16... internal circuit area, 17.
...Auxiliary protection device.
第１図（ａ）は本発明の一実施例の全体構成を示す平面
図、第１図（ｂ）は一実施例における補助保護装置の平
面図、第１図（ｃ）は第１図（ｂ）のＡ−Ａ線断面図、
第２図は一実施例の変形を示す平面図、第３図は従来の
入力保護装置の等価回路である。FIG. 1(a) is a plan view showing the overall configuration of one embodiment of the present invention, FIG. 1(b) is a plan view of an auxiliary protection device in one embodiment, and FIG. AA line cross-sectional view of b),
FIG. 2 is a plan view showing a modification of one embodiment, and FIG. 3 is an equivalent circuit of a conventional input protection device.
Claims (1)
保護装置を用いた半導体装置において、前記入力保護装
置と所定の距離を隔てて設けられた、スクライブ線の基
板電位の金属配線層と、前記金属配線層に接続された、
半導体基板と逆導電型の第１の不純物拡散層、前記第１
の不純物拡散層と所定の距離隔てて設けられた半導体基
板と逆導電型のウェル及び前記ウェル内に設けられた、
接地レベル又は電源レベルの金属配線層に接続された半
導体基板と逆導電型の第２の不純物拡散層を有する補助
保護装置が設けられていることを特徴とする半導体装置
。 ２、第１の不純物拡散層が第２の不純物拡散層で囲まれ
ている請求項１記載の半導体装置。[Claims] 1. In a semiconductor device using an input protection device having an impurity diffusion layer of a conductivity type opposite to that of the semiconductor substrate, a substrate potential of a scribe line provided at a predetermined distance from the input protection device. a metal wiring layer connected to the metal wiring layer;
a first impurity diffusion layer of a conductivity type opposite to that of the semiconductor substrate;
a well of a conductivity type opposite to that of the semiconductor substrate, which is provided at a predetermined distance from the impurity diffusion layer of the semiconductor substrate; and a well provided within the well;
A semiconductor device comprising an auxiliary protection device having a second impurity diffusion layer of a conductivity type opposite to that of a semiconductor substrate connected to a metal wiring layer at a ground level or a power supply level. 2. The semiconductor device according to claim 1, wherein the first impurity diffusion layer is surrounded by a second impurity diffusion layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25778690A JPH04134855A (en) | 1990-09-27 | 1990-09-27 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25778690A JPH04134855A (en) | 1990-09-27 | 1990-09-27 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04134855A true JPH04134855A (en) | 1992-05-08 |
Family
ID=17311088
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25778690A Pending JPH04134855A (en) | 1990-09-27 | 1990-09-27 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04134855A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6787432B2 (en) | 1999-08-12 | 2004-09-07 | Oki Electric Industry Co., Ltd. | Semiconductor device |
| US6879025B2 (en) * | 1997-08-29 | 2005-04-12 | Kabushiki Kaisha Toshiba | Semiconductor device incorporating a dicing technique for wafer separation and a method for manufacturing the same |
-
1990
- 1990-09-27 JP JP25778690A patent/JPH04134855A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6879025B2 (en) * | 1997-08-29 | 2005-04-12 | Kabushiki Kaisha Toshiba | Semiconductor device incorporating a dicing technique for wafer separation and a method for manufacturing the same |
| US7176061B2 (en) | 1997-08-29 | 2007-02-13 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
| US7576411B2 (en) | 1997-08-29 | 2009-08-18 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
| US6787432B2 (en) | 1999-08-12 | 2004-09-07 | Oki Electric Industry Co., Ltd. | Semiconductor device |
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