JPH04131960A - Computer operating method and computer system - Google Patents
Computer operating method and computer systemInfo
- Publication number
- JPH04131960A JPH04131960A JP2251868A JP25186890A JPH04131960A JP H04131960 A JPH04131960 A JP H04131960A JP 2251868 A JP2251868 A JP 2251868A JP 25186890 A JP25186890 A JP 25186890A JP H04131960 A JPH04131960 A JP H04131960A
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- 238000011017 operating method Methods 0.000 title description 4
- 230000015654 memory Effects 0.000 claims abstract description 75
- 238000012545 processing Methods 0.000 claims abstract description 63
- 230000005540 biological transmission Effects 0.000 claims abstract description 36
- 238000004364 calculation method Methods 0.000 claims description 31
- 238000000034 method Methods 0.000 claims description 16
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 15
- 230000000737 periodic effect Effects 0.000 claims description 5
- 238000001514 detection method Methods 0.000 abstract 2
- 230000008569 process Effects 0.000 description 14
- 238000010586 diagram Methods 0.000 description 10
- 238000007781 pre-processing Methods 0.000 description 6
- 230000001360 synchronised effect Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000012546 transfer Methods 0.000 description 3
- 230000004044 response Effects 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
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Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、複数の計算機が同期をとりながら処理の分担
を行っている計算機システムに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a computer system in which a plurality of computers share processing while maintaining synchronization.
複数の計算機の同期をはかった従来例には、特開昭63
−291156号公報がある。はこの従来例は、各計算
機に対し、後段の計算機へ印加する同期信号時点を、前
段の同期信号発生時点からその前段の計算機の処理に要
する時間よりも長くずらしたものとした。この結果、シ
ステム全体としての処理時間の短縮、つまりロスタイム
の削減を図った。A conventional example of synchronizing multiple computers is JP-A-63
There is a publication No.-291156. In this conventional example, for each computer, the timing of the synchronization signal applied to the subsequent computer is shifted from the generation time of the synchronization signal of the previous stage by a longer time than the time required for processing in the previous stage computer. As a result, the processing time of the entire system was shortened, in other words, loss time was reduced.
具体的に従来例を説明する。第6図は従来例のブロック
図、第7図は従来例のタイミングチャートである。この
従来例は、多段結合された複数の計算機へ、個々の計算
機毎に定期時間分の位相差をもった同期信号を与えて、
処理を実行するものである。即ち、この従来例は、1台
の同期信号発生部62と3台のカスケード接続された計
算機#1〜# 3 (61〜63)とを有し、同期信号
発生部62は、クロック回路66と、それぞれ異なるタ
イミングの同期信号71〜73を発生する同期信号発生
部63.64゜65とを有する。計算機# 1 (61
)は第1の同期信号発生回路63により同期信号71(
71a、 71b、・・・)毎に演算処理(711a、
711b、 −)と送信処理(712a、712b。A conventional example will be specifically explained. FIG. 6 is a block diagram of the conventional example, and FIG. 7 is a timing chart of the conventional example. In this conventional example, a synchronization signal having a phase difference of a fixed time period is given to each computer to a plurality of computers connected in multiple stages.
It executes processing. That is, this conventional example has one synchronization signal generation section 62 and three cascade-connected computers #1 to #3 (61 to 63), and the synchronization signal generation section 62 has a clock circuit 66 and three computers #1 to #3 (61 to 63) connected in cascade. , and synchronous signal generating sections 63, 64 and 65 that generate synchronous signals 71 to 73 at different timings, respectively. Calculator #1 (61
) is generated by the first synchronization signal generation circuit 63 as the synchronization signal 71 (
Computation processing (711a, 71b, ...) is performed for each
711b, -) and transmission processing (712a, 712b).
・・・)を行い、計算機$ 2 (62)はそれらの処
理の合計時間(t+ + tIs)よりも長い時間t1
2なる位相差をもつ同期信号72(72a、 72b、
・・・)によって演算処理(722a、 722b、
・・・)と送信処理(723a、 723b。), and the computer $ 2 (62) takes a time t1 longer than the total time (t+ + tIs) for those processes.
Synchronization signals 72 (72a, 72b,
) performs arithmetic processing (722a, 722b,
) and transmission processing (723a, 723b).
・・・)を行う。計算機# 3 (63)も同様に計算
機#2(62)の処理の合計時間(t2+t2s)より
も長い時間t23なる位相差をもった同期信号73 (
73a 、 73b 。···)I do. Computer #3 (63) similarly generates a synchronization signal 73 (
73a, 73b.
・・・)毎に演算(732a、 732b、・・・)を
行う。...), the calculations (732a, 732b, ...) are performed for each step.
上記従来例を適用する為には、前記のように各計算機に
対するデータ転送の開始タイミングを始めとして、全体
の処理時間を把握することが前提となる。音声や映像の
リアルタイムシュミレーションの制御を行う多段階のマ
ルチプロセッサシステムにおいては、個々の計算機の処
理内容やデータ転送量が逐次変化する場合があり、デー
タ転送の開始時間を一義的に決定することができない。In order to apply the above-mentioned conventional example, it is necessary to know the entire processing time, including the start timing of data transfer to each computer as described above. In a multi-stage multiprocessor system that controls real-time simulation of audio and video, the processing content and data transfer amount of individual computers may change sequentially, so it is difficult to uniquely determine the start time of data transfer. Can not.
したがって、制御を統括するホスト計算機からはそれら
の個々の計算機に対する処理開始のタイミングの確立が
不可能となる為、この様なシステムには適用できなくな
る点が問題となる。Therefore, the problem is that it is impossible to establish the timing of starting processing for each computer from the host computer that is in charge of controlling the system, so that it cannot be applied to such a system.
更に従来例は、各計算機関のデータの送信及び受信処理
の時間(tls+ t2r+ j2s+ t3r)が演
算時間に比べ極めて短い場合は問題ないが、それが長く
なってくると同期信号がサイタイムto内の演算時間(
t+、 j2+ t3)が削減されることになりスルー
プットの低下につながる。逆にtQ内のスループレット
を向上させようとすれば今度はデータの送受信処理(t
est j2r+ test j3r)の時間を十分に
確保できなくなる。したがって、この方式ではデータの
転送量が多い場合や負荷率の高い処理を要求されるシス
テムに対して有効ではなし\。Furthermore, in the conventional example, there is no problem if the time for data transmission and reception processing (tls + t2r + j2s + t3r) of each computing engine is extremely short compared to the calculation time, but if it becomes longer, the synchronization signal will be lost within the synchronization time to. Computation time (
t+, j2+t3), which leads to a reduction in throughput. Conversely, if we try to improve the throughput within tQ, we will need to increase the data transmission/reception processing (t
est j2r+ test j3r) will not be able to secure enough time. Therefore, this method is not effective for systems that require a large amount of data to be transferred or for systems that require processing with a high load rate.
また、従来の方式においては計算機1台毎に個別の同期
信号を与えなければならない為、大規模かつ複雑化した
システム構成の場合法の点が問題となる。Furthermore, in the conventional method, an individual synchronization signal must be given to each computer, which poses a problem in terms of suitability for large-scale and complicated system configurations.
(I)計算機の台数毎に同期信号を発生させるハードウ
ェアロジックを必要とし、さらに全計算機毎の処理時間
を把握しない限り各計算機毎の同期信号の位相差の設定
が不可能。(I) It requires hardware logic to generate a synchronization signal for each number of computers, and it is impossible to set the phase difference of the synchronization signals for each computer unless the processing time for each computer is known.
(2)計算機関の接続変更や処理時間の変更が生じた場
合、特定の計算機のみならず、すべての同期信号の位相
差の再設定を強いられる可能性がある。(2) If the connection of a computing engine or the processing time changes, it may be necessary to reset the phase difference of not only a specific computer but also all synchronizing signals.
これは、ソフトウェアのデパック時、システムの立ち上
げ時や保守点検時の作業効率を著しく低下させるもので
ある。This significantly reduces work efficiency during software depacking, system startup, and maintenance/inspection.
本発明は、以上述べた問題点を解決し、さらにシステム
としてのスループットを最大限に向上させる計算機の運
転方法及び、計算機システムを提供することを目的とす
る。It is an object of the present invention to provide a computer operating method and a computer system that solve the above-mentioned problems and further improve the throughput of the system to the maximum extent possible.
本発明の計算機の運転方法は、計算機内にあっては、演
算部からのアクセスと送受信部からのアクセスを同時に
行うことのできる交代バッファメモリを用いて、演算部
と送受信部の動作を独立化し、全計算機共通の同期信号
により、演算処理とデータの送受信処理を同時に開始さ
せ、同期信号1サイクル内に処理を完了させるようにし
た。The computer operating method of the present invention uses an alternating buffer memory in the computer that can be accessed simultaneously from the arithmetic unit and the transmitter/receiver, thereby making the operations of the arithmetic unit and the transmitter/receiver independent. By using a common synchronization signal for all computers, arithmetic processing and data transmission/reception processing are started at the same time, and the processing is completed within one cycle of the synchronization signal.
(請求項1)。(Claim 1).
更に、本発明の計算機システムは、各計算機にあっては
、演算部と、他の計算機との交信用の送受信部と、演算
部と送受信部との間に設けた2つの交代バッファメモリ
と、該2つの交代バッファメモリを、同期信号に同期し
て、演算部用と送受信部用とに、交互に切替える切替部
とを有する(請求項2)。Furthermore, in the computer system of the present invention, in each computer, a calculation section, a transmission/reception section for communication with other computers, two alternating buffer memories provided between the calculation section and the transmission/reception section, A switching section is provided that alternately switches the two alternating buffer memories for use in the arithmetic section and for use in the transmission/reception section in synchronization with a synchronization signal (claim 2).
更に本発明の計算機システムは、各計算機内にあっては
、演算部と、他の計算機との交信用の送信部と、演算部
と送受信部との間に設けた2つの交代バッファメモリと
、該2つの交代バッファメモリを、演算部用と送受信部
用とに、交互に切替える切替部と、より成り、各計算機
内の演算部は。Furthermore, the computer system of the present invention includes, in each computer, a calculation section, a transmission section for communicating with other computers, and two alternating buffer memories provided between the calculation section and the transmission/reception section; The arithmetic unit in each computer is comprised of a switching unit that alternately switches the two alternating buffer memories to one for the arithmetic unit and one for the transmitting/receiving unit.
上記同期信号が入力する毎に、上記切替部を働かせて2
つのバッファメモリを、一方は演算部用に。Each time the synchronization signal is input, the switching section is activated to
Two buffer memories, one for the calculation section.
他方は送受信部用に、交互に切替えさせるものとし、且
つすべての演算部とすべての送受信部とは同期信号に同
期して、対応するバッファメモリとの間で演算処理、送
受信処理を独立で行うものとする(請求項3)。The other is for the transmitter/receiver unit and is switched alternately, and all the arithmetic units and all the transmitter/receivers independently perform arithmetic processing and transmission/reception processing with the corresponding buffer memory in synchronization with a synchronization signal. (Claim 3)
更に本発明の計算機システムは、互いにカスケード接続
された3台以上の計算機での初段の計算機は、演算部と
、次段の計算機への送信部と、演算部と送信部との間に
設けた2つの交代バッファメモリと、該2つの交代バッ
ファメモリを演算部用と送受信部用とに交互に切替える
切替部と、より成り、中段の計算機は、前段の計算機か
らの受信部と、演算部と、次段の計算機への送信部と、
上記受信部と演算部との間に設けた2つの交代バラフア
メモリ(I)と、該2つの交代バッファメモリ(I)を
上記受信部用と演算部用とに、交互に。Further, in the computer system of the present invention, in three or more computers connected in cascade to each other, the first-stage computer is provided with an arithmetic section, a transmitting section to the next-stage computer, and between the arithmetic section and the transmitting section. It consists of two alternating buffer memories, and a switching section that alternately switches the two alternating buffer memories to one for an arithmetic section and one for a transmitting/receiving section. , a transmitter to the next computer,
Two alternating buffer memories (I) are provided between the receiving section and the calculating section, and the two alternating buffer memories (I) are alternately used for the receiving section and for the calculating section.
切替える第1の切替部と、上記演算部と送信部との間に
設けた2つのバッファメモリ(■)と、該2つの交代バ
ッファメモリ(II)を演算部用と送信部用とに、交互
に、切替える第2の切替部と、より成り、最終段の計算
機は、前段の計算機からの受信部と、演算部と、該受信
部と演算部との間に設けた2つの交代バッファメモリと
、該2つの交代バッファメモリを該受信部用と演算部用
とに、交互に切替える切替部と、より成り、各計算機内
の演算部は、同期信号が入力する毎に、上記各切替部を
働かせて各2つの交代バッファメモリを、方は演算部用
、他方は受信部用と送信部用に、交互に、切替えるもの
とし、且つすべての演算部、すべての受信部、すべての
送信部は、上記同期信号に同期して対応するバッファメ
モリとの間で、演算処理、受信処理、送信処理を行うも
のとする(請求項4)。The first switching section to be switched, the two buffer memories (■) provided between the arithmetic section and the transmitting section, and the two alternating buffer memories (II) are alternately used for the arithmetic section and for the transmitting section. The final stage computer includes a receiving part from the previous stage computer, a calculating part, and two alternating buffer memories provided between the receiving part and the calculating part. , a switching section that alternately switches the two alternate buffer memories for the receiving section and the computing section, and the computing section in each computer switches each of the switching sections each time a synchronization signal is input. Each of the two alternating buffer memories is switched alternately, one for the calculation section and the other for the reception section and the transmission section, and all the calculation sections, all reception sections, and all transmission sections are switched. , and a corresponding buffer memory in synchronization with the synchronization signal, arithmetic processing, reception processing, and transmission processing are performed (claim 4).
更に本発明の計算機システムは、複数台の計算機からの
入力を受け、複数台の計算機へ処理結果を出力する計算
機と、各計算機へ完全同期した同期信号を発生する同期
信号発生部とを有し、該計算機は、入力側の複数台の計
算機対応の受信部と、演算部と、該各受信部と演算部と
の間に設けた2つの交代バッファメモリ群(I)と、出
力側の複数の計算機対応の送信部と、上記演算部と各送
信部との間に設けた2つの交代バッファメモリ群(II
)と、上記2つの交代バッファメモリ群(I)を受信部
用と演算部用とに、上記同期信号に同期して、切替える
第1の切替部と、上記2つの交代バッファメモリ群(I
I)を演算部用と送信部用とに、上記同期信号に同期し
て切替える第2の切替部と、より成る(請求項5)。Furthermore, the computer system of the present invention includes a computer that receives input from a plurality of computers and outputs processing results to the plurality of computers, and a synchronization signal generator that generates a completely synchronized synchronization signal to each computer. , the computer includes a receiving section compatible with a plurality of computers on the input side, an arithmetic section, two alternating buffer memory groups (I) provided between each of the receiving sections and the arithmetic section, and a plurality of computers on the output side. a computer-compatible transmitter, and two alternating buffer memory groups (II) provided between the arithmetic unit and each transmitter.
), a first switching section that switches the two alternating buffer memory groups (I) into one for the receiving section and one for the arithmetic section in synchronization with the synchronizing signal, and
I) for the arithmetic section and for the transmitting section, and a second switching section that switches I) in synchronization with the synchronization signal (claim 5).
本発明の計算機の運転方法及び計算機システムにおいて
は、複数の計算機のすべてに対して共通の同期信号によ
り、演算部と送受信部が独立して動作し、その同期信号
の1サイクル内に各々が所定の処理を特徴する請求項1
,1.3)。それによって、以下の作用を得る。In the computer operating method and computer system of the present invention, the arithmetic unit and the transmitting/receiving unit operate independently using a common synchronization signal for all of the plurality of computers, and each of them operates in a predetermined manner within one cycle of the synchronization signal. Claim 1 characterized by the processing of
, 1.3). As a result, the following effects are obtained.
(I)各計算機毎の送受信処理によるロスタイムがなく
、1サイクル内のスループットを最大限に確保できる。(I) There is no loss time due to transmission/reception processing for each computer, and the maximum throughput within one cycle can be ensured.
(2)各計算機毎の演算処理時間及び送受信時間を考慮
することなく計算機関のあらゆる接続形態に対応し、か
つ接続変更も容易にできる。(2) It is compatible with all types of connection of computing institutions without considering the calculation processing time and transmission/reception time of each computer, and the connection can be easily changed.
更に本発明の計算機システムにおいては、3台以上の計
算機がカスケード接続された計算機システムにおいて、
初段の計算機での演算と送信、中段の計算機での受信と
演算と送信、最終段の計算機での受信と演算とが、完全
周期のもとて切替られ、且つそれぞれの処理では2交代
バッファメモリを採用して、それぞれの処理に必要なバ
ッファメモリが選択される(請求項4)。これにより、
カスケード接続された計算機システムでのスループット
が向上する。Furthermore, in the computer system of the present invention, in a computer system in which three or more computers are connected in cascade,
Calculation and transmission in the first-stage computer, reception, calculation, and transmission in the middle-stage computer, and reception and calculation in the final-stage computer are switched in a complete cycle, and two-alternate buffer memory is used for each process. The buffer memory necessary for each process is selected by employing the following (claim 4). This results in
Throughput in cascade-connected computer systems is improved.
更に本発明の計算機システムにおいては、複数台の計算
機からの入力を受け、複数台の計算機へ処理結果を出力
する計算機にあっては、その入力対応及び出力対応に交
代バッファメモリを用いて受信、演算、送信を、同期し
て行うことができる(請求項5)。これにより、並列入
力、並列出力を行う計算機にあっては、スループットの
向上をはかれる。Furthermore, in the computer system of the present invention, in a computer that receives input from a plurality of computers and outputs processing results to the plurality of computers, alternate buffer memories are used to handle the input and output. Calculation and transmission can be performed synchronously (claim 5). As a result, in computers that perform parallel input and output, throughput can be improved.
以下に本発明の詳細な説明する。 The present invention will be explained in detail below.
本発明の実施例の全体構成図を第1図に示す。FIG. 1 shows an overall configuration diagram of an embodiment of the present invention.
計算機# 1 (I1)は、演算部111と接続バス1
15゜116を交互に切替えることのできる交代バッフ
ァメモリ112.113、その切替えを行う切替部11
7及び計算機$ 2 (I2)へデータを転送する為の
送信部114にて構成される。計算機# 2 (I2)
は、計算機$ 1 (I1)と同様に演算部124、バ
ッファメモリ125゜126、送信部127に加え、受
信部121.バッフ7メモリ122.123.及び切替
部128A、 128Bより構成される。計算機# 3
(I3)は、計算機# 2 (I2)と同様の受信部
131、バッファメモリ132.133及び演算部13
4.切替部135より構成される。ここで、送信部と受
信部は、いずれも起動信号によりデータ転逆処理単独で
行う回路である。更に演算部とはCPUとプログラムを
格納するメモリとを含むものである。Computer #1 (I1) is connected to the calculation unit 111 and the connection bus 1.
Alternate buffer memories 112 and 113 that can alternately switch between 15° and 116, and a switching unit 11 that performs the switching
7 and a transmitter 114 for transmitting data to the computer $2 (I2). Calculator #2 (I2)
Like the computer $ 1 (I1), in addition to the arithmetic unit 124, buffer memories 125, 126, and transmitter 127, the receiver 121 . Buffer 7 memory 122.123. and switching sections 128A and 128B. Calculator #3
(I3) includes a receiving section 131, buffer memory 132, 133, and calculation section 13 similar to computer #2 (I2).
4. It is composed of a switching section 135. Here, both the transmitting section and the receiving section are circuits that independently perform data inversion processing in response to an activation signal. Furthermore, the arithmetic unit includes a CPU and a memory that stores programs.
まず、計算機全体の同期をとる為の同期信号発生部15
に対し、システムの動作を開始させる為の起動制御部1
4からの起動信号145が与えられ、クロック回路15
1からのクロック信号153をもとに同期信号発生回路
152より同一位相の同期信号154゜155、156
を出力し、それぞれ計算機#1,32゜# 3(I1,
12,13)に与えられる。First, a synchronization signal generator 15 for synchronizing the entire computer.
In contrast, a startup control unit 1 for starting the operation of the system
A start signal 145 from clock circuit 15 is applied to clock circuit 15.
Based on the clock signal 153 from 1, the synchronous signal generation circuit 152 generates synchronous signals 154° 155, 156 of the same phase.
, and output them respectively from computers #1 and 32゜#3 (I1,
12, 13).
計算機31 (I1)は、第2図に示す同期信号154
の最初のパルス154aを検出するとまず演算部111
が処理111aを実行し、その結果をバッファメモリ1
12へ格納する。計算機# 1 (I1)は、演算処理
111aが終了した時点で、切替部117を働かせて、
バッファメモリ112と113に接続されているパスラ
イン115と116を切替え、バッファメモリ112は
受信部114に、バッファメモリ113は演算部111
に接続される。次に、計算機# 1 (I1)は同期信
号145bを検出すると、演算部111が演算111b
を実行してバッファメモリ113八結果を格納すると同
時に送信部114はバッファメモリ112の内容を計算
機#2(I2)に対して送信する為の送信処理114a
を行う。The computer 31 (I1) receives the synchronization signal 154 shown in FIG.
When the first pulse 154a of
executes the process 111a and stores the result in the buffer memory 1.
12. When the calculation process 111a is completed, the computer #1 (I1) activates the switching unit 117,
Switch the path lines 115 and 116 connected to the buffer memories 112 and 113, so that the buffer memory 112 is connected to the receiving section 114, and the buffer memory 113 is connected to the calculation section 111.
connected to. Next, when the computer #1 (I1) detects the synchronization signal 145b, the calculation unit 111 performs the calculation 111b.
At the same time as executing and storing the results in the buffer memory 113, the transmitter 114 performs a transmitting process 114a to transmit the contents of the buffer memory 112 to the computer #2 (I2).
I do.
その後計算機# 1 (I1)は、同期信号154の各
パルス(I54c、 154d、 154e、 −)を
検出する毎に以上の動作をくり返す。Thereafter, computer #1 (I1) repeats the above operation every time it detects each pulse (I54c, 154d, 154e, -) of the synchronization signal 154.
計算機# 2 (I2)は、同期信号155(I55a
=155d)を検出するたびに、バッファメモリ122
と123を受信部128と演算部124に対して交互に
接続を切替えながら、計算機# 1 (I1)からの送
信データの送出と共に直ちに受信可能な状態としている
。よって、計算機$ 1 (H)の送信処理114aが
行われると同時に、計算機# 2 (I2)は受信処理
121aを行い、その受信データはバッファメモリ12
2へ格納される。Computer #2 (I2) receives synchronization signal 155 (I55a
= 155d), the buffer memory 122
and 123 are alternately connected to the receiving section 128 and the calculating section 124, so that they can immediately receive transmission data from the computer #1 (I1) as soon as it is sent. Therefore, at the same time as the transmission processing 114a of computer $ 1 (H) is performed, the computer # 2 (I2) performs the reception processing 121a, and the received data is stored in the buffer memory 12.
2.
この時、バッファメモリ123は演算部124へ接続さ
れているが、受信データが空の状態であり、演算処理は
実行されない6次に、計算機# 2 (I2)は、同期
信号155aを検出することにより、バッファメモリ1
22を演算部124へ、バッファメモリ123を受信部
121へ接続し、計算機# 1 (I1)からの次のデ
ータが送出されるのを待ち、送信処理114bと同時に
受信処理121bを行い受信データはバッファメモリ1
23へ格納される。また、この処理と平行して、演算部
124は、同期信号155aの検出直後に受信処理12
1a格納したバッファメモリ122のデータをもとに演
算処理124aを行い、その結果がバッファメモリ12
5へ格納される。そして、計算機$ 2 (I2)が同
期信号155bを検出するとバッファメモリ122は受
信部121、バッファメモリ123は演算部124、バ
ッファメモリ125は送信部127、バッファメモリ1
26は演算部124へと切り替わり、この時点で受信処
理121c、演算処理124b、送信処理127aを並
列に行うこととなる。以降計算機#2は、同期信号(I
15a、 115b、 115c、 −)を検出する毎
に以上の動作をくり返す。At this time, the buffer memory 123 is connected to the arithmetic unit 124, but the received data is empty and no arithmetic processing is performed.Next, the computer #2 (I2) detects the synchronization signal 155a. Therefore, buffer memory 1
22 to the arithmetic unit 124 and the buffer memory 123 to the receiving unit 121, wait for the next data to be sent from computer #1 (I1), and perform the receiving process 121b at the same time as the sending process 114b. Buffer memory 1
23. Further, in parallel with this process, the calculation unit 124 performs a reception process 12 immediately after detecting the synchronization signal 155a.
Arithmetic processing 124a is performed based on the data in the buffer memory 122 stored in 1a, and the result is stored in the buffer memory 12.
5. Then, when the computer $ 2 (I2) detects the synchronization signal 155b, the buffer memory 122 is connected to the reception section 121, the buffer memory 123 is connected to the calculation section 124, the buffer memory 125 is connected to the transmission section 127, and the buffer memory 1
26 switches to the arithmetic unit 124, and at this point, a reception process 121c, an arithmetic process 124b, and a transmission process 127a are performed in parallel. Thereafter, computer #2 receives the synchronization signal (I
15a, 115b, 115c, -) is detected, the above operation is repeated.
計算機$ 3 (I3)は、まず計算機# 2 (I2
)からのデータを受信処理131aにて受診し、バッフ
ァメモリ132へ格納する。次に、同期信号156aを
検出することにより、バッファメモリ132は演算部1
34、バッファメモリ133は受信部131へと切り替
わり、受信部131が受信処理131bを行い、それと
同時に演算部134はバッファメモリ132のデータを
もとに、演算処理134aを行う。その後同様に同期信
号156(I56a、 165b、・・・)を検出する
毎にバッファメモリ132、133の接続を切替えなが
ら以上の動作をくり返す。Calculator $ 3 (I3) first uses computer # 2 (I2
) is received in the reception process 131a and stored in the buffer memory 132. Next, by detecting the synchronization signal 156a, the buffer memory 132
34, the buffer memory 133 is switched to the receiving section 131, and the receiving section 131 performs receiving processing 131b, and at the same time, the calculating section 134 performs calculating processing 134a based on the data in the buffer memory 132. Thereafter, the above operation is repeated while switching the connections between the buffer memories 132 and 133 every time the synchronizing signal 156 (I56a, 165b, . . . ) is detected.
このように、計算機#1. $2. $3(I1,12
゜13)は、演算とデータの送受信処理を同期信号の検
出と同時に開始し、それらは独立化した回路により並列
に行われることとなる。また、これらの処理時間jll
r t12νj21 r i22+ j23y i3
1 pt32は、周期信号の周期to以内の設定として
いる。したがって、各計算毎の演算処理におけるスルー
プレットをデータの送受信処理によるロスタイムをほと
んど意識せずに周期to内に最大限に確保することがで
きる。さらに、計算期間の接続は、互いの処理時間を考
慮することなく変更等が容易にできる。In this way, calculator #1. $2. $3 (I1,12
13), calculation and data transmission/reception processing are started at the same time as the synchronization signal is detected, and these are performed in parallel by independent circuits. In addition, these processing times
r t12νj21 r i22+ j23y i3
1 pt32 is set within the period to of the periodic signal. Therefore, the maximum throughput in arithmetic processing for each calculation can be secured within the period to without being aware of loss time due to data transmission and reception processing. Furthermore, the connection of calculation periods can be easily changed without considering each other's processing time.
なお1水力式を応用すれば、特有の効果として前記の一
次元的な接続形態のみならず、第3図のブロック図に示
すように二次元的な多重結合状態の接続をも容易に行う
ことができる。第3図を詳述する。If the 1-hydraulic type is applied, a unique effect is that not only the above-mentioned one-dimensional connection form but also two-dimensional multiple connection state as shown in the block diagram of Fig. 3 can be easily performed. I can do it. FIG. 3 will be explained in detail.
この実施例は、8台の計算機#1〜$8(31〜38)
と、1台の周期信号発生装置39と、より成る。This example uses eight computers #1 to $8 (31 to 38).
and one periodic signal generator 39.
計算機32.36.38は1人力と1出力の入出力の例
、計算機31.35は、2出力、3出力の例、計算機3
3゜37は2人力、3人力の例、計算機34は、2人力
と2出力の例である。同期信号発生装置39は、クロッ
ク回路39Bと、同期信号発生回路39Aとより成り、
各計算機31〜38に対して共通な同期信号■〜■を出
力する。Calculator 32.36.38 is an example of input/output with 1 human power and 1 output, Calculator 31.35 is an example of 2 outputs and 3 outputs, Calculator 3
3°37 is an example of two-man power and three-man power, and the computer 34 is an example of two-man power and two outputs. The synchronization signal generation device 39 includes a clock circuit 39B and a synchronization signal generation circuit 39A.
Common synchronization signals (1) to (2) are output to each of the computers 31 to 38.
計算機#1〜# 8 (31〜38)は、第1図に示す
計算機に、データの送受信部を増やした回路(計算機3
4.35.37を指す。)を含んでいる。Computers #1 to #8 (31 to 38) are the same as the computer shown in FIG.
4.35.37. ).
このうち計算機$ 4 (34)を例にとれば、そのブ
ロック図は第4図の構成となり、送受信部及び二重のバ
ッファメモリ部を4対(42,43,45,46゜48
、49.412.414)を設けたものである。更に、
受信部41,44、送信部411.413、演算部47
を有する。この計算機# 4 (34)は、第1図に示
す計算機# 2 (I2)と全く同様に動作する。第5
図に計算機# 4 (34)のタイミングチャートを示
す。計算機#1への同期信号■を、記号51(51a、
51b、・・・)で示す。計算機#4へも同期信号■
が入力するが、これは記号40で示す。信号40と51
とは、同一の同期信号である。同期信号51aにて計算
機# 1 (31)と計算機$ 5 (35)はそれぞ
れ、演算511aと551aを行う。続いて同期信号5
1bによって、計算機#1(31)、計算機$ 5 (
35)、計算機# 5 (34)は、それぞれ処理51
1b、 512a、 551b、 552a、 541
a、 542aを行う。このとき計算機$ 4 (34
)は、受信部41.44により計算機# 1 (31)
、計算機$ 5 (35)からのデータを個別に受信す
る。そして、計算機# 4 (34)は同期信号51C
によって、受信処理541b、 542bでデータを受
信しながら、 541a、 542aで受信済みの2種
のデータをもとに演算543aを行う。同期信号51d
の時点で、計算機# 4 (34)は前記と同様に処理
541c、 542c、 543bを行いながら、演算
543aでの結果のデータを送信部411.413によ
り処理544a 。Taking the computer $4 (34) as an example, its block diagram has the configuration shown in Figure 4, with four pairs of transmitter/receiver sections and double buffer memory sections (42, 43, 45, 46゜48).
, 49.412.414). Furthermore,
Receiving units 41, 44, transmitting units 411, 413, calculation unit 47
has. This computer #4 (34) operates in exactly the same way as computer #2 (I2) shown in FIG. Fifth
The figure shows a timing chart for computer #4 (34). The synchronization signal ■ to computer #1 is sent to symbol 51 (51a,
51b,...). Synchronization signal also to computer #4■
is input, which is indicated by the symbol 40. Signals 40 and 51
are the same synchronization signal. In response to the synchronization signal 51a, the computer #1 (31) and the computer $5 (35) perform operations 511a and 551a, respectively. Next, synchronization signal 5
1b, Calculator #1 (31), Calculator $5 (
35) and computer #5 (34) are respectively processed 51
1b, 512a, 551b, 552a, 541
a, perform 542a. At this time, the calculator $ 4 (34
) is sent to computer #1 (31) by the receiving unit 41.44.
, the computer $5 (35). And computer #4 (34) receives synchronization signal 51C.
Accordingly, while receiving data in reception processing 541b and 542b, calculation 543a is performed based on the two types of data already received in 541a and 542a. Synchronization signal 51d
At the time point, computer #4 (34) performs processing 541c, 542c, and 543b in the same manner as described above, and transmits the data resulting from the calculation 543a to processing 544a by transmitting units 411 and 413.
545aとして、それぞれ計算機# 3 (33)と計
算機#7 (37)へ送呂する。545a, and sent to computer #3 (33) and computer #7 (37), respectively.
このように、本発明は直列のみならず並列的な多重接続
においても容易に動作が可能である。In this manner, the present invention can be easily operated not only in series but also in parallel multiple connections.
この計算機システムを用いての具体例を述べる。A specific example using this computer system will be described.
立体物体を、異なる位置に設置した2台のTVカメラで
撮像し、計算機#1が第1のTVカメラの撮像画像を取
り込むものとし、計算機#5が第2のTVカメラの撮像
画像を取り込むものとする。A three-dimensional object is imaged by two TV cameras installed at different positions, computer #1 captures the image captured by the first TV camera, and computer #5 captures the image captured by the second TV camera. shall be.
そして、第3図の計算機システムがそれら2つの画像を
処理して、ある種の特徴を抽出するものとする。この際
の各計算機#1〜#8の役1?J 44以下の如く設定
する。It is assumed that the computer system shown in FIG. 3 processes these two images and extracts certain features. Role 1 of each calculator #1 to #8 in this case? J44 Set as below.
計算機#1・・・第1画像に対するノイズ除去等の前処
理、
計算機#2・・・前処理結果画像の2値化処理計算機#
5・・・第2画像に対するノイズ除去等の前処理、
計算機#4・・・計算機$1.#5の前処理結果の積和
演算処理。Computer #1: Preprocessing such as noise removal for the first image, Computer #2: Binarization processing computer # of the preprocessing result image
5... Pre-processing such as noise removal on the second image, Computer #4... Computer $1. Product-sum calculation processing of the preprocessing result of #5.
計算機#6・・・前処理結果画像の2値化処理計算機#
8・・・前処理結果画像のエツジ強調処理計算機#3・
・・計算機#2,34の処理結果から特徴I抽出。Computer #6: Binarization processing computer # for preprocessing result images
8... Edge enhancement processing computer #3 for preprocessing result image
... Feature I is extracted from the processing results of computers #2 and #34.
計算機#7・・・計算機#4.$6.118の処理結果
から特徴■抽出、
ここで特徴Iや■とは、画像の性状を示すものである。Calculator #7... Calculator #4. Extraction of feature (2) from the processing result of $6.118, where feature I and (2) indicate the properties of the image.
尚、第1図の計算機#1では1個の送信部、計算機#3
では1個の受信部としたが、これらを区別せずに送受信
部と称しても特に問題はない。In addition, computer #1 in FIG. 1 has one transmitter, computer #3
In the above, one receiving section was used, but there is no particular problem if they are referred to as a transmitting/receiving section without distinction.
本発明によれば、演算部と送信部及び受信部を独立化し
ているので演算部の負荷率を原理的には100パーセン
ト近くまで上げられる効果がある。According to the present invention, since the arithmetic section, the transmitting section, and the receiving section are made independent, there is an effect that the load factor of the arithmetic section can be increased to nearly 100 percent in principle.
また、システムの接続状態が大規模化、複雑化しても、
あらゆるシステム構成に対応でき、かつ接続変更等も容
易にできる。In addition, even if the system connection status becomes larger and more complex,
It is compatible with all system configurations, and connections can be easily changed.
第1図は、本発明のブロック図、第2図はその動作タイ
ミングチャート、第3図は本発明を応用したブロック図
、第4図はその中の1つの計算機内を示すブロック図、
第5図はそのタイミングチャート、第6図は従来の方式
を説明するブロック図、第7図はそのタイミングチャー
トである。
11・・・計算機(#1)、12・・・計算機(32)
、13・・・計算機(#3)、14・・・起動制御部、
15・・・同期信号発生部、31〜38・・・計算機#
1〜#8.39・・・同期信号発生部、61・・・計算
機#1.62・・・計算機#2.63・・・計算機#3
.64・・・第1の同期信号発生回路、65・・・第2
の同期信号発生回路、66・・・第3の同期信号発生回
路、67・・・クロック回路、60・・・同期信号発生
部。
代理人弁理士 秋 本 正 実
第
図
第
図FIG. 1 is a block diagram of the present invention, FIG. 2 is an operation timing chart thereof, FIG. 3 is a block diagram to which the present invention is applied, and FIG. 4 is a block diagram showing the inside of one of the computers.
FIG. 5 is a timing chart thereof, FIG. 6 is a block diagram explaining the conventional system, and FIG. 7 is a timing chart thereof. 11... Calculator (#1), 12... Calculator (32)
, 13... Computer (#3), 14... Start-up control unit,
15... Synchronization signal generation section, 31-38... Computer #
1 to #8.39...Synchronization signal generation unit, 61...Computer #1.62...Computer #2.63...Computer #3
.. 64...First synchronization signal generation circuit, 65...Second
66... Third sync signal generation circuit, 67... Clock circuit, 60... Sync signal generation section. Representative Patent Attorney Tadashi Akimoto Actual Diagram Diagram
Claims (1)
完全同期した同期信号を発生する同期信号発生部とを有
し、各計算機内にあっては、演算部からのアクセスと送
受信部からのアクセスを同時に行うことのできる交代バ
ッファメモリを用いて、演算部と送受信部の動作を独立
化し、全計算機共通の同期信号により、演算処理とデー
タの送受信処理を同時に開始させ、同期信号の1サイク
ル内に処理を完了させるようにした計算機の運転方法。 2、互いに接続された複数台の計算機と、該各計算機へ
完全周期した同期信号を発生する同期信号発生部と、よ
り成り、 上記各計算機は、演算部と、他の計算機との交信用の送
受信部と、演算部と送受信部との間に設けた2つの交代
バッファメモリと、該2つの交代バッファメモリを、上
記同期信号に同期して、演算部用と送受信部用とに、交
互に切替える切替部と、を有する計算機システム。 3、互いに接続された複数台の計算機と、該各計算機へ
、完全周期した同期信号を発生する同期信号発生部と、
より成り、 上記各計算機は、演算部と、他の計算機との交信用の送
受信部と、演算部と送受信部との間に設けた2つの交代
バッファメモリと、該2つの交代バッファメモリを、演
算部用と送受信部用とに、交互に切替える切替部と、よ
り成り、各計算機内の演算部は、上記周期信号が入力す
る毎に、上記切替部を動かせて2つのバッファメモリを
、一方は演算部用に、他方は送受信部用に、交互に、切
替えさせるものとし、且つすべての演算部とすべての送
受信部とは上記周期信号に同期して、対応するバッファ
メモリとの間で演算処理、送受信処理を独立で行うもの
とする計算機システム。 4、互いにカスケード接続された3台以上の計算機と、
該計算機へ完全周期した同期信号を発生する同期信号発
生部と、より成り、 初段の計算機は、演算部と、次段の計算機への送信部と
、演算部と送信部との間に設けた2つの交代バッファメ
モリと、該2つの交代バッファメモリを演算部用と送信
部用とに交互に切替える切替部と、より成り、 中段の計算機は、前段の計算機からの受信部と、演算部
と、次段の計算機への送信部と、上記受信部と演算部と
の間に設けた2つの交代バッファメモリ( I )と、該
2つの交代バッファメモリ( I )を上記受信部用と演
算部用とに、交互に、切替える第1の切替部と、上記演
算部と送信部との間に設けた2つのバッファメモリ(I
I)と、該2つの交代バッファメモリ(II)を演算部用
と送信部用とに、交互に、切替える第2の切替部と、よ
り成り、 最終段の計算機は、前段の計算機からの受信部と、演算
部と、該受信部と演算部との間に設けた2つの交代バッ
ファメモリと、該2つの交代バッファメモリを該受信部
用と演算部用とに、交互に切替える切替部と、より成り
、 各計算機内の演算部は、同期信号が入力する毎に、上記
各切替部を働かせて各2つの交代バッファメモリを、一
方は演算部用、他方は受信部用と送信部用に、交互に、
切替えるものとし、且つすべての演算部、すべての受信
部、すべての送信部は上記同期信号に同期して対応する
バッファメモリとの間で、演算処理、受信処理、送信処
理を行うものとする計算機システム。 5、複数台の計算機からの入力を受け、複数台の計算機
へ処理結果を出力する計算機と、各計算機へ完全周期し
た同期信号を発生する同期信号発生部とを有し、 該計算機は、入力側の複数台の計算機対応の受信部と、
演算部と、該各受信部と演算部との間に設けた2つの交
代バッファメモリ群( I )と、出力側の複数の計算機
対応の送信部と、上記演算部と各送信部との間に設けた
2つの交代バッファメモリ群(II)と、上記2つの交代
バッファメモリ群( I )を受信部用と演算部用とに、
上記同期信号に同期して、切替える第1の切替部と、上
記2つの交代バッファメモリ群(II)を演算部用と送信
部用とに、上記同期信号に同期して切替える第2の切替
部と、より成る計算機システム。[Claims] 1. It has a plurality of computers connected to each other and a synchronization signal generation section that generates a synchronization signal in complete synchronization to each of the computers. Using an alternating buffer memory that can simultaneously access data from the transmitter and receiver, the operation of the arithmetic unit and the transmitter/receiver are made independent, and a synchronization signal common to all computers starts arithmetic processing and data transmission/reception processing at the same time. A method of operating a computer in which processing is completed within one cycle of a synchronization signal. 2. Consists of a plurality of computers connected to each other and a synchronization signal generation section that generates a synchronization signal with a complete cycle to each of the computers. The transmitter/receiver, two alternate buffer memories provided between the arithmetic unit and the transmitter/receiver, and the two alternate buffer memories are alternately used for the arithmetic unit and for the transmitter/receiver in synchronization with the synchronization signal. A computer system comprising: a switching unit that performs switching; 3. A plurality of computers connected to each other, and a synchronization signal generation unit that generates a synchronization signal with a complete period to each of the computers;
Each of the above-mentioned computers includes an arithmetic unit, a transmitting/receiving unit for communicating with other computers, two alternating buffer memories provided between the arithmetic unit and the transmitting/receiving unit, and the two alternating buffer memories. It consists of a switching section that alternately switches between the arithmetic section and the transmitting/receiving section, and each time the periodic signal is input, the arithmetic section in each computer can move the switching section to switch between the two buffer memories. shall be alternately switched between one for the arithmetic unit and the other for the transmitter/receiver, and all the arithmetic units and all the transmitter/receivers will perform arithmetic operations with the corresponding buffer memory in synchronization with the above periodic signal. A computer system that performs processing, transmission and reception independently. 4. Three or more computers connected in cascade to each other,
a synchronization signal generation section that generates a perfectly periodic synchronization signal to the computer; It consists of two alternating buffer memories and a switching section that alternately switches the two alternating buffer memories between the arithmetic section and the transmitting section. , a transmitter for the next stage computer, two alternate buffer memories (I) provided between the receiver and the arithmetic unit, and two alternate buffer memories (I) for the receiver and the arithmetic unit. A first switching section that alternately switches between the two buffer memories (I) provided between the calculation section and the transmission section.
I) and a second switching unit that alternately switches the two alternating buffer memories (II) between the arithmetic unit and the transmitting unit, and the final stage computer receives data from the previous stage computer. a computing section, two alternating buffer memories provided between the receiving section and the computing section, and a switching section that alternately switches the two alternating buffer memories for the receiving section and for the computing section; Each time a synchronization signal is input, the arithmetic section in each computer activates each of the above switching sections to create two alternating buffer memories, one for the arithmetic section, the other for the receiving section and the transmitting section. alternately,
A computer in which all arithmetic units, all receiving units, and all transmitting units perform arithmetic processing, reception processing, and transmission processing with the corresponding buffer memory in synchronization with the synchronization signal. system. 5. It has a computer that receives input from multiple computers and outputs processing results to the multiple computers, and a synchronization signal generator that generates a synchronization signal with a complete period to each computer, and the computer has an input A receiving section compatible with multiple computers on the side,
an arithmetic unit, two alternating buffer memory groups (I) provided between each receiving unit and the arithmetic unit, a transmitting unit compatible with a plurality of computers on the output side, and between the above arithmetic unit and each transmitting unit; The two alternating buffer memory groups (II) provided in
A first switching unit that switches in synchronization with the synchronization signal, and a second switching unit that switches the two alternating buffer memory groups (II) into one for the calculation unit and one for the transmission unit in synchronization with the synchronization signal. A computer system consisting of.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2251868A JPH04131960A (en) | 1990-09-25 | 1990-09-25 | Computer operating method and computer system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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JP2251868A JPH04131960A (en) | 1990-09-25 | 1990-09-25 | Computer operating method and computer system |
Publications (1)
Publication Number | Publication Date |
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JPH04131960A true JPH04131960A (en) | 1992-05-06 |
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Application Number | Title | Priority Date | Filing Date |
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JP2251868A Pending JPH04131960A (en) | 1990-09-25 | 1990-09-25 | Computer operating method and computer system |
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JP (1) | JPH04131960A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2002031769A1 (en) * | 2000-10-10 | 2002-04-18 | Sony Computer Entertainment Inc. | Data processing system and method, computer program, and recorded medium |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62132456A (en) * | 1985-12-04 | 1987-06-15 | Iwatsu Electric Co Ltd | Data transmission equipment |
-
1990
- 1990-09-25 JP JP2251868A patent/JPH04131960A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62132456A (en) * | 1985-12-04 | 1987-06-15 | Iwatsu Electric Co Ltd | Data transmission equipment |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2002031769A1 (en) * | 2000-10-10 | 2002-04-18 | Sony Computer Entertainment Inc. | Data processing system and method, computer program, and recorded medium |
US7212211B2 (en) | 2000-10-10 | 2007-05-01 | Sony Computer Entertainment Inc. | Data processing system and method, computer program, and recording medium |
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