JPH04130630A - Oxide film for integrated circuit device and its formation method - Google Patents
Oxide film for integrated circuit device and its formation methodInfo
- Publication number
- JPH04130630A JPH04130630A JP25095490A JP25095490A JPH04130630A JP H04130630 A JPH04130630 A JP H04130630A JP 25095490 A JP25095490 A JP 25095490A JP 25095490 A JP25095490 A JP 25095490A JP H04130630 A JPH04130630 A JP H04130630A
- Authority
- JP
- Japan
- Prior art keywords
- film
- oxide film
- oxidation
- resistant
- oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 14
- 230000015572 biosynthetic process Effects 0.000 title 1
- 230000003647 oxidation Effects 0.000 claims abstract description 62
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 61
- 239000004065 semiconductor Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 230000001590 oxidative effect Effects 0.000 claims description 5
- 230000007547 defect Effects 0.000 abstract description 10
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 6
- 238000002955 isolation Methods 0.000 description 5
- 239000010410 layer Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 239000007795 chemical reaction product Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 101001134134 Homo sapiens Oxidation resistance protein 1 Proteins 0.000 description 1
- 102100034219 Oxidation resistance protein 1 Human genes 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、集積回路装置内の回路素子の相互間を表面側
から分離する素子骨ｌＩ！１膜等に用いられる酸化膜、
正確にはシリコンの半導体基体の表面の所定範囲を覆い
下側のシリコンの酸化により形成される酸化膜およびそ
の形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention provides an element structure for separating circuit elements in an integrated circuit device from each other from the surface side. Oxide film used for 1 film etc.
More precisely, the present invention relates to an oxide film that covers a predetermined area of the surface of a silicon semiconductor substrate and is formed by oxidizing the underlying silicon, and a method for forming the same.
［従来の技術〕
周知のように、半導体装置内で酸化シリコン膜は種々な
機能を果たすが、シリコンの半導体基体の表面を直接覆
う酸化シリコン膜はふつうはシリコンを高温酸化して得
られる酸化膜で、いわゆるプロセス酸化膜、ゲート酸化
膜、フィールド酸化膜等として用いられる。また集積回
路装置では、そのトランジスタ等の回路素子の相互間を
表面側から分離するだめの素子分離膜としても酸化膜が
用いられる。よく知られていることであるが、第３図を
参照して酸化膜を素子分離膜に用いた例を簡単に説明す
る。[Prior Art] As is well known, silicon oxide films perform various functions in semiconductor devices, but the silicon oxide film that directly covers the surface of a silicon semiconductor substrate is usually an oxide film obtained by high-temperature oxidation of silicon. It is used as a so-called process oxide film, gate oxide film, field oxide film, etc. In integrated circuit devices, an oxide film is also used as an element isolation film for separating circuit elements such as transistors from each other from the surface side. As is well known, an example in which an oxide film is used as an element isolation film will be briefly described with reference to FIG.
第３図の回路素子ばｎチャネル形のＦＥＴで、図示しな
い基板の上にエピタキシャル層１１を成長させたウェハ
やチップである半導体基体１０に組み込まれる。この組
み込みに先立ち、半導体基体ｌＯの表面にＦＥＴの範囲
を取り囲むように酸化１１！３０を付け、その開口内に
ウェル１２とゲート酸化膜１３とゲー［４と接Ｍｊｉｔ
ｓとＩ対のソース・ドレイン層１６を備えるＦＥＴを作
り込んで層間絶縁膜１７で覆った後に、その上に配設し
た配線膜１８を介して他の回路素子と接続する。The circuit element shown in FIG. 3 is an n-channel type FET and is incorporated into a semiconductor substrate 10, which is a wafer or chip, on which an epitaxial layer 11 is grown on a substrate (not shown). Prior to this incorporation, an oxide film 11!30 is applied to the surface of the semiconductor substrate IO so as to surround the area of the FET, and a well 12, a gate oxide film 13, a gate oxide film 13, a gate oxide film 13, and a contact Mjit
After fabricating an FET with an S and I pair of source/drain layers 16 and covering it with an interlayer insulating film 17, it is connected to other circuit elements via a wiring film 18 disposed thereon.
このように、素子分１１１１１Ｑとしての酸化＠３０は
各凹路素子を紐み込む範囲を画成する役目を果たすが、
その上に配線膜１８が配設されるので、それを絶縁しか
つ半導体基体１０に対するその電位の影響を遮断するい
わゆるフィールド酸化膜の役目をも兼ねる。このため、
かかる酸化膜３０には回路電圧にもよるがふつう１−程
度の膜厚を持たせ、いわゆるＬＯＣＯ５法によって窒化
シリコン膜等をマスクとして半導体基体１０のシリコン
の表面を高温酸化してこれを成膜するのが通例である。In this way, the oxidation@30 as the element part 11111Q serves to define the range in which each concave path element is tied,
Since the wiring film 18 is disposed on the wiring film 18, it also serves as a so-called field oxide film that insulates the wiring film and blocks the influence of the potential on the semiconductor substrate 10. For this reason,
The oxide film 30 is usually made to have a thickness of about 1-100 nm, depending on the circuit voltage, and is formed by oxidizing the silicon surface of the semiconductor substrate 10 at high temperature using a silicon nitride film or the like as a mask using the so-called LOCO5 method. It is customary to do so.
上のような素子分離膜等に用いる酸化膜の膜厚は通常よ
りも厚めにされるが、最近では集積回路装置の用途拡大
に伴いその使用回路電圧を１００ Ｖ以上にも上げる必
要が生し、これに応して酸化膜の膜厚を１−以上に増し
て行くと、以下のような間Ｈ点が出て来た。The film thickness of the oxide film used for the element isolation film etc. above is made thicker than usual, but recently, with the expansion of applications for integrated circuit devices, it has become necessary to increase the circuit voltage used to 100 V or more. In response to this, when the thickness of the oxide film was increased to 1- or more, the following point H appeared.
第１の問題点は酸化膜の周縁にホワイトリボンと呼ばれ
る欠陥が出やすくなることであり、これを第４図に示す
０図はエピタキシャル層１１の表面に上述のＬＯＣＯ３
法により成膜した酸化膜３０の周縁の拡大断面図である
８図のように窒化シリコン等の耐酸化性１１２０をマス
クとしてシリコンの表面を高温酸化すると、酸化８３０
がシリコン表面に食い込みかつＩ′！１縁が耐酸化性膜
２０の下に潜り込むように成長する。この酸化膜３０の
周縁には図示のように喫状の（頃斜面が形成されるが、
１１Ｍ以上の膜厚にこれを成長させると模の先端部に図
の前後方向に延びる白っぽいホワイトリボン−Ｒが非常
に発生しやすくなって来る。The first problem is that a defect called a white ribbon tends to appear on the periphery of the oxide film, and this is shown in Figure 4, where the above-mentioned LOCO3 is formed on the surface of the epitaxial layer 11.
As shown in FIG. 8, which is an enlarged cross-sectional view of the periphery of the oxide film 30 formed by the method, when the surface of silicon is oxidized at high temperature using an oxidation-resistant material such as silicon nitride as a mask, oxidation 830
bites into the silicon surface and I'! It grows so that one edge goes under the oxidation-resistant film 20. At the periphery of this oxide film 30, a slanted slope is formed as shown in the figure.
When this film is grown to a thickness of 11M or more, a whitish white ribbon -R extending in the front-rear direction of the figure becomes very likely to occur at the tip of the pattern.
この示ワイドリボン■は、酸化ｆｆ１３０の酸化シリコ
ンと耐酸化性膜２ｏとの反応生成物、とくにその窒化シ
リコン中の窒素との反応生成物であって、酸化シリコン
とは著しく性状が異なっていて回路素子の耐圧低下を招
きゃす（、その上の絶縁膜等のＭ！覆が不完全になりゃ
すく、がっ除去が非常に困難な問題がある。This wide ribbon (■) is a reaction product between the silicon oxide of the oxide FF130 and the oxidation-resistant film 2o, especially the reaction product with nitrogen in the silicon nitride, and its properties are significantly different from that of silicon oxide. This may lead to a decrease in the withstand voltage of the circuit elements (and the M! covering of the insulating film, etc. thereon may become incomplete, making it extremely difficult to remove it).
第２の問題点は、酸化膜の膜厚を増すとそれによる段差
も大きくなり、その上の絶縁膜や配線膜に欠陥が発生し
ゃすいことにある。第５図にこの様子を示す、酸化膜３
ｏの周縁は斜面ではあるが、酸化膜３０の膜厚が１−を
越えると段差Ｓが０．５−以上になるので、それを覆う
層間絶縁膜１７に応力が掛かってクラックＣＩが発生し
ゃすくなり、その上の配線膜１８に断線Ｂが誘発されや
すい、また、配線１１２１Ｂ内にも応力が発生してクラ
ンクｃ２が発生しやすくなる。The second problem is that as the thickness of the oxide film increases, the resulting step difference also increases, making it more likely that defects will occur in the overlying insulating film and wiring film. This situation is shown in Figure 5, where the oxide film 3
Although the periphery of the oxide film 30 is sloped, if the thickness of the oxide film 30 exceeds 1-, the step S becomes 0.5- or more, so stress is applied to the interlayer insulating film 17 covering it, which prevents crack CI from occurring. This tends to cause disconnection B in the wiring film 18 thereon, and stress is also generated in the wiring 1121B, making it easy to generate crank c2.
本発明の目的は、酸化膜の周縁部上のホワイトリボン欠
陥の発生および段差上の絶縁膜や配線膜中の欠陥の発生
を防止することにある。An object of the present invention is to prevent the occurrence of white ribbon defects on the periphery of an oxide film and the occurrence of defects in an insulating film or wiring film on a step.
ＣｎＢを解決するための手段〕
本発明は酸化膜の周縁を段付き傾斜面に形成してその各
段の最大段差を０．５−以下にすることにより上述の目
的を達成するもので、酸化膜のこの段付き傾斜面は、耐
酸化性膜をマスクとしてシリコンの表面を酸化して酸化
膜を形成する際、１回の酸化で形成する酸化膜の膜厚限
度を１−とし、膜厚がこれを越えるごとに耐酸化性膜を
被覆範囲を順次広げながら付け直した上で、酸化を重ね
て酸化膜を積み増すことにより形成される。Means for Solving CnB] The present invention achieves the above object by forming the periphery of the oxide film into a stepped inclined surface and making the maximum step difference of each step 0.5- or less. This stepped inclined surface of the film is created by using the oxidation-resistant film as a mask to oxidize the surface of silicon to form an oxide film. It is formed by reapplying the oxidation-resistant film while sequentially expanding the coverage area each time it exceeds this range, and then repeating oxidation to increase the number of oxide films.
なお、上記の段付き傾斜面は各段ごとに傾斜面を横方向
に段差以上ずらせた形状に形成するのが望ましい。また
、耐酸化性膜には窒化シリコン膜が好適で、これを薄い
酸化シリコンのバッファ股上に被着してマスクとするの
がよい。Note that it is preferable that the stepped sloped surface is formed in such a shape that the sloped surface is shifted in the lateral direction by more than a step difference for each step. Further, a silicon nitride film is suitable as the oxidation-resistant film, and it is preferable to apply this film to the top of a thin silicon oxide buffer and use it as a mask.
本発明は、膜厚が大な酸化膜を複数回に分けて形成する
ことにより酸化膜周縁のホワイトリボンの発生を防止し
ながら、段差を複数段に分割して絶縁膜や配線膜の欠陥
を防止するものである。The present invention prevents the generation of white ribbons around the oxide film by forming a thick oxide film in multiple steps, and at the same time prevents defects in the insulating film and wiring film by dividing the step into multiple steps. It is intended to prevent
このため、前項の構成にいうように１回の酸化により形
成する酸化膜の膜厚の限度を１４．段差の限度にして０
．５１Ｍとし、この限度を越えるごとに酸化工程を分け
て酸化膜を積み増すようにし、かつそれを利用して酸化
膜の周縁を段付き傾斜面に形成する。すなわち、酸化膜
を積み増すごとに酸化用マスクとしての耐酸化性膜をそ
の被覆範囲を順次広げながら付け直すことにより、酸化
膜の周縁を段付き傾斜面に形成する。For this reason, as mentioned in the configuration in the previous section, the limit of the thickness of the oxide film formed by one oxidation is set to 14. 0 as the limit of the step
．． 51M, and each time this limit is exceeded, the oxidation process is divided to increase the oxide film, and this is used to form the periphery of the oxide film into a stepped slope. That is, each time an oxide film is accumulated, an oxidation-resistant film serving as an oxidation mask is reattached while sequentially expanding its coverage area, thereby forming the periphery of the oxide film into a stepped slope.
以下、図を参照しながら本発明の詳細な説明する。第１
図に周縁が段付き傾斜面に形成された本発明の集積回路
装置用酸化８３０を半導体基板１０上に付けた状態を示
し、第２図にこの状態にするまでの主な工程ごとの状態
を示す、いずれも前に説明した第３図に対応して半導体
基体１０内に回路素子を作り込む範囲を取り囲んで酸化
膜３０を付ける部分の拡大断面である。説明の便宜上、
以下の実施例の説明を第２図の方から主な工程を追って
順次に進めることとする。Hereinafter, the present invention will be described in detail with reference to the drawings. 1st
The figure shows the state in which the oxide 830 for integrated circuit devices of the present invention, which has a stepped sloped peripheral edge, is applied on the semiconductor substrate 10, and FIG. 2 shows the state of each main process to achieve this state. These are enlarged cross-sectional views of the portion where the oxide film 30 is attached surrounding the area where circuit elements are to be formed in the semiconductor substrate 10, corresponding to FIG. 3 described above. For convenience of explanation,
The following description of the embodiment will proceed sequentially, following the main steps starting from FIG.
この実施例では２回の酸化工程により約１．４−の膜厚
の酸化Ｍ３０を形成するものとし、第２図（ａ）は１回
目の酸化工程用のマスクを形成した状態を示す、まず、
例えば第３図のエピタキシャル層１１である半導体基板
ＩＯの表面を９００°Ｃ程度の温度下で短時間酸化する
ことにより、０．０４−程度の薄い酸化シリコン膜を形
成してバッファ膜２１とする。In this example, oxidation M30 with a film thickness of approximately 1.4 mm is formed by two oxidation steps, and FIG. 2(a) shows the state in which a mask for the first oxidation step has been formed. ,
For example, by oxidizing the surface of the semiconductor substrate IO, which is the epitaxial layer 11 in FIG. .
次に、その上に耐酸化性膜２２用に例えば窒化シリコン
を減圧ＣＶＤ法等により０．１５−の膜厚に成長させ、
フォトプロセスとドライエツチングにより回路素子を作
り込むべき範囲を覆う図のパターンに形成して酸化用マ
スクとする。Next, silicon nitride, for example, is grown on it to a thickness of 0.15 for the oxidation-resistant film 22 by low-pressure CVD or the like.
By photoprocessing and dry etching, the pattern shown in the figure is formed to cover the area where circuit elements are to be fabricated, and is used as an oxidation mask.
第２図（ｂ）は１回目の酸化工程の終了時の状態を示す
、この酸化は１０００°Ｃ程度の高温下で行ない、この
例では酸化膜３０の１回目の酸化による膜厚【ｌをホワ
イトリボンの発生を完全に防止できるよう薄い目の０．
６−程度とする。酸化ｌｌ！３０はもちろん耐酸化性膜
２０で覆われていない範囲に成長され、その周縁の傾斜
面３１を耐酸化性膜２０の周縁の下に潜り込ませるよう
にして形成される。FIG. 2(b) shows the state at the end of the first oxidation process. This oxidation is performed at a high temperature of about 1000°C, and in this example, the film thickness of the oxide film 30 due to the first oxidation [l] Thin 0.0mm to completely prevent the occurrence of white ribbons.
It should be about 6-. Oxidation! 30 is of course grown in an area not covered by the oxidation-resistant film 20, and is formed so that the inclined surface 31 at its peripheral edge is submerged under the peripheral edge of the oxidation-resistant film 20.
第２図（Ｃ）は２回−目の酸化工程用のマスクを形成し
た状態を示す、もちろん、この状態にする前に同図（ロ
）の状態からまず耐酸化性１！１２１を取り除く。FIG. 2(C) shows a state in which a mask for the second oxidation process has been formed.Of course, before changing to this state, the oxidation resistance 1!121 is first removed from the state in FIG. 2(B).
また、バッファ１１！Ｉ２１は酸化膜３０内に取り込ま
れた状態になっているが、それに相当する部分もごく短
時間のウェットエツチングにより除去するのが望ましい
、以後、第１図（ａ）で述べたと同じ要領でバッファ膜
２３と耐酸化性膜２４を付け、かつ後者をフォトエツチ
ングして図示の状態とするが、この２回目の酸化用の耐
酸化性Ｗｉ２４を被覆範囲が必ず１回目よりも広がるよ
うにパターンニングする。Also, buffer 11! Although I21 is now incorporated into the oxide film 30, it is desirable to remove the corresponding portion by wet etching for a very short period of time. A film 23 and an oxidation-resistant film 24 are attached, and the latter is photo-etched to obtain the state shown in the figure.The oxidation-resistant Wi 24 for the second oxidation is patterned so that the covered area is always wider than the first oxidation. do.
例えば、この実施例では被覆範囲が片側で１，５−程度
ずつ広げられる。For example, in this embodiment, the coverage area is increased by about 1.5-degrees on each side.
第２図（ｄ）は２回目の酸化工程の終了時の状態を示す
、耐酸化性膜２４をマスクとする酸化は同図（ｂｌの１
回目と同じ要領でよく、この例では酸化Ｉ！３０をｌ１
９［ｔ２＝０．８−分だけ積み増して、全体の膜厚をｔ
ｌ ＋ Ｌ２＝ １．４−とする。この２回目の酸化工
程により、酸化膜３０の周縁の耐酸化性膜２４の下側に
２段目の傾斜面３２が形成される。FIG. 2(d) shows the state at the end of the second oxidation step. Oxidation using the oxidation-resistant film 24 as a mask is shown in FIG.
You can follow the same procedure as the previous time, but in this example, oxidation I! 30 to l1
9 [t2 = 0.8-minute increase to make the total film thickness t
Let l + L2 = 1.4-. Through this second oxidation step, a second sloped surface 32 is formed on the lower side of the oxidation-resistant film 24 at the periphery of the oxide film 30.
以陵は第２図（ハ）の状態から耐酸化性Ｈ２４を取り除
き、かつ望ましくは酸化膜３０の表面から同図（Ｃ）の
バッファ膜２３に相当する部分を取り除くことにより第
１図の状態とする。The state shown in FIG. 1 is then obtained by removing the oxidation resistance H24 from the state shown in FIG. shall be.
以上のように形成された酸化膜３０は、第１図に示すよ
うにその周縁が２個の傾斜面３１と３２をもつ段付き傾
斜面３３に形成され、その２段の段差ｓｌと３２は上述
の１回目と２回目の酸化工程による膜厚ｔｌとｔ２のそ
れぞれ約半分のこの実施例では０．３゜と０．４１！ｍ
程度になる。また、２個の傾斜面３１と３２の相互間の
ずれｓｈは前述の１．５，１ｍとなる。かがる傾斜面間
のずれｓｈは、段差ｓｌやｓ２と同程度以上とする必要
があるが、この実施例のように２倍以上とするのが望ま
しい。As shown in FIG. 1, the oxide film 30 formed as described above is formed into a stepped inclined surface 33 having two inclined surfaces 31 and 32 at its periphery, and the two steps sl and 32 are In this example, the film thicknesses tl and t2 from the first and second oxidation steps described above are about half, respectively, 0.3° and 0.41! m
It will be about. Further, the deviation sh between the two inclined surfaces 31 and 32 is the aforementioned 1.5.1 m. The deviation sh between the sloped surfaces needs to be equal to or more than the steps sl and s2, but it is desirable to make it twice or more as in this embodiment.
なお、集積回路装置の回路電圧が２００ Ｖ程度までの
場合は酸化ＩＩ！３０を第１図のような２段構成とする
ことで充分であるが、回路電圧が数百Ｖ程度にまで高く
なって酸化膜３０の全体膜厚・を２−近くないしそれ以
上に増加させる必要がある場合は、３段以上の構成が採
用される。In addition, if the circuit voltage of the integrated circuit device is up to about 200 V, oxidation II! It is sufficient to have the oxide film 30 in a two-stage configuration as shown in FIG. 1, but the circuit voltage increases to several hundreds of volts, increasing the overall thickness of the oxide film 30 to nearly 2- or more. If necessary, a configuration with three or more stages is adopted.
本発明による酸化膜の試作実験結果によれば、第１図の
ように酸化工程を２回に分けて成長させた酸化Ｉｔ！３
０には第４図のようなホワイトリボンの発生は見られず
、半導体基体ｌＯの酸化膜３０で取り囲まれた範囲内に
第３図と同じ要領で回路素子を作り込むことができる。According to the experimental results of the oxide film according to the present invention, it was found that the oxide It! was grown in two oxidation steps as shown in FIG. 3
0, no white ribbon as shown in FIG. 4 is observed, and circuit elements can be fabricated in the same manner as in FIG. 3 within the area surrounded by the oxide film 30 of the semiconductor substrate IO.
この要領でＦＥＴを作り込んだ試作結果では、酸化Ｈ３
０の周縁上に配設した層間絶縁１１１７や配線１１１８
に第５図のような欠陥が発生する確率が従来より約１桁
減少し、第１図の段付き傾斜面３３の効果がｆ１認され
た。The prototype results of fabricating an FET in this manner show that oxidized H3
Interlayer insulation 1117 and wiring 1118 arranged on the periphery of 0
The probability of occurrence of a defect as shown in FIG. 5 was reduced by about one order of magnitude compared to the conventional method, and the effect of the stepped inclined surface 33 shown in FIG. 1 was recognized as f1.
以上述べたとおり本発明では、集積回路装置用酸化膜の
周縁を段付き傾斜面に形成してその各段の段差を０．５
ｐ以下にし、この酸化膜を耐酸化性膜をマスクとしてシ
リコン表面を酸化して酸化膜を形成する際に、１回の酸
化で形成する酸化膜の膜厚限度を１−とじ、膜厚がそれ
を越えるごとに耐酸化性膜をその被覆範囲を順次広げな
がら付け直した上で、酸化を重ねて酸化膜を積み増すこ
とにより、以下の効果が得られる。As described above, in the present invention, the peripheral edge of the oxide film for an integrated circuit device is formed into a stepped inclined surface, and the step difference between each step is 0.5.
p or less, and when forming an oxide film by oxidizing the silicon surface using the oxidation-resistant film as a mask, the film thickness limit of the oxide film formed in one oxidation is set as 1-, and the film thickness is The following effects can be obtained by reapplying the oxidation-resistant film while sequentially expanding its coverage each time the range is exceeded, and then increasing the number of oxide films by repeating oxidation.
（ａ）膜厚が大な酸化膜を複数回の工程に分けて酸化を
重ねつつ順次積み増して形成することにより、１回の酸
化工程で形成する膜厚限度を１−に制限して酸化膜の周
縁におけるホワイトリボンの発生を皆無にすることがで
きる。(a) By dividing a thick oxide film into multiple steps and stacking the oxide layer sequentially, the oxide film can be formed by limiting the film thickness that can be formed in one oxidation step to 1-. It is possible to completely eliminate the occurrence of white ribbons at the periphery of the paper.
（ｂ）＊数回の酸化工程ごとにマスク用の耐酸化性膜を
被覆範囲を順次広げつつ付け直すことにより、酸化膜の
周縁を段（−ｊき傾斜面に形成して各段差を０．５−以
下に制限するので、その上に配設される絶＆！膜や配線
膜内の応力を緩和して、被覆不足や断線欠陥の発生を有
効に防止できる。(b) *By reapplying the oxidation-resistant film for the mask every several oxidation steps while gradually expanding the coverage area, the periphery of the oxide film is formed into a step (-j) slope, and each step is reduced to 0. Since it is limited to .5- or less, it is possible to relieve the stress in the insulation &! film and wiring film disposed thereon, and effectively prevent the occurrence of insufficient coverage and disconnection defects.
（Ｃ）集積回路装置内の場所に応じて、酸化膜形成のた
めの酸化工程の回数を選択してその膜厚の切り換え設定
ができるので、集積回路装置内に複数個の電圧下で動作
する回路素子や回路部分を非常に合理的に作り込むこと
ができる。(C) The number of oxidation steps to form an oxide film can be selected and the film thickness can be switched depending on the location within the integrated circuit device, so the integrated circuit device can operate under multiple voltages. Circuit elements and circuit parts can be built very rationally.
かかる特長を俯える本発明による酸化膜は集積回路装置
内の素子分離膜やフィールド酸化膜への適用にとくに有
利であり、欠陥の発生を防止して耐圧や性能を向上さ廿
ることができる。The oxide film according to the present invention, which has such features, is particularly advantageous in application to element isolation films and field oxide films in integrated circuit devices, and can prevent the occurrence of defects and improve breakdown voltage and performance. .
第１図および第２図が本発明に関し、第１図は半導体基
体上に形成した本発明の集積回路装置用酸化膜の実施例
を示す断面図、第２図（ａｌ〜（ｄ）はこの第１図に対
応する本発明の集積回路装置酸化膜の形成方法の実施例
を主な工程ごとの状態で示す半導体基体の断面図である
。第３図以降は従来の技術に関し、第３図は従来の酸化
膜を素子分離膜に用いたＦＥＴの断面図、第４図および
第５図は従来技術の問題点を示すための第３図に対応す
るそれぞれ要部の拡大断面図である。これらの図におい
て、
１０：半導体基体、２０．２２，２４ ：耐酸化性膜な
いし窒化シリコン膜、２１，２３ ：耐酸化性膜の下地
用のバッファ膜、３０：酸化膜、３１．３２Ｆ酸化膜の
周縁の傾斜面、３３：段付き傾斜面、ｓｌ、ｓ２：各傾
斜面の段差、ｓｈ：傾斜面相互間のずれ、ｔｌ：１回目
の酸化による酸化膜の膜厚、ｔ２：２回目の酸化にょ′
；ｆ７ｚ図1 and 2 relate to the present invention, FIG. 1 is a cross-sectional view showing an embodiment of an oxide film for an integrated circuit device of the present invention formed on a semiconductor substrate, and FIGS. 3 is a cross-sectional view of a semiconductor substrate showing the state of each main step in an embodiment of the method for forming an oxide film in an integrated circuit device of the present invention corresponding to FIG. 1. FIG. 1 is a cross-sectional view of a conventional FET using an oxide film as an isolation film, and FIGS. 4 and 5 are enlarged cross-sectional views of essential parts corresponding to FIG. 3 for illustrating problems of the prior art. In these figures, 10: semiconductor substrate, 20. 22, 24: oxidation-resistant film or silicon nitride film, 21, 23: buffer film for base of oxidation-resistant film, 30: oxide film, 31. 32F oxide film. 33: Stepped slope, sl, s2: Step difference between each slope, sh: Displacement between slopes, tl: Thickness of oxide film due to first oxidation, t2: Second oxidation Oxidation
;f7z diagram
Claims (1)
のシリコンの酸化により形成される酸化膜であって、周
縁が段付き傾斜面に形成され、各段の最大段差が０．５
μｍ以下にされたことを特徴とする集積回路装置用酸化
膜。 ２）請求項１に記載の酸化膜において、各段ごとに傾斜
面が横方向に段差以上ずらされたことを特徴とする集積
回路装置用酸化膜。 ３）耐酸化性膜をマスクとしてシリコンの半導体基体の
表面を酸化してその所定範囲を覆い周縁に耐酸化性膜下
に潜り込む傾斜面をもつ酸化膜を形成する方法であって
、１回の酸化で形成する酸化膜の膜厚限度を１μｍとし
て膜厚がこれを越えるごとに耐酸化性膜を被覆範囲を順
次広げながら付け直した上で酸化を重ねて酸化膜を積み
増し、酸化膜の周縁を段付き傾斜面に形成することを特
徴とする集積回路装置用酸化膜の形成方法。[Scope of Claims] 1) An oxide film that covers a predetermined area of the surface of a silicon semiconductor substrate and is formed by oxidizing the underlying silicon, the periphery of which is formed into a stepped slope, and the maximum step difference between each step. is 0.5
An oxide film for an integrated circuit device, characterized in that the oxide film has a thickness of μm or less. 2) An oxide film for an integrated circuit device according to claim 1, wherein the slanted surface of each step is shifted laterally by more than a step. 3) A method in which the surface of a silicon semiconductor substrate is oxidized using an oxidation-resistant film as a mask to form an oxide film having a sloped surface that covers a predetermined area and goes under the oxidation-resistant film at the periphery. The thickness limit of the oxide film formed by oxidation is set at 1 μm, and each time the film thickness exceeds this, the oxidation-resistant film is reapplied while sequentially expanding the coverage area, and then oxidation is repeated to increase the oxide film and remove the periphery of the oxide film. 1. A method for forming an oxide film for an integrated circuit device, the method comprising forming an oxide film on a stepped inclined surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25095490A JPH04130630A (en) | 1990-09-20 | 1990-09-20 | Oxide film for integrated circuit device and its formation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25095490A JPH04130630A (en) | 1990-09-20 | 1990-09-20 | Oxide film for integrated circuit device and its formation method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04130630A true JPH04130630A (en) | 1992-05-01 |
Family
ID=17215482
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25095490A Pending JPH04130630A (en) | 1990-09-20 | 1990-09-20 | Oxide film for integrated circuit device and its formation method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04130630A (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5468675A (en) * | 1993-05-26 | 1995-11-21 | Rohm Co., Ltd. | Method for manufacturing a device separation region for semiconductor device |
| US5700733A (en) * | 1995-06-27 | 1997-12-23 | Micron Technology, Inc. | Semiconductor processing methods of forming field oxide regions on a semiconductor substrate |
| US5714414A (en) * | 1996-08-19 | 1998-02-03 | Micron Technology, Inc. | Semiconductor processing method of forming field isolation oxide relative to a semiconductor substrate |
| US5789306A (en) * | 1996-04-18 | 1998-08-04 | Micron Technology, Inc. | Dual-masked field isolation |
| US6387777B1 (en) | 1998-09-02 | 2002-05-14 | Kelly T. Hurley | Variable temperature LOCOS process |
| US7229895B2 (en) | 2005-01-14 | 2007-06-12 | Micron Technology, Inc | Memory array buried digit line |
| US7247570B2 (en) | 2004-08-19 | 2007-07-24 | Micron Technology, Inc. | Silicon pillars for vertical transistors |
| US7285812B2 (en) | 2004-09-02 | 2007-10-23 | Micron Technology, Inc. | Vertical transistors |
| US7368344B2 (en) | 2004-12-13 | 2008-05-06 | Micron Technology, Inc. | Methods of reducing floating body effect |
| US7371627B1 (en) | 2005-05-13 | 2008-05-13 | Micron Technology, Inc. | Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines |
| US10515801B2 (en) | 2007-06-04 | 2019-12-24 | Micron Technology, Inc. | Pitch multiplication using self-assembling materials |
-
1990
- 1990-09-20 JP JP25095490A patent/JPH04130630A/en active Pending
Cited By (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5468675A (en) * | 1993-05-26 | 1995-11-21 | Rohm Co., Ltd. | Method for manufacturing a device separation region for semiconductor device |
| US5700733A (en) * | 1995-06-27 | 1997-12-23 | Micron Technology, Inc. | Semiconductor processing methods of forming field oxide regions on a semiconductor substrate |
| US5909629A (en) * | 1995-06-27 | 1999-06-01 | Micron Technology, Inc. | Semiconductor processing method of forming field oxide regions on a semiconductor substrate |
| US6103020A (en) * | 1996-04-18 | 2000-08-15 | Micron Technology, Inc. | Dual-masked field isolation |
| US5789306A (en) * | 1996-04-18 | 1998-08-04 | Micron Technology, Inc. | Dual-masked field isolation |
| US5909630A (en) * | 1996-04-18 | 1999-06-01 | Micron Technology, Inc. | Dual-masked isolation |
| US5989980A (en) * | 1996-08-19 | 1999-11-23 | Micron Technology, Inc. | Semiconductor processing method of forming field isolation oxide relative to a semiconductor substrate |
| US5714414A (en) * | 1996-08-19 | 1998-02-03 | Micron Technology, Inc. | Semiconductor processing method of forming field isolation oxide relative to a semiconductor substrate |
| US6387777B1 (en) | 1998-09-02 | 2002-05-14 | Kelly T. Hurley | Variable temperature LOCOS process |
| US7413480B2 (en) | 2004-08-19 | 2008-08-19 | Micron Technology, Inc. | Silicon pillars for vertical transistors |
| US8847298B2 (en) | 2004-08-19 | 2014-09-30 | Micron Technology, Inc. | Pillars for vertical transistors |
| US7247570B2 (en) | 2004-08-19 | 2007-07-24 | Micron Technology, Inc. | Silicon pillars for vertical transistors |
| US8629533B2 (en) | 2004-08-19 | 2014-01-14 | Micron Technology, Inc. | Pillars for vertical transistors |
| US7285812B2 (en) | 2004-09-02 | 2007-10-23 | Micron Technology, Inc. | Vertical transistors |
| US7521322B2 (en) | 2004-09-02 | 2009-04-21 | Micron Technology, Inc. | Vertical transistors |
| US7368344B2 (en) | 2004-12-13 | 2008-05-06 | Micron Technology, Inc. | Methods of reducing floating body effect |
| US7626223B2 (en) | 2004-12-13 | 2009-12-01 | Micron Technology, Inc. | Memory structure for reduced floating body effect |
| US7601608B2 (en) | 2005-01-14 | 2009-10-13 | Micron Technologies, Inc. | Memory array buried digit line |
| US7768073B2 (en) | 2005-01-14 | 2010-08-03 | Micron Technology, Inc. | Memory array buried digit line |
| US8102008B2 (en) | 2005-01-14 | 2012-01-24 | Micron Technology, Inc. | Integrated circuit with buried digit line |
| US7368365B2 (en) | 2005-01-14 | 2008-05-06 | Wells David H | Memory array buried digit line |
| US7229895B2 (en) | 2005-01-14 | 2007-06-12 | Micron Technology, Inc | Memory array buried digit line |
| US7371627B1 (en) | 2005-05-13 | 2008-05-13 | Micron Technology, Inc. | Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines |
| US10515801B2 (en) | 2007-06-04 | 2019-12-24 | Micron Technology, Inc. | Pitch multiplication using self-assembling materials |
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