JPH04124854A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH04124854A JPH04124854A JP24392590A JP24392590A JPH04124854A JP H04124854 A JPH04124854 A JP H04124854A JP 24392590 A JP24392590 A JP 24392590A JP 24392590 A JP24392590 A JP 24392590A JP H04124854 A JPH04124854 A JP H04124854A
- Authority
- JP
- Japan
- Prior art keywords
- active layer
- layer
- depth
- ion
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 229910052796 boron Inorganic materials 0.000 claims abstract description 9
- -1 boron ions Chemical class 0.000 claims description 7
- 150000002500 ions Chemical class 0.000 abstract description 14
- 230000005684 electric field Effects 0.000 abstract description 10
- 230000001133 acceleration Effects 0.000 abstract description 7
- 238000000137 annealing Methods 0.000 abstract description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract 2
- 238000005468 ion implantation Methods 0.000 description 18
- 238000002955 isolation Methods 0.000 description 7
- 230000007423 decrease Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000011156 evaluation Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
Landscapes
- Element Separation (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野]
この発明は、半導体装置の製造方法に関し、特にGaA
sを用いた半導体基板上に素子間等分離用の高抵抗層を
形成する方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device.
The present invention relates to a method of forming a high resistance layer for equal isolation between elements on a semiconductor substrate using S.
[従来の技術]
GaAsを用いた半導体基板上に複数個の素子等を構成
する場合、素子間又は素子内の電気的な分離構造が必要
とされる。特に、半絶縁性のGaAs基板上の全面に、
活性層をエピタキシャル成長法で形成した場合、その分
離構造としては、例えば、次の■又は■の構造かとられ
ている。[Prior Art] When configuring a plurality of elements on a semiconductor substrate using GaAs, an electrical isolation structure is required between the elements or within the element. In particular, on the entire surface of a semi-insulating GaAs substrate,
When the active layer is formed by epitaxial growth, the isolation structure is, for example, the following structure (1) or (2).
■活性層をメサエッチングしてメサ構造により電気的に
分離する。■Mesa-etch the active layer to electrically isolate it using a mesa structure.
■イオン注入により、活性層の所望領域に高抵抗層を形
成する。(2) Form a high resistance layer in a desired region of the active layer by ion implantation.
上記■及び■の両分鍵構造を比べると、■の構造の方が
表面が平坦でブレーナ構造となるので、一般に、高集積
化及び複雑な構造に有利と考えられている。Comparing the above-mentioned two key structures (1) and (2), the structure (2) has a flat surface and a Brainer structure, so it is generally considered to be advantageous for high integration and complex structures.
従来、この■の分離構造を実現するための高抵抗層の形
成方法としては、活性層表面から、その活性層の深さの
2倍位の深さに、活性層のキャリア濃度の1/10程度
のドース量(注入量)のH′″ B+ 01等のイオン
をイオン注入することが行われている(浅井、大畑、信
学技報 ED89−91.p25)。Conventionally, the method for forming a high-resistance layer to realize the isolation structure (2) was to deposit a layer of 1/10 of the carrier concentration of the active layer from the surface of the active layer to a depth approximately twice the depth of the active layer. Ion implantation of ions such as H''' B+ 01 at a dose (implantation amount) of about 100 to 100 m is being carried out (Asai, Ohata, IEICE Technical Report ED89-91.p25).
[発明か解決しようとする課題]
上記■の分離構造を実現するための従来方法で形成され
た高抵抗層は、低い電界強度では高い抵抗率を示すが、
高い電界強度では抵抗率か低下してしまう。このため、
高集積化等により電極間(素子間)距離を短かくし、又
は高出力化等により印加電圧を高くすることができず、
素子間又は素子内の電気的分離用として不十分であると
いう問題があった。[Problem to be solved by the invention] The high-resistance layer formed by the conventional method to realize the isolation structure in (2) above exhibits high resistivity at low electric field strength;
At high electric field strengths, the resistivity decreases. For this reason,
It is not possible to shorten the distance between electrodes (between elements) due to high integration, or increase the applied voltage due to high output, etc.
There was a problem that it was insufficient for electrical isolation between elements or within an element.
そこで、この発明は、高い電界を印加しても十分に素子
間等の分離が可能な高抵抗層を基板上に得ることができ
る半導体装置の製造方法を提供することを目的とする。SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for manufacturing a semiconductor device that can provide a high resistance layer on a substrate that can sufficiently isolate elements even when a high electric field is applied.
[課題を解決するための手段]
この発明は上記課題を解決するために、(a)実質的に
絶縁性であるGaAs半導体からなる基板上にn型Ga
Asを含む半導体からなる活性層を形成する工程、(b
)前記活性層表面から該活性層の深さの2.5倍以上の
深さに当該活性層のキャリア濃度の1/10以下のホウ
素イオンをイオン注入する工程を有することを要旨とす
る。[Means for Solving the Problems] In order to solve the above problems, the present invention provides (a) an n-type GaAs semiconductor substrate on a substrate made of a substantially insulating GaAs semiconductor;
Step of forming an active layer made of a semiconductor containing As, (b
) The method comprises the step of implanting boron ions having a carrier concentration of 1/10 or less of the active layer to a depth of 2.5 times or more the depth of the active layer from the surface of the active layer.
なお、活性層の深さは、その表面から当該活性層の最大
キャリア濃度に対し1/eまて低下したキャリア濃度点
(表面から深い側の当該キャリア濃度点)までの深さを
指し、そのeの値は、当該活性層がイオン注入法又はエ
ビタキンヤル成長法等の形成法の別によりe−2〜]0
の値に選ばれる。また、一般に、活性層のキャリア濃度
は単位体積当りで表わされ、イオン注入量は単位面積当
りで表わされるため、活性層のキャリア濃度の]/10
以下のイオン注入量とは、活性層のキャリア濃度を、そ
の表面から上述の活性層の深さまで積分した量の1/1
0以下のイオン量を指す。Note that the depth of the active layer refers to the depth from its surface to a carrier concentration point that is 1/e lower than the maximum carrier concentration of the active layer (the carrier concentration point on the deep side from the surface), and The value of e is e-2 to ]0 depending on the formation method such as the ion implantation method or the epitaaxial growth method when the active layer is formed.
is chosen as the value of Furthermore, in general, the carrier concentration in the active layer is expressed per unit volume, and the ion implantation amount is expressed per unit area, so the carrier concentration in the active layer is ]/10
The following ion implantation amount is 1/1 of the amount obtained by integrating the carrier concentration of the active layer from its surface to the depth of the active layer described above.
Refers to the amount of ions less than 0.
[作用]
活性層にホウ素イオンがイオン注入されると、そのイオ
ン注入で形成されるキャリアトラップにより注入領域が
高抵抗化する。この場合の高抵抗層の導電機構は、第1
図に示すように、aニオ−ミック領域
b=トラップ充填領域
C:空間電荷制限領域
に分けられる。オーミック領域aの電流1ohmは、有
効電流径路をd(第2図参照)とすると次式で表わされ
る。[Operation] When boron ions are implanted into the active layer, the implanted region becomes highly resistive due to carrier traps formed by the ion implantation. The conductive mechanism of the high resistance layer in this case is the first
As shown in the figure, it is divided into a niomic region, b = trap filling region C: space charge limited region. A current of 1 ohm in the ohmic region a is expressed by the following equation, assuming that the effective current path is d (see FIG. 2).
工Ohm!qIlno 11μ00v/d ・・・
(1)ここに
q:電荷素置
no :高抵抗層の平衡キャリア濃度
μ0 :高抵抗層の電子移動度
V:印加電圧
なお、第2図中、1は半絶縁性GaAs基板、2は活性
層、3は特性評価用のオーミック電極、4が高抵抗層で
ある。Engineering Ohm! qIlno 11μ00v/d...
(1) where q: charge element no: equilibrium carrier concentration μ0 of high resistance layer: electron mobility of high resistance layer V: applied voltage. In Fig. 2, 1 is a semi-insulating GaAs substrate, 2 is an active Layer 3 is an ohmic electrode for characteristic evaluation, and layer 4 is a high resistance layer.
また、オーミック領域aとトラップ充填領域すの境界電
圧vcは次式で表わされる。Further, the boundary voltage vc between the ohmic region a and the trap filling region is expressed by the following equation.
VC−(q−Nt/2ε) ・d2 ・−(
2)ここに、
Ntニドラップ濃度
と:誘電率
形成された高抵抗層に高い電界を印加しても所要の高い
抵抗率を得るためにはIohmか小さく境界電圧VCが
大きいことか必要である。このためには有効電流径路d
を大、即ち、イオンの注入深さ(イオンの侵入距離RP
)を大にすることか必要である。イオンの侵入距離RP
を活性層の深さの2.5倍以上にすると境界電圧VCは
従来技術に比べて約2倍程度以上となることが判明し、
イオンの注入深さを活性層の2.5倍以上とすることに
より高抵抗層に高い電界を印加しても所要の高い抵抗率
を得ることが可能となる。活性層が厚い場合、その2.
5倍以上の注入深さとするため、高エネルギーでイオン
注入すると活性層表面のダメージが増して表面リークが
増えることが懸念される。この場合は多重注入を用いる
ことで解決が可能である。一方、イオン注入量が大きく
なり過ぎると、活性層表面のダメージが増し、オーミッ
ク領域aての電気抵抗が低下してリーク電流か増える。VC-(q-Nt/2ε) ・d2 ・-(
2) Here, Nt Nidrap concentration: Even if a high electric field is applied to a high resistance layer formed with a dielectric constant, in order to obtain the required high resistivity, it is necessary that Iohm be small and the boundary voltage VC be large. For this purpose, the effective current path d
is large, that is, the ion implantation depth (ion penetration distance RP
) is necessary. Ion penetration distance RP
It has been found that when the depth of the active layer is made 2.5 times or more, the boundary voltage VC becomes about twice or more compared to the conventional technology.
By making the ion implantation depth 2.5 times or more deeper than the active layer, it is possible to obtain the required high resistivity even when a high electric field is applied to the high resistance layer. If the active layer is thick, 2.
Since the implantation depth is five times or more, there is a concern that if ions are implanted with high energy, damage to the surface of the active layer will increase and surface leakage will increase. This case can be solved by using multiple injections. On the other hand, if the amount of ion implantation becomes too large, damage to the surface of the active layer increases, the electrical resistance of the ohmic region a decreases, and leakage current increases.
イオン注入量の増加とともにリーク電流が増加し始める
のは、およそホウ素イオンの濃度が活性層のキャリア濃
度の1/1oを超える付近である。このため注入するホ
ウ素イオンの注入量は活性層のキャリア濃度の1 /
1.0以下に抑えられる。以上のように、活性層表面か
らその活性層の深さの2.5倍以上の深さに、当該活性
層のキャリア濃度の1/10以下のホウ素イオンをイオ
ン注入することにより、形成された高抵抗層に高い電界
を印加しても所要の高い抵抗率が得られて十分に素子間
等の分離か可能となる。The leakage current begins to increase as the amount of ion implantation increases when the concentration of boron ions exceeds approximately 1/10 of the carrier concentration of the active layer. Therefore, the amount of boron ions to be implanted is 1/ of the carrier concentration in the active layer.
It can be suppressed to 1.0 or less. As described above, boron ions with a carrier concentration of 1/10 or less of the active layer are ion-implanted from the surface of the active layer to a depth of 2.5 times or more the depth of the active layer. Even if a high electric field is applied to the high-resistance layer, the required high resistivity can be obtained, making it possible to sufficiently isolate elements.
[実施例] 以下、この発明の実施例を図面を参照して説明する。[Example] Embodiments of the present invention will be described below with reference to the drawings.
第3図(A)に示すように、半絶縁性GaAs基板1の
一主面に2981+イオンをイオン注入してn型の活性
層2を形成する。イオン注入の条件は、加速電圧100
keV、ドース量5×1012/c−とじ、イオン注入
後アニールを施した。この条件で得た活性層2の深さは
850Aである。活性層2の表面には形成する高抵抗層
の電気的特性評価のため、2μmの間隔をおいて1対の
オーミック電極3を形成した。As shown in FIG. 3(A), 2981+ ions are implanted into one main surface of the semi-insulating GaAs substrate 1 to form an n-type active layer 2. As shown in FIG. The conditions for ion implantation are an acceleration voltage of 100
keV, a dose of 5×10 12 /c−, and annealing was performed after ion implantation. The depth of the active layer 2 obtained under these conditions was 850A. A pair of ohmic electrodes 3 were formed on the surface of the active layer 2 with an interval of 2 μm in order to evaluate the electrical characteristics of the high resistance layer to be formed.
次いで、オーミック電極3をマスクとして活性層2に1
184イオンをイオン注入して高抵抗層4を形成する(
第3図(B))。イオン注入の条件は、ドーズ量4X1
01’/c−で、加速電圧は特性評価の目的て50〜1
60keVの間で可変した。加速電圧160keVて、
イオンの注入深さは活性層2の深さの2.5倍以上とな
る。Next, using the ohmic electrode 3 as a mask, a layer of 1 is applied to the active layer 2.
184 ions are implanted to form a high resistance layer 4 (
Figure 3 (B)). The conditions for ion implantation are a dose of 4X1.
01'/c-, and the acceleration voltage was 50~1 for the purpose of characteristic evaluation.
It varied between 60 keV. Accelerating voltage 160keV,
The depth of ion implantation is 2.5 times or more the depth of the active layer 2.
第4図は、上記のようにして形成した試料について境界
電圧VCの加速電圧依存性の測定結果を示している。従
来技術における加速電圧はせいぜい100keVである
。これに対し、加速電圧160keVてイオン注入して
イオン注入の深さを活性層2の深さの2.5倍以上とす
ると、境界電圧VCは従来技術の約2.5倍になること
が分る。FIG. 4 shows the measurement results of the acceleration voltage dependence of the boundary voltage VC for the sample formed as described above. The accelerating voltage in the prior art is at most 100 keV. On the other hand, if ions are implanted at an acceleration voltage of 160 keV and the ion implantation depth is 2.5 times or more the depth of the active layer 2, the boundary voltage VC is found to be approximately 2.5 times that of the conventional technique. Ru.
また、第5図は、イオン注入の深さとオーミック電極3
.3間のリーク電流との関係の測定結果を示している。In addition, FIG. 5 shows the depth of ion implantation and the ohmic electrode 3.
.. 3 shows the measurement results of the relationship between the leakage current and the leakage current.
印加電界はIOV/2μmである。The applied electric field is IOV/2 μm.
測定結果は、活性層2の深さ850人に対し、イオン注
入の深さをそのほぼ2.5倍である210OA以上にす
ると、リーク電流は1.0×1O−7A程度以下に減少
して実用に供し得る値まで減少し、はぼ3倍以上である
290OA以上にするとリーク電流は2 X ]、 O
−8A程度となって飽和する。The measurement results show that for a depth of 850 people in the active layer 2, when the ion implantation depth is increased to 210 OA or more, which is approximately 2.5 times that depth, the leakage current decreases to about 1.0 x 1 O-7 A or less. When the leakage current is reduced to a value that can be used in practical use and exceeds 290OA, which is more than three times as much, the leakage current becomes 2
It becomes saturated at about -8A.
この実施例から、活性層2の表面からその活性層2の深
さの2.5倍以上の深さに、当該活性層のキャリア濃度
の1/10以下の11 B+イオンをイオン注入する
ことにより、高い電界を印加しても十分に素子間等の分
離か可能な高抵抗層4かGaAs基板1上に得られるこ
とが分る。From this example, by ion-implanting 11B+ ions with a carrier concentration of 1/10 or less of the carrier concentration of the active layer 2 from the surface of the active layer 2 to a depth of 2.5 times or more the depth of the active layer 2, It can be seen that even when a high electric field is applied, a high-resistance layer 4 is obtained on the GaAs substrate 1, which allows sufficient isolation between elements.
[発明の効果]
以上説明したように、この発明によれば、活性層表面か
らその活性層の深さの2.5倍以上の深さに、当該活性
層のキャリア濃度の1/10以下のホウ素イオンをイオ
ン注入するようにしたため、高い電界を印加してもリー
ク電流か少なく十分に素子間等の分離が可能な高抵抗層
を基板上に形成することができる。[Effects of the Invention] As explained above, according to the present invention, a carrier concentration of 1/10 or less of the carrier concentration of the active layer is formed from the surface of the active layer to a depth of 2.5 times or more the depth of the active layer. Since boron ions are implanted, a high-resistance layer can be formed on the substrate with little leakage current even when a high electric field is applied, and which can sufficiently isolate elements.
第1図及び第2図はこの発明に係る半導体装置の製造方
法で形成される高抵抗層の特性を説明するためのもので
、第1図は導電機構を説明するための印加電圧対電流特
性を示す特性図、第2図は有効電流径路を説明するため
の縦断面図、第3図ないし第5図はこの発明の詳細な説
明するためのもので、第3図は高抵抗層の形成工程を説
明するための工程図、第4図は形成された高抵抗層にお
ける境界電圧の加速電圧依存性を示す特性図、第5図は
イオン注入の深さと高抵抗層のリーク電流との関係を示
す特性図である。
1・半絶縁性GaAs基板、
2:活性層、 4:高抵抗層。1 and 2 are for explaining the characteristics of the high resistance layer formed by the method for manufacturing a semiconductor device according to the present invention, and FIG. 1 is for explaining the applied voltage vs. current characteristics for explaining the conduction mechanism. FIG. 2 is a longitudinal cross-sectional view for explaining the effective current path, FIGS. 3 to 5 are for explaining the invention in detail, and FIG. 3 is a diagram showing the formation of the high resistance layer. A process diagram for explaining the process, Figure 4 is a characteristic diagram showing the acceleration voltage dependence of the boundary voltage in the formed high resistance layer, and Figure 5 is the relationship between the depth of ion implantation and the leakage current of the high resistance layer. FIG. 1. Semi-insulating GaAs substrate, 2: Active layer, 4: High resistance layer.
Claims (1)
板上にn型GaAsを含む半導体からなる活性層を形成
する工程、 (b)前記活性層表面から該活性層の深さの2.5倍以
上の深さに当該活性層のキャリア濃度の1/10以下の
ホウ素イオンをイオン注入する工程 を有することを特徴とする半導体装置の製造方法。Scope of Claims: (a) a step of forming an active layer made of a semiconductor containing n-type GaAs on a substrate made of a substantially insulating GaAs semiconductor; (b) a step of forming an active layer made of a semiconductor containing n-type GaAs from the surface of the active layer; A method for manufacturing a semiconductor device, comprising the step of implanting boron ions with a carrier concentration of 1/10 or less of the active layer to a depth of 2.5 times or more.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24392590A JPH04124854A (en) | 1990-09-17 | 1990-09-17 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24392590A JPH04124854A (en) | 1990-09-17 | 1990-09-17 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04124854A true JPH04124854A (en) | 1992-04-24 |
Family
ID=17111063
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP24392590A Pending JPH04124854A (en) | 1990-09-17 | 1990-09-17 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
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JP (1) | JPH04124854A (en) |
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1990
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US7091008B1 (en) | 1994-07-01 | 2006-08-15 | The Board Of Regents Of The University Of Oklahoma | Hyaluronan synthase genes and expression thereof in Bacillus hosts |
US8735102B2 (en) | 1994-07-01 | 2014-05-27 | The Board Of Regents Of The University Of Oklahoma | Hyaluronan synthase genes and expression thereof in Bacillus hosts |
US6833264B1 (en) | 1997-10-31 | 2004-12-21 | The Board Of Regents Of The University Of Oklahoma | Hyaluronan synthase gene and uses therof |
US6987023B2 (en) | 1998-04-02 | 2006-01-17 | The Board Of Regents Of The University Of Oklahoma | DNA encoding hyaluronan synthase from Pasteurella multocida and methods of use |
US7223571B2 (en) | 1998-04-02 | 2007-05-29 | The Board Of Regents Of The Universtiy Of Oklahoma | Targeted glycosaminoglycan polymers by polymer grafting and methods of making and using same |
US7579173B2 (en) | 1998-04-02 | 2009-08-25 | The Board Of Regents Of The University Of Oklahoma | Targeted glycosaminoglycan polymers by polymer grafting and methods of making and using the same |
US7604973B2 (en) | 1998-04-02 | 2009-10-20 | The Board Of Regents Of The University Of Oklahoma | DNA encoding hyaluronan synthase from Pasteurella multocida and methods of use |
US7741091B2 (en) | 1998-04-02 | 2010-06-22 | The Board Of Regents Of The University Of Oklahoma | Methods of producing hyaluronic acid and chimeric and hybrid glycosaminoglycan polymers |
US7094581B2 (en) | 1998-10-26 | 2006-08-22 | The Board Of Regents Of The University Of Oklahoma | Hyaluronan synthases and methods of making and using same |
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