JPH04116859A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH04116859A
JPH04116859A JP2237713A JP23771390A JPH04116859A JP H04116859 A JPH04116859 A JP H04116859A JP 2237713 A JP2237713 A JP 2237713A JP 23771390 A JP23771390 A JP 23771390A JP H04116859 A JPH04116859 A JP H04116859A
Authority
JP
Japan
Prior art keywords
chip
size
package
chips
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2237713A
Other languages
Japanese (ja)
Other versions
JP2871041B2 (en
Inventor
Hiroshi Sawano
沢野　寛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2237713A priority Critical patent/JP2871041B2/en
Publication of JPH04116859A publication Critical patent/JPH04116859A/en
Application granted granted Critical
Publication of JP2871041B2 publication Critical patent/JP2871041B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To reduce the size of a package by forming a chip wherein the circuit function of a semiconductor device is divided into two chips, and sealing said chips which are stacked in the same package. CONSTITUTION:The title semiconductor device is formed by dividing a chip constituting a circuit into two chips, and sealing the divided chips which are stacked. Thereby a chip size is restrained and the defective rate can be decreased. Since the package size is reduced, the mounting area can be made small.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は半導体装置に関するものである。[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor device.

〔従来技術〕[Prior art]

図１は従来の半導体装置の断面図であり、（１）はチッ
プ、（２）はダイパッド、（３）はワイヤ、（４）は封
止樹脂、（５）は外部リード示す。FIG. 1 is a cross-sectional view of a conventional semiconductor device, in which (1) shows a chip, (2) a die pad, (3) a wire, (4) a sealing resin, and (5) an external lead.

次にこの構成について説明する。従来は半導体装置は一
つのパッケージ内に一つチップを封止してその機能を発
揮して来た。そしてその機能はとんとんと高集積化され
複雑なものに又大きなチップに変わって来た。この為、
特に記憶用半導体装置では従来、パッケージの大きさは
変化させないで容量のみの増加を図かってきた。Next, this configuration will be explained. Conventionally, semiconductor devices have performed their functions by sealing one chip within one package. Their functions have become increasingly highly integrated, complex, and require large chips. For this reason,
Particularly in storage semiconductor devices, conventional efforts have been to increase only the capacity without changing the size of the package.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の半導体装置はパッケージの大きさを変えないで機
能容量を増加を図って来のて多機能、高容量となり大変
使いやすかった。が−層の多機能、大容量で達成するに
はチップの回路の縮小だけでは限界が見えており、とう
してもパッケージそのものも大きくせざるを得ない状況
となって来た。Conventional semiconductor devices have been designed to increase functional capacity without changing the size of the package, resulting in multifunctionality, high capacity, and great ease of use. However, in order to achieve multi-layer functionality and high capacity, it is becoming clear that there is a limit to simply reducing the size of the chip circuit, and the package itself has to be made larger.

例えばダイナミックメモリを考えた場合、ＩＭの容量迄
は同一のパッケージサイズに封止可能であったが４Ｍで
は一部不可能となった。又チップサイズの増大は不良率
の増加もまねき、これ迄の多機能、大容量化を行ないな
がらコストダウンを行う半導体の長所が限界に近くなっ
て来た。For example, when considering dynamic memory, it was possible to package up to the IM capacity in the same package size, but with 4M, this is partially impossible. In addition, the increase in chip size has also led to an increase in the defective rate, and the advantages of semiconductors, which have been able to reduce costs while providing multiple functions and increasing capacity, are approaching their limits.

この発明は上記の様な問題を解決する事になされたもの
である。多機能、大容量化を安価に達成するには程良い
チップサイズ従来と同じパッケージサイズが大変好まし
い。This invention was made to solve the above problems. To achieve multi-functionality and large capacity at low cost, it is very desirable to have a chip size that is the same as the conventional one.

〔問題を解決するだめの手段〕[Failure to solve the problem]

この発明における半導体装置は回路を構成するチップを
２分割しチップサイズの大形化を避け、又分割したチッ
プを重ね合せて封止する事によりパッケージサイズの減
少を図っている。In the semiconductor device of the present invention, the chip constituting the circuit is divided into two to avoid increasing the chip size, and the divided chips are overlapped and sealed to reduce the package size.

〔作用］ チップサイズの２分割はゴミ等の問題によりチップサイ
ズに逆比例して増大する不良率の低減に寄与し、かつ重
ね合せた事によりパッケージサイズの減少にもなり、実
装密度の向上が得られる。[Effect] Dividing the chip size into two contributes to reducing the defect rate, which increases inversely with the chip size due to problems such as dust, and stacking them also reduces the package size, improving packaging density. can get.

〔実施例〕〔Example〕

図２においてαυと０２は２分割されたチップであり、
（２）はダイパッド、（３）はワイヤ、（４）は封止樹
脂、（５）は外部リードを示す。In Figure 2, αυ and 02 are chips divided into two,
(2) is a die pad, (3) is a wire, (4) is a sealing resin, and (5) is an external lead.

チップを２分割する事によりチップサイズの大形化を避
は不良率の低減を図り、かつそれらのチップを重ね合せ
る事によりパッケージサイズの減少か行え、これにより
実装面積が少なくなり、特にコンピュータ等の多数の半
導体装置を使用するシステムでは大変コンパクトにする
事か可能である。By dividing the chip into two, it is possible to avoid increasing the chip size and reduce the defective rate, and by stacking the chips, it is possible to reduce the package size, which reduces the mounting area, especially for computers etc. A system using a large number of semiconductor devices can be made very compact.

なお図ではチップの上にチップを乗せたプラスチックパ
ッケージで説明したか、ダイパッドの両面に取りつけて
も良く又セラミックパッケージでも可能である。In the figure, a plastic package is illustrated in which a chip is mounted on a chip, but it may also be attached to both sides of a die pad, or a ceramic package may also be used.

〔発明の効果〕〔Effect of the invention〕

チップを２分割したのでｌヶ当りのチップサイズが抑え
られ不良率が減少でき、かつ重ね合せた事によりパッケ
ージサイズか減少できる事により実装面積が小さくでき
る。Since the chip is divided into two parts, the chip size per unit can be suppressed and the defective rate can be reduced, and by stacking the chips, the package size can be reduced and the mounting area can be reduced.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来のものの断面図であり、（＋＋はチップ、
（２）はダイパッド、（３）はワイヤ、（４）は封止樹
脂、（５）は外部リードを示す。第２図は本発明による
半導体装置の断面図てあり、αυ、α２はチップ、（２
）はダイパッド、（３）はワイヤ、（４）は封止樹脂、
（５）は外部リードを示す。 なお、図中、同一符号は同一　または相当部分を示す。Figure 1 is a cross-sectional view of a conventional device (++ is a chip,
(2) is a die pad, (3) is a wire, (4) is a sealing resin, and (5) is an external lead. FIG. 2 is a cross-sectional view of the semiconductor device according to the present invention, where αυ and α2 are chips, (2
) is the die pad, (3) is the wire, (4) is the sealing resin,
(5) indicates an external lead. In addition, the same symbols in the figures indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] 　半導体装置において回路の機能を２分割したチップを
作り、そのチップを同一パッケージ内に重ね合せて封止
する事によりパッケージの大きさを１／２に削減する事
を特徴とした半導体装置。A semiconductor device characterized in that the size of the package can be reduced to 1/2 by creating a chip in which the circuit function is divided into two, and stacking and sealing the chips in the same package.
JP2237713A 1990-09-06 1990-09-06 Semiconductor device Expired - Fee Related JP2871041B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2237713A JP2871041B2 (en) 1990-09-06 1990-09-06 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2237713A JP2871041B2 (en) 1990-09-06 1990-09-06 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH04116859A true JPH04116859A (en) 1992-04-17
JP2871041B2 JP2871041B2 (en) 1999-03-17

Family

ID=17019397

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2237713A Expired - Fee Related JP2871041B2 (en) 1990-09-06 1990-09-06 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2871041B2 (en)

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5760478A (en) * 1996-08-20 1998-06-02 International Business Machines Corporation Clock skew minimization system and method for integrated circuits
US5780925A (en) * 1992-10-28 1998-07-14 International Business Machines Corporation Lead frame package for electronic devices
US5838603A (en) * 1994-10-11 1998-11-17 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for fabricating the same, memory core chip and memory peripheral circuit chip
US6552416B1 (en) 2000-09-08 2003-04-22 Amkor Technology, Inc. Multiple die lead frame package with enhanced die-to-die interconnect routing using internal lead trace wiring
US6555917B1 (en) 2001-10-09 2003-04-29 Amkor Technology, Inc. Semiconductor package having stacked semiconductor chips and method of making the same
US6642610B2 (en) 1999-12-20 2003-11-04 Amkor Technology, Inc. Wire bonding method and semiconductor package manufactured using the same
US6737750B1 (en) 2001-12-07 2004-05-18 Amkor Technology, Inc. Structures for improving heat dissipation in stacked semiconductor packages
US6798049B1 (en) 1999-08-24 2004-09-28 Amkor Technology Inc. Semiconductor package and method for fabricating the same
US6879047B1 (en) 2003-02-19 2005-04-12 Amkor Technology, Inc. Stacking structure for semiconductor devices using a folded over flexible substrate and method therefor
US6946323B1 (en) 2001-11-02 2005-09-20 Amkor Technology, Inc. Semiconductor package having one or more die stacked on a prepackaged device and method therefor
US7154171B1 (en) 2002-02-22 2006-12-26 Amkor Technology, Inc. Stacking structure for semiconductor devices using a folded over flexible substrate and method therefor
US7342309B2 (en) 2005-05-06 2008-03-11 Oki Electric Industry Co., Ltd. Semiconductor device and fabrication method thereof
US7485490B2 (en) 2001-03-09 2009-02-03 Amkor Technology, Inc. Method of forming a stacked semiconductor package
US8159062B2 (en) 2000-01-31 2012-04-17 Elpida Memory, Inc. Semiconductor and a method of manufacturing the same
US9768124B2 (en) 2007-02-21 2017-09-19 Amkor Technology, Inc. Semiconductor package in package

Cited By (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5780925A (en) * 1992-10-28 1998-07-14 International Business Machines Corporation Lead frame package for electronic devices
US5838603A (en) * 1994-10-11 1998-11-17 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for fabricating the same, memory core chip and memory peripheral circuit chip
US6064585A (en) * 1994-10-11 2000-05-16 Matsushita Electric Industrial Co. Semiconductor device and method for fabricating the same, memory core chip and memory peripheral circuit chip
US6313493B1 (en) 1994-10-11 2001-11-06 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for fabricating the same, memory core chip and memory peripheral circuit chip
US5760478A (en) * 1996-08-20 1998-06-02 International Business Machines Corporation Clock skew minimization system and method for integrated circuits
US6798049B1 (en) 1999-08-24 2004-09-28 Amkor Technology Inc. Semiconductor package and method for fabricating the same
US6642610B2 (en) 1999-12-20 2003-11-04 Amkor Technology, Inc. Wire bonding method and semiconductor package manufactured using the same
US6803254B2 (en) 1999-12-20 2004-10-12 Amkor Technology, Inc. Wire bonding method for a semiconductor package
US8159062B2 (en) 2000-01-31 2012-04-17 Elpida Memory, Inc. Semiconductor and a method of manufacturing the same
US8853864B2 (en) 2000-01-31 2014-10-07 Ps4 Luxco S.A.R.L. Semiconductor device and a method of manufacturing the same
US8502395B2 (en) 2000-01-31 2013-08-06 Elpida Memory, Inc. Semiconductor device and a method of manufacturing the same
US6552416B1 (en) 2000-09-08 2003-04-22 Amkor Technology, Inc. Multiple die lead frame package with enhanced die-to-die interconnect routing using internal lead trace wiring
US7485490B2 (en) 2001-03-09 2009-02-03 Amkor Technology, Inc. Method of forming a stacked semiconductor package
US6555917B1 (en) 2001-10-09 2003-04-29 Amkor Technology, Inc. Semiconductor package having stacked semiconductor chips and method of making the same
US6946323B1 (en) 2001-11-02 2005-09-20 Amkor Technology, Inc. Semiconductor package having one or more die stacked on a prepackaged device and method therefor
US6919631B1 (en) 2001-12-07 2005-07-19 Amkor Technology, Inc. Structures for improving heat dissipation in stacked semiconductor packages
US6737750B1 (en) 2001-12-07 2004-05-18 Amkor Technology, Inc. Structures for improving heat dissipation in stacked semiconductor packages
US7154171B1 (en) 2002-02-22 2006-12-26 Amkor Technology, Inc. Stacking structure for semiconductor devices using a folded over flexible substrate and method therefor
US6879047B1 (en) 2003-02-19 2005-04-12 Amkor Technology, Inc. Stacking structure for semiconductor devices using a folded over flexible substrate and method therefor
US7342309B2 (en) 2005-05-06 2008-03-11 Oki Electric Industry Co., Ltd. Semiconductor device and fabrication method thereof
US7432128B2 (en) 2005-05-06 2008-10-07 Oki Electric Industry Co., Ltd. Method of making semiconductor device
KR101247389B1 (en) * 2005-05-06 2013-03-25 오끼 덴끼 고오교 가부시끼가이샤 Semiconductor device and method for manufacturing the same
US9768124B2 (en) 2007-02-21 2017-09-19 Amkor Technology, Inc. Semiconductor package in package

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