JPH04112362A - Accumulation circuit - Google Patents
Accumulation circuitInfo
- Publication number
- JPH04112362A JPH04112362A JP2232914A JP23291490A JPH04112362A JP H04112362 A JPH04112362 A JP H04112362A JP 2232914 A JP2232914 A JP 2232914A JP 23291490 A JP23291490 A JP 23291490A JP H04112362 A JPH04112362 A JP H04112362A
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- circuits
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- 238000009825 accumulation Methods 0.000 title claims abstract description 27
- 238000004364 calculation method Methods 0.000 claims description 82
- 230000035508 accumulation Effects 0.000 claims description 24
- 230000001186 cumulative effect Effects 0.000 claims description 11
- 210000004027 cell Anatomy 0.000 description 10
- 238000010586 diagram Methods 0.000 description 10
- 238000013528 artificial neural network Methods 0.000 description 7
- 238000003909 pattern recognition Methods 0.000 description 7
- 230000006870 function Effects 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 210000002569 neuron Anatomy 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 229930183689 terminalin Natural products 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000001537 neural effect Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
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Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は累積回路に係り、特にパターン認識やニューラ
ルネットワーク回路の演算において、多数の入力と計数
の相関を計算する場合に使用される累積回路に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an accumulation circuit, and in particular to an accumulation circuit used to calculate correlations between a large number of inputs and counts in pattern recognition and neural network circuit operations. Regarding.
ニューラルネットワーク回路は生物の神経回路mをモデ
ル化して、従来のノイマン形計算機では難しかった文字
認識や音声認識等のパターン認識処理、最適化問題、ロ
ボット制御等を実現するものである。従来のノイマン形
計算機ではプログラムに従って逐次処理するために膨大
な計算時間か必要とされたか、ニューラルネットワーク
回路ではニューロン回路か並列に演算を実行できるのて
処理速度か極めて高速になる特徴かある。また、同一の
ニューロン回路を多数接続してネットワクを構成するこ
とにより、故障した回路があっても他の正常な回路に簡
単に置き換えて動作できるので、LSI化する場合なと
に高い欠陥耐性を実現できる。このようなニューラルネ
ットワーク回路なとて使用される累積回路は回路規模を
低減することか要求されている。Neural network circuits model biological neural circuits m to realize pattern recognition processing such as character recognition and speech recognition, optimization problems, robot control, etc., which were difficult with conventional Neumann type computers. Conventional Neumann type computers require a huge amount of calculation time to perform sequential processing according to the program, whereas neural network circuits have extremely high processing speeds because they can perform calculations in parallel using neuron circuits. In addition, by configuring a network by connecting many identical neuron circuits, even if there is a faulty circuit, it can be easily replaced with another normal circuit. realizable. There is a need to reduce the circuit scale of accumulation circuits used as such neural network circuits.
第4図は従来のニューラルネッ)・ワーク回路等て使用
されていた累積回路の構成図を示す。FIG. 4 shows a block diagram of an accumulation circuit used in a conventional neural network circuit.
40〜40.は入力端子、4111〜41.、。はメモ
リ回路、421□〜42m、、は係数演算回路、431
、〜43−は加算回路、44.〜44.は閾値回路、4
51〜45.は出力端子、46.〜46、は単位回路で
ある。40-40. are input terminals, 4111-41. ,. is a memory circuit, 421□~42m, is a coefficient calculation circuit, 431
, ~43- are adder circuits, 44. ~44. is a threshold circuit, 4
51-45. is an output terminal, 46. -46 are unit circuits.
累積回路はn個(nは1以上の整数)の入力端子401
〜40fiと、m個(mは1以上の整数)の出力端子4
5.〜45.をもっており、m個の同一構造の単位回路
461〜46.、て構成されている。The accumulation circuit has n input terminals 401 (n is an integer greater than or equal to 1).
~40fi and m output terminals 4 (m is an integer greater than or equal to 1)
5. ~45. It has m unit circuits 461 to 46 . of the same structure. , is made up of.
単位回路46□〜46□はn個の入力端子40、〜40
゜からの信号とメモリ回路41,1〜41、ゎに記憶さ
れた係数との差や距離あるいは係数による荷重値などを
求める係数演算回路42.。Unit circuits 46□ to 46□ have n input terminals 40, to 40
A coefficient calculating circuit 42 which calculates the difference between the signal from ゜ and the coefficient stored in the memory circuits 41, 1 to 41, ゎ, the distance, or the load value based on the coefficient. .
〜42.afiをn個もち、n個の係数演算回路421
〜42.。の出力を全て加算する加算回路433.〜4
3、ffiと1個の閾値回路441〜44.とによって
構成されている。~42. n afi and n coefficient calculation circuits 421
~42. . An adder circuit 433 that adds all the outputs of . ~4
3. ffi and one threshold circuit 441 to 44. It is composed of.
出力値を最終的に決定する閾値回路441〜44、は第
5図に示すような伝達特性をもっている。伝達特性を表
すものとして、同図(C)のシグモイド関数形か最も汎
用性か高いが、同図(A)のステップ関数形、同図(B
)の折れ線形のように簡単化したものか多く使用される
。The threshold circuits 441 to 44, which ultimately determine the output value, have transfer characteristics as shown in FIG. The sigmoid function form shown in figure (C) is the most versatile to represent the transfer characteristic, but the step function form shown in figure (A) and the step function form shown in figure (B) are the most versatile.
) is often used as a simplified version like the polygonal line.
m個の単位回路46.〜46..はそれぞれ独自の係数
をもっており、例えば、パターン認識なとてはとの単位
回路461〜46.の出力端子45、〜45.からの出
力が閾値回路441〜441の閾値レベルを上回りハイ
レベルになったかで入力端子401〜40.からの入カ
バターンを認識することができる。m unit circuits 46. ~46. .. have their own coefficients, for example, the unit circuits 461 to 46 . for pattern recognition. Output terminals 45, -45. The output from the input terminals 401-40. exceeds the threshold level of the threshold circuits 441-441 and becomes a high level. It is possible to recognize input patterns from
しかるに、第4図の従来の累積回路は1組の入力信号に
対して、それぞれの単位回路46.〜46、が並列に演
算を実行できるようになっているので、高速に演算でき
る利点がある。しかし、n個の入力端子401〜40.
とm個の出力端子45、〜45.を持っネットワークで
は、係数演算回路42,1〜42.、、と加算回路43
1.〜43.6がほぼnm個必要である。出力端子数m
はパターン認識などでは認識するカテゴリー数に応じて
大きくする必要かあるため、係数演算回路42,1〜4
2−と加算回路4311〜43ゆ、の回路数nmは極め
て大きな数になり、回路規模が大きくなり、また、多数
の演算回路4211〜42.。か同時に並列に動作する
ために回路動作に伴う消費電力も極めて大きくなるため
、累積回路をLSI化する場合に大きな問題になってい
た。However, the conventional accumulator circuit of FIG. 4 processes each unit circuit 46 . .about.46 can perform calculations in parallel, which has the advantage of being able to perform calculations at high speed. However, n input terminals 401 to 40 .
and m output terminals 45, to 45. In the network having coefficient calculation circuits 42,1 to 42. , , and the addition circuit 43
1. ~43.6 is required approximately in nm pieces. Number of output terminals m
Since it is necessary to increase the size according to the number of categories to be recognized in pattern recognition etc., the coefficient calculation circuit 42, 1 to 4
The number of circuits (nm) of the adder circuits 4311 to 43 .2- and the adder circuits 4311 to 43 . . However, since they operate in parallel at the same time, the power consumption associated with the circuit operation becomes extremely large, which has been a major problem when converting the accumulation circuit into an LSI.
本発明は上記の点に鑑みなされたもので従来の累積回路
の高速に演算できる利点を損なわずに、累積回路の回路
規模と消費電力を低減することかできる累積回路を提供
することを目的とする。The present invention has been made in view of the above points, and an object of the present invention is to provide an accumulation circuit that can reduce the circuit size and power consumption of the accumulation circuit without impairing the advantage of the conventional accumulation circuit in that it can perform high-speed calculations. do.
本発明はn(nは1より大きい整数)個の入力端子と、
m(mは1より大きい整数)個の出力端子を持ち、独自
のn個の係数で構成される係数組をm組もち、全ての係
数組について、i (iはlからnまでの整数)番目の
係数と1番目の入力端子信号間の差や距離あるいは係数
による荷重値などを係数演算回路により単一極性の係数
演算値として求め、1からnまでの係数演算値を全て累
積し、この累積結果を閾値処理して得られる変換値を出
力信号とする一連の演算を行う場合において、1からk
(kは1以上てnより小さい整数)番目の入力端子信号
に対しては前記係数演算値を求めるために1個の係数に
それぞれ専用の第1の係数演算回路と、1からに番目の
係数演算回路の出力の累積を行うための第1の加算回路
を有する回路をm組並列に配置し、m個の累積の途中結
果と閾値回路の飽和レベルを比較して残りの入力端子か
らの入力に対する演算を続行するかを判定し、演算の続
行か必要な累積の途中結果を出力する選択制御回路を備
え、演算の続行か必要な入力に対し、1個あるいは数個
の第2の係数演算回路と第2の加算回路を共通に使用し
て入力端子信号と係数値を切り換えて累積演算を続行し
、1からn番目の入力端子に対する累積結果を閾値回路
に入力し、閾値回路の処理結果を出力端子に出力する。The present invention includes n (n is an integer greater than 1) input terminals;
It has m output terminals (m is an integer greater than 1), has m coefficient sets each consisting of unique n coefficients, and for every coefficient set, i (i is an integer from l to n). The difference or distance between the th coefficient and the 1st input terminal signal or the weight value due to the coefficient is determined by the coefficient calculation circuit as a single polarity coefficient calculation value, and all the coefficient calculation values from 1 to n are accumulated. When performing a series of calculations in which the output signal is the converted value obtained by thresholding the accumulated results, from 1 to k
(k is an integer greater than or equal to 1 and less than n) For the input terminal signal, in order to obtain the coefficient calculation value, a first coefficient calculation circuit dedicated to one coefficient, and a first coefficient calculation circuit dedicated to each coefficient, m sets of circuits each having a first adder circuit for accumulating the outputs of the arithmetic circuits are arranged in parallel, and the intermediate results of m accumulations are compared with the saturation level of the threshold circuit to calculate the input from the remaining input terminals. It is equipped with a selection control circuit that determines whether to continue the calculation for the calculation and outputs the intermediate result of the necessary accumulation, and determines whether to continue the calculation or outputs the intermediate result of necessary accumulation. The circuit and the second addition circuit are used in common to switch the input terminal signal and coefficient value to continue the accumulation operation, input the accumulation results for the 1st to nth input terminals to the threshold circuit, and calculate the processing results of the threshold circuit. is output to the output terminal.
本発明は、各入力端子からの入力に対応する第1の係数
演算回路や第1の加算回路の累積値の出力段の閾値回路
の飽和特性を利用して累積途中結果の値と、閾値回路の
閾値レベルを比較し、閾値回路の飽和レベルかハイレベ
ルの場合に残りの入力信号の累積演算を途中から省略す
ることによって、大幅に演算回路を削減する。The present invention utilizes the saturation characteristics of the threshold circuit in the output stage of the cumulative value of the first coefficient calculation circuit and the first addition circuit corresponding to the input from each input terminal to calculate the value of the cumulative intermediate result and the threshold circuit. The number of arithmetic circuits can be significantly reduced by comparing the threshold levels of and omitting the cumulative calculation of the remaining input signals if the threshold circuit is at the saturation level or high level.
第1図は本発明の一実施例の回路構成図を示す。 FIG. 1 shows a circuit diagram of an embodiment of the present invention.
同図中、第4図と同一構成部分には同一符号を付し、そ
の説明を省略する。In the figure, the same components as those in FIG. 4 are denoted by the same reference numerals, and the explanation thereof will be omitted.
10は選択制御回路、12は係数RAM回路、14はレ
ジスタ回路、20は集中演算部てあり、複数のレジスタ
回路14+〜14.〜と、係数演算回路15+〜15.
−、、加算回路171〜17、、から構成されている。10 is a selection control circuit, 12 is a coefficient RAM circuit, 14 is a register circuit, and 20 is a centralized calculation unit, which includes a plurality of register circuits 14+ to 14. and coefficient calculation circuits 15+ to 15.
-, , addition circuits 171 to 17, .
18は出力レジスタ回路、19は閾値回路である。18 is an output register circuit, and 19 is a threshold circuit.
また、n個の入力端子40と、m個の出力端子45の数
は第4図と同様である。さらに、入力端子401〜。4
0にの信号に対しては従来と同様に並列に全ての計算に
応じて係数演算回路42++〜421、と加算回路43
,1〜43+tk−nか配置しである。これは、後述す
る第3図の入力端子INI〜IN4の列か該当している
。Further, the numbers of n input terminals 40 and m output terminals 45 are the same as in FIG. 4. Furthermore, input terminals 401-. 4
For a signal of 0, the coefficient calculation circuits 42++ to 421 and the addition circuit 43 are operated in parallel according to all calculations as in the conventional case.
, 1 to 43+tk-n. This corresponds to the rows of input terminals INI to IN4 in FIG. 3, which will be described later.
100は入力端子401〜40にの入力により並列演算
処理か行われる並列演算部である。Reference numeral 100 denotes a parallel calculation unit that performs parallel calculation processing based on inputs to input terminals 401-40.
一方、入力端子40Lk+z〜40.の入力に対しては
第1図に示す集中演算部20のみて演算を実行するよう
になっている。これは後述する第3図の入力端子INS
以降の列が該当する。On the other hand, input terminal 40Lk+z~40. In response to the input, only the centralized calculation unit 20 shown in FIG. 1 executes the calculation. This is the input terminal INS in Figure 3, which will be described later.
The following columns apply.
入力端子40.〜40.に対する演算の途中結果はm個
の出力端子45.〜45.に対応してm個存在し、それ
らはすべて選択制御回路10に入力される。Input terminal 40. ~40. The intermediate results of the calculations for m output terminals 45. ~45. There are m pieces corresponding to , and all of them are input to the selection control circuit 10 .
選択制御回路lOは予め閾値回路19の飽和レベルの情
報を保持しており上記累積の途中結果をの値と閾値回路
19の飽和レベルを比較を行う。The selection control circuit 10 holds information on the saturation level of the threshold circuit 19 in advance, and compares the intermediate result of the accumulation with the saturation level of the threshold circuit 19.
その結果、閾値回路19の飽和レベルに満たない場合に
は選択制御回路IOはm個の加算回路43.1〜43.
。−1,の演算途中結果から1個を選択して集中演算部
20に入力している。このとき選択制御回路10は出力
端子45.〜45゜のうち何番目の出力端子45.〜4
5.に対応する信号を選択したかをアドレス信号として
同時に出力している。そのアドレス信号は係数RAM回
路12と出力レジスタ回路18に入力される。As a result, if the saturation level of the threshold circuit 19 is not reached, the selection control circuit IO operates the m adder circuits 43.1 to 43.
. -1, one of the intermediate results of the calculation is selected and input to the centralized calculation section 20. At this time, the selection control circuit 10 outputs the output terminal 45. Which output terminal 45. ~4
5. It simultaneously outputs as an address signal whether the signal corresponding to is selected. The address signal is input to the coefficient RAM circuit 12 and the output register circuit 18.
また、選択制御回路10は閾値回路19の飽和レベルと
累積結果を比較して飽和レベルに達していた場合には、
次の入力に対しては集中演算部20において演算を行う
ようアドレス信号を出力する。Further, the selection control circuit 10 compares the saturation level of the threshold circuit 19 with the cumulative result, and if the saturation level has been reached,
For the next input, an address signal is outputted so that the centralized calculation section 20 performs the calculation.
係数RAM回路12は選択制御回路lOのアドレス信号
によって必要な係数データを読み出して集中演算部20
の入力端子に該当するレジスタ回路14.〜14 n−
kに転送する。The coefficient RAM circuit 12 reads out necessary coefficient data in accordance with the address signal of the selection control circuit 10 and outputs it to the centralized calculation unit 20.
The register circuit corresponding to the input terminal of 14. ~14 n-
Transfer to k.
転送された係数データは入力端子40Lk+++〜40
、の入力信号と集中演算部16の入力端子に該当する係
数演算部151〜15.、て演算か実行され、加算回路
17.〜17..演算の途中結果と累積されて、全入力
に対する演算の累積結果は閾値回路1.9に入力される
。The transferred coefficient data is input terminal 40Lk++~40
, and the coefficient calculation units 151 to 15. which correspond to the input signals of the input terminals of the centralized calculation unit 16. , the calculation is executed, and the addition circuit 17. ~17. .. The cumulative results of the calculations for all inputs are accumulated with the intermediate results of the calculations, and are input to the threshold circuit 1.9.
閾値回路19の出力信号は出力レジスタ回路18に入力
される。一方、選択制御回路IOからのアドレス信号に
よって選択された出力端子45t〜45.に出力レジス
タ回路18によって出力されるとともに出力レジスタ回
路18は出力信号を保持する。The output signal of the threshold circuit 19 is input to the output register circuit 18. On the other hand, output terminals 45t to 45. selected by the address signal from the selection control circuit IO. The signal is output by the output register circuit 18, and the output register circuit 18 holds the output signal.
このように、入力端子40+に+11〜40□の入力に
対する演算回路か殆ど省略されている。In this way, most of the arithmetic circuits for inputs from +11 to 40□ to the input terminal 40+ are omitted.
第2図は本発明の他の実施例の構成図を示す。FIG. 2 shows a block diagram of another embodiment of the invention.
同図中、第4図、第1図と同一構成部分には同一符号を
付し、その説明を省略する。In the figure, the same components as in FIGS. 4 and 1 are denoted by the same reference numerals, and their explanations will be omitted.
本実施例の集中演算部35は第1の実施例の集中演算部
20の構成と異なっている。21はスイッチ、22.2
4はスイッチ回路、26は係数演算部、28は累積用の
レジスタ回路(ACC)、29は加算回路、33.〜3
3..は係数データ用のレジスタ回路である。The configuration of the centralized calculation section 35 of this embodiment is different from that of the centralized calculation section 20 of the first embodiment. 21 is a switch, 22.2
4 is a switch circuit, 26 is a coefficient calculation unit, 28 is an accumulation register circuit (ACC), 29 is an adder circuit, 33. ~3
3. .. is a register circuit for coefficient data.
本実施例では集中演算部35の構成を第2図に示す如く
、第1図の集中演算部2oの係数演算回路I5と加算回
路17の回路規模をさらに低減するために累積用のレジ
スタ回路(ACC)28とスイッチ回路22.24によ
って一組の係数演算回路26と加算回路29で入力端子
40+に+11〜40、の入力信号の演算を実行てきる
ように構成されている。In this embodiment, the configuration of the centralized calculation unit 35 is shown in FIG. 2. In order to further reduce the circuit scale of the coefficient calculation circuit I5 and the adder circuit 17 of the centralized calculation unit 2o in FIG. ACC) 28 and switch circuits 22 and 24, a set of coefficient calculation circuits 26 and addition circuits 29 are configured to perform calculations on input signals from +11 to +40 to input terminal 40+.
つまり、第2実施例では係数演算回路26の2つの入力
に夫々スイッチ回路22.24を設け、入力端子40+
に+11〜40□からの入力信号と係数RAM回路12
からの係数とを切り換えている。That is, in the second embodiment, switch circuits 22 and 24 are provided at the two inputs of the coefficient calculation circuit 26, respectively, and the input terminals 40+
Input signals from +11 to 40□ and coefficient RAM circuit 12
The coefficients from
さらに、並列演算部100で累積された累積ブタ信号を
選択制御回路IOより取り出してスイッチ21を図中、
左に倒してACCレジスタ回路28に入力する。スイッ
チ21は一度累積データを取り出した後は図中、右に倒
される。切り換えられた係数と入力信号を係数演算回路
26て演算し、その値をレジスタ回路28からの値とを
加算回路29で加算し、閾値回路19に入力し、出力レ
ジスタ回路18を経て出方端子451〜45゜に出力さ
れる。Further, the cumulative pig signal accumulated by the parallel calculation unit 100 is taken out from the selection control circuit IO, and the switch 21 is activated as shown in the figure.
Tilt it to the left and input it to the ACC register circuit 28. Once the accumulated data is taken out, the switch 21 is turned to the right in the figure. The coefficient calculation circuit 26 calculates the switched coefficient and the input signal, and the added value is added to the value from the register circuit 28 in the addition circuit 29. The result is input to the threshold circuit 19, and then sent to the output terminal via the output register circuit 18. It is output at 451 to 45 degrees.
これにより、入力端子4(lfk+11〜40.の入力
に対する演算回路規模は第1の実施例よりさらに低減さ
れる。As a result, the scale of the arithmetic circuit for the inputs to the input terminals 4 (lfk+11 to 40.) is further reduced compared to the first embodiment.
第3図は累積回路の動作を示す。従来の累積回路の場合
に対応して、係数演算回路42と加算回路43と係数の
メモリ回路41を1個のセルと考える。第3図は入力端
子数nが8個、出カ端子数mカ月6個の場合について各
セルの演算動作を示すものである。FIG. 3 shows the operation of the accumulator circuit. Corresponding to the conventional accumulation circuit, the coefficient calculation circuit 42, addition circuit 43, and coefficient memory circuit 41 are considered as one cell. FIG. 3 shows the calculation operation of each cell in the case where the number of input terminals n is 8 and the number of output terminals m is 6.
係数演算回路42はパターン認識等では一般には入力信
号と係数の間の誤差や距離を計算している。その場合に
は係数演算回路42の出力は正数である。一方、閾値回
路19は第5図に示したように飽和特性をもっている。The coefficient calculating circuit 42 generally calculates the error or distance between an input signal and a coefficient in pattern recognition or the like. In that case, the output of the coefficient calculation circuit 42 is a positive number. On the other hand, the threshold circuit 19 has saturation characteristics as shown in FIG.
飽和特性では入力レベルがある値以上では出力レベルが
変化しないようになる。つまり、出方レベルが飽和レベ
ルに達すると、それ以上に入力レベルか大きくなっても
出力レベルは変化しなくなる。従って、正数の累積演算
と閾値回路19の組み合わせては、累積結果は単調増加
するだけなのて、累積途中で出力レベルか飽和レベルま
で達したら、それ以後の演算を省略することが可能であ
る。With saturation characteristics, the output level does not change when the input level exceeds a certain value. In other words, when the output level reaches the saturation level, the output level will not change even if the input level increases beyond that level. Therefore, when a positive number cumulative operation is combined with the threshold circuit 19, the cumulative result only increases monotonically, and if the output level or saturation level is reached during the accumulation, subsequent calculations can be omitted. .
第3図は演算の必要なセル30と演算の省略か必要なセ
ル32を示している。同図ではすべてのセルについて演
算を実行しなければならない列は8列目の1列だけであ
る。このとき、入力端子IN1〜IN4の行は演算の必
要なセルが多いが入力端子IN5〜INSの行は8列目
を除いてすべて演算の不要なセルとなっている。このた
め、入力端子INI〜IN4の行については第1図、第
2図に示す並列演算部100で演算を行い、一方、入力
端子IN5〜lN8の行については集中演算部20.3
5て演算を行うことになる。FIG. 3 shows cells 30 that require calculations and cells 32 that require calculations to be omitted or required. In the figure, the only column in which calculations must be performed for all cells is the eighth column. At this time, the rows of input terminals IN1 to IN4 have many cells that require calculations, but the rows of input terminals IN5 to INS have cells that do not require calculations, except for the eighth column. Therefore, for the rows of input terminals INI to IN4, calculations are performed in the parallel calculation unit 100 shown in FIGS. 1 and 2, while for the rows of input terminals IN5 to IN8, the centralized calculation unit 20.
5 and perform the calculation.
一般にパターン認識なとでは、入力に対していずれか1
個の出力が反応して入カバターンをカテゴリーに分類す
るように設計されている。Generally, in pattern recognition, one of the
The outputs are designed to react and classify the input patterns into categories.
ニューラルネットワーク回路でも少数の出力か反応する
たけて殆との出力は反応しない。従って、第3図に示し
たような動作は多くの応用において見られる特性である
。同図の例では、入力端子INS以降は8列目の演算回
路42しか演算は必要なく、その他の大部分の演算回路
については省略できることが明らかである。演算の必要
なセル30と演算の不要なセル32の配置は入力信号に
よって変化するか、とのような入力信号に対しても不要
なセルか第3図に近い形で分布するため、本発明の累積
回路のように演算回路を省略しても従来の累積回路と同
様の演算が実行できる。Even in neural network circuits, only a small number of outputs react, and most outputs do not. Therefore, operation as shown in FIG. 3 is a characteristic found in many applications. In the example shown in the figure, it is clear that only the calculation circuit 42 in the 8th column is required to perform calculations after the input terminal INS, and most of the other calculation circuits can be omitted. Does the arrangement of cells 30 that require calculations and cells 32 that do not require calculations change depending on the input signal?Since unnecessary cells are distributed in a form similar to that shown in FIG. 3 even in response to input signals, the present invention Even if the arithmetic circuit is omitted, the same arithmetic operations as in the conventional accumulator circuit can be performed.
上記のように本発明によれば、従来の累積回路に比較し
て演算速度を殆ど低下させずに、回路規模は大幅に低減
できる。また、演算回路の省略に伴い、消費電力も同様
に大幅に低減できる。As described above, according to the present invention, the circuit scale can be significantly reduced with almost no reduction in calculation speed compared to conventional accumulation circuits. Moreover, with the omission of the arithmetic circuit, power consumption can also be significantly reduced.
さらにパターン認識回路やニューラルネットワク回路を
ハード化するとき、必要な単位回路数は応用によって異
なるか、−船釣には回路数が大きいほと処理能力は向上
する。そのため、多数の単位回路を搭載したLSIの実
現か期待されている。しかし、チップサイズの制限によ
って1チツプに搭載できる回路規模は限られているため
、放熱や実装の問題から1チツプで消費できる電力にも
制限かある。したかって、LSIか実用的な性能を発揮
するために、回路規模と消費電力の低減が最も重要な課
題となっている点において本発明は実用上極めて有用で
ある。Furthermore, when implementing hardware for pattern recognition circuits and neural network circuits, the number of unit circuits required varies depending on the application; for boat fishing, the larger the number of circuits, the better the processing power. Therefore, it is expected that LSIs equipped with a large number of unit circuits will be realized. However, due to chip size limitations, there is a limit to the amount of circuitry that can be mounted on a single chip, and there are also limits to the amount of power that can be consumed by a single chip due to heat dissipation and mounting issues. Therefore, the present invention is extremely useful in practice in that reducing circuit scale and power consumption are the most important issues in order for an LSI to exhibit practical performance.
第1図は本発明の一実施例の回路構成図、第2図は本発
明の他の実施例の回路構成図、第3図は累積回路の動作
を示す図、
第4図は従来の累積回路の一例の構成図、第5図は閾値
回路の伝達特性を示す図である。
10・・・選択制御回路、12・・・係数RAM回路、
14、〜14.k・・・レジスタ回路、15.〜15、
、.26・・・係数演算回路、17.〜+7..・・・
加算回路、18・・・出力レジスタ回路、19・・・閾
値回路、20・・・集中演算部、40゜〜40、.40
□や、、〜40..・・・入力端子、42.。
〜42□、43.〜43□−z 45+〜45゜・
・・出力端子。
特許出願人 日本電信電話株式会社閾値回路の伝達
特性
第
図
(C)シグモイド関数形Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is a circuit diagram of another embodiment of the invention, Fig. 3 is a diagram showing the operation of an accumulation circuit, and Fig. 4 is a diagram of a conventional accumulation circuit. FIG. 5, which is a configuration diagram of an example of the circuit, is a diagram showing the transfer characteristics of the threshold circuit. 10... Selection control circuit, 12... Coefficient RAM circuit,
14, ~14. k...Register circuit, 15. ~15,
,.. 26... Coefficient calculation circuit, 17. ~+7. .. ...
Addition circuit, 18... Output register circuit, 19... Threshold circuit, 20... Centralized calculation unit, 40° to 40, . 40
□Ya...~40. .. ...input terminal, 42. . ~42□, 43. ~43□−z 45+~45°・
...Output terminal. Patent applicant Nippon Telegraph and Telephone Corporation Transfer characteristic diagram of threshold circuit (C) Sigmoid function form
Claims (1)
1より大きい整数)個の出力端子を持ち、独自のn個の
係数で構成される係数組をm組持ち、全ての係数組につ
いて、i(iは1からnまでの整数)番目の係数とi番
目の入力端子信号間の差や距離あるいは係数による荷重
値などを係数演算回路により単一極性の係数演算値とし
て求め、1からnまでの係数演算値を全て累積し、この
累積結果を閾値処理して得られる変換値を出力信号とす
る一連の演算を行う場合において、 1からk(kは1以上でnより小さい整数)番目の入力
端子信号に対しては前記係数演算値を求めるために1個
の係数にそれぞれ専用の第1の係数演算回路と、1から
k番目の該係数演算回路の出力の累積を行うための第1
の加算回路を有する回路をm組並列に配置し、 m個の累積の途中結果と閾値回路の飽和レベルを比較し
て残りの入力端子からの入力に対する演算を続行するか
を判定し、演算の続行が必要な累積の途中結果を出力す
る選択制御回路を備え、演算の続行が必要な入力に対し
、1個あるいは数個の第2の係数演算回路と第2の加算
回路を共通に使用して入力端子信号と係数値を切り換え
て累積演算を続行し、 1からn番目の入力端子に対する累積結果を閾値回路に
入力し、該閾値回路の処理結果を出力端子に出力するこ
とを特徴とする累積回路。[Claims] A coefficient set having n (n is an integer greater than 1) input terminals and m (m is an integer greater than 1) output terminals, and is composed of unique n coefficients. There are m sets, and for all coefficient sets, the difference or distance between the i-th coefficient and the i-th input terminal signal, or the weight value due to the coefficient, etc., is calculated using a coefficient calculation circuit with a single polarity. When performing a series of calculations in which all the coefficient calculation values from 1 to n are accumulated, and the output signal is the converted value obtained by thresholding this cumulative result, from 1 to k (k is an integer greater than or equal to 1 and less than n) For the input terminal signal, a first coefficient calculation circuit dedicated to each coefficient is used to obtain the coefficient calculation value, and a first coefficient calculation circuit dedicated to each coefficient is used to calculate the coefficient calculation value from 1 to k. The first step is to accumulate the output of the circuit.
m sets of circuits having adder circuits are arranged in parallel, and the intermediate results of m accumulations are compared with the saturation level of the threshold circuit to determine whether to continue the operation on the inputs from the remaining input terminals, and It is equipped with a selection control circuit that outputs an intermediate result of accumulation that requires continuation, and uses one or several second coefficient calculation circuits and second addition circuits in common for inputs that require continuation of calculation. continues the cumulative calculation by switching the input terminal signal and the coefficient value, inputting the cumulative results for the 1st to nth input terminals to a threshold circuit, and outputting the processing results of the threshold circuit to the output terminal. Accumulation circuit.
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2232914A JPH04112362A (en) | 1990-09-03 | 1990-09-03 | Accumulation circuit |
US07/727,065 US5166539A (en) | 1990-07-09 | 1991-07-08 | Neural network circuit |
KR1019910011546A KR950001601B1 (en) | 1990-07-09 | 1991-07-08 | Neural network circuit |
DE69119172T DE69119172T2 (en) | 1990-07-09 | 1991-07-09 | Neural network circuit |
EP91111435A EP0477486B1 (en) | 1990-07-09 | 1991-07-09 | Neural network circuit |
US07/909,993 US5353383A (en) | 1990-07-09 | 1992-07-07 | Neural network circuit |
US08/266,691 US5467429A (en) | 1990-07-09 | 1994-06-28 | Neural network circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2232914A JPH04112362A (en) | 1990-09-03 | 1990-09-03 | Accumulation circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04112362A true JPH04112362A (en) | 1992-04-14 |
Family
ID=16946819
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2232914A Pending JPH04112362A (en) | 1990-07-09 | 1990-09-03 | Accumulation circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04112362A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10187648A (en) * | 1996-12-19 | 1998-07-21 | Nec Corp | Neural unit operation system and its device |
JP2017151604A (en) * | 2016-02-23 | 2017-08-31 | 株式会社デンソー | Arithmetic processing unit |
CN108345935A (en) * | 2017-01-25 | 2018-07-31 | 株式会社东芝 | Product and arithmetic unit, network element and network equipment |
-
1990
- 1990-09-03 JP JP2232914A patent/JPH04112362A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10187648A (en) * | 1996-12-19 | 1998-07-21 | Nec Corp | Neural unit operation system and its device |
JP2017151604A (en) * | 2016-02-23 | 2017-08-31 | 株式会社デンソー | Arithmetic processing unit |
CN108345935A (en) * | 2017-01-25 | 2018-07-31 | 株式会社东芝 | Product and arithmetic unit, network element and network equipment |
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