JPH04107933A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH04107933A
JPH04107933A JP2227217A JP22721790A JPH04107933A JP H04107933 A JPH04107933 A JP H04107933A JP 2227217 A JP2227217 A JP 2227217A JP 22721790 A JP22721790 A JP 22721790A JP H04107933 A JPH04107933 A JP H04107933A
Authority
JP
Japan
Prior art keywords
lead frame
resin
semiconductor chip
semiconductor device
stage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2227217A
Other languages
Japanese (ja)
Inventor
Chitoshi Ando
安藤　千利
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyushu Fujitsu Electronics Ltd
Fujitsu Ltd
Original Assignee
Kyushu Fujitsu Electronics Ltd
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyushu Fujitsu Electronics Ltd, Fujitsu Ltd filed Critical Kyushu Fujitsu Electronics Ltd
Priority to JP2227217A priority Critical patent/JPH04107933A/en
Publication of JPH04107933A publication Critical patent/JPH04107933A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector

Abstract

PURPOSE:To enhance the adhesion of resin to a lead frame by applying far- ultraviolet radiation to the lead frame to remove oxide from its surface, before a semiconductor chip is molded with resin. CONSTITUTION:A semiconductor chip 6 is bonded to a stage 2 on a lead frame 1, and wire bonding is performed. A mask 12 is used to apply far-ultraviolet radiation selectively to the areas having no aluminum plating on the lead frame to remove copper oxide 9. The chip is molded with resin such as epoxy, and the resin is post-cured. Unwanted parts of the lead frame are cut off, and leads are formed and plated. According to this method, the adhesion of resin to the lead frame is enhanced, and it is possible to prevent the cracking of the mold due to the vaporization of moisture.

Description

【発明の詳細な説明】 ［概要］ 半導体チップをリードフレームに接着して樹脂で封止し
てなる半導体装置の製造方法に関し、リードフレームと
封止樹脂との密着性を強め、吸収された水分の気化膨張
によるクラックの発生を防止することを目的とし、 半導体チップを前記樹脂で封止する前に、リードフレー
ムに遠紫外線を照射し７て、リードフレームの表面に形
成されている酸化物層を除去するようにする。[Detailed Description of the Invention] [Summary] A method for manufacturing a semiconductor device in which a semiconductor chip is bonded to a lead frame and sealed with a resin, the method involves strengthening the adhesion between the lead frame and the sealing resin, and reducing absorbed moisture. In order to prevent the occurrence of cracks due to vaporization expansion, the lead frame is irradiated with deep ultraviolet rays before the semiconductor chip is sealed with the resin to remove the oxide layer formed on the surface of the lead frame. Try to remove it.

［産業上の利用分野］ 本発明は半導体チップをリードフレームに接着して樹脂
で封止してなる半導体装置の製造方法に関する。[Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device in which a semiconductor chip is bonded to a lead frame and sealed with resin.

［従来の技術］ 従来、半導体チップをリードフレームに接着して樹脂で
封止してなる半導体装置の製造方法として第３図にその
工程図を示すようなものが提案されている。[Prior Art] Conventionally, a method of manufacturing a semiconductor device in which a semiconductor chip is bonded to a lead frame and sealed with resin has been proposed, the process diagram of which is shown in FIG.

この方法によれば、まず、第３図Ａに示すように、リー
ドフレームｌを用意する。なお、図中、２は半導体チッ
プを接着するステージ（アイランド、ダイパッド）、３
は外部端子たるリード、４はポンディングパッドの部分
を示している。また、このリードフレーム１は銅（Ｃｕ
）で形成され、第４図にその平面図を示すように、ステ
ージ２の部分及びポンディングパッド４の部分にアルミ
ニウム（ＡＩ）２６をメツキされている。According to this method, first, as shown in FIG. 3A, a lead frame 1 is prepared. In addition, in the figure, 2 is a stage (island, die pad) for bonding semiconductor chips, 3 is a stage for bonding semiconductor chips;
4 indicates a lead serving as an external terminal, and 4 indicates a bonding pad. Moreover, this lead frame 1 is made of copper (Cu).
), and as shown in a plan view in FIG. 4, the stage 2 portion and the bonding pad 4 portion are plated with aluminum (AI) 26.

次に、第３図Ｂに示すように、ステージ２に銀ペースト
５を塗布した後、第３図Ｃに示すように、半導体チップ
６をステージ２に接着する。Next, as shown in FIG. 3B, a silver paste 5 is applied to the stage 2, and then a semiconductor chip 6 is bonded to the stage 2, as shown in FIG. 3C.

次に、全体を加熱し、銀ペースト５の溶剤を蒸発させた
後、第３図りに示すように、金線７を使用したワイヤボ
ンディングを行う。Next, the whole is heated to evaporate the solvent of the silver paste 5, and then wire bonding is performed using a gold wire 7, as shown in the third diagram.

次に、第３図Ｅに示すように、エポキシ樹脂等の樹脂８
を使用して半導体チップ６を封止した後、ボストキュア
を行い、即ち、所定温度の下に所定時間数１して樹脂８
を硬化させ、その後、リードフレーム１の不必要な部分
の切断、リード３の部分の折り曲げ、メツキ等の工程を
経て、第３図Ｆに示すように、半導体チップ６をリード
フレーム１に接着して樹脂８で封止してなる半導体装置
を得ることができる。Next, as shown in FIG. 3E, a resin 8 such as epoxy resin
After sealing the semiconductor chip 6 using the resin, a boss cure is performed, that is, the resin 8 is sealed at a predetermined temperature for a predetermined number of hours.
After that, through steps such as cutting unnecessary parts of the lead frame 1, bending the leads 3, and plating, the semiconductor chip 6 is bonded to the lead frame 1 as shown in FIG. A semiconductor device sealed with resin 8 can be obtained.

［発明が解決しようとする課題］ しかしながら、かかる従来の半導体装置の製造方法にお
いては、半導体チップ６をステージ２に接着した後、銀
ペースト５中の溶剤を蒸発させる工程やワイヤボンディ
ングを行う工程で、リードフレーム１に熱が加わるため
、第５図Ａ、Ｂに示すように、リードフレーム１のアル
ミニウムメツキがされていない部分に酸化銅９が形成さ
れてしまう。このなめ、リードフレーム１と樹脂８との
密着性が劣化し、湿気の吸収により、ステージ２の裏面
の樹脂部分にクラックが発生してしまう場合があるとい
う問題点があった。なお、第６図は、吸湿によるクラッ
クの発生過程を示す図であって、第６図Ａに示すように
、パッケージに水分が吸収されると、第６図Ｂに示すよ
うに、吸収された水分が気化ｍ張し、ステージ２の裏面
に、部分的に樹脂８の剥離部分１０が発生する。そして
、第６図Ｃに示すように、ステージ２の裏面の樹脂８の
剥離部分１０が大きくなると、第６図りに示すように、
樹脂８にクラック１１が発生してしまう。[Problems to be Solved by the Invention] However, in such a conventional semiconductor device manufacturing method, after bonding the semiconductor chip 6 to the stage 2, there are no steps such as evaporating the solvent in the silver paste 5 or performing wire bonding. Since heat is applied to the lead frame 1, copper oxide 9 is formed on the portions of the lead frame 1 that are not plated with aluminum, as shown in FIGS. 5A and 5B. This licking deteriorates the adhesion between the lead frame 1 and the resin 8, and there is a problem in that cracks may occur in the resin portion on the back surface of the stage 2 due to absorption of moisture. FIG. 6 is a diagram showing the process of crack generation due to moisture absorption. As shown in FIG. 6A, when moisture is absorbed into the package, as shown in FIG. 6B, the moisture is absorbed. The moisture evaporates and a peeled portion 10 of the resin 8 is generated on the back surface of the stage 2. As shown in FIG. 6C, when the peeled part 10 of the resin 8 on the back surface of the stage 2 becomes larger, as shown in FIG.
Cracks 11 occur in the resin 8.

特に、近年、半導体チップ６の大型化や、実装密度の向
上を図ろうとすることから、樹脂８の膜厚を薄く形成す
る傾向にあり、この点からしても、かかる吸湿によるク
ラックの発生は重要な問題となっており、その対策が急
がれていた。In particular, in recent years, as semiconductor chips 6 have become larger and the packaging density has been increased, there has been a tendency to make the resin 8 thinner. This has become an important problem, and countermeasures are urgently needed.

本発明は、かかる点に鑑み、リードフレームと封止樹脂
との密着性を強め、吸収された水分の気化膨張によるク
ラックの発生を防止することができるようにした半導体
装置の製造方法を提供することを目的とする。In view of this, the present invention provides a method for manufacturing a semiconductor device that strengthens the adhesion between a lead frame and a sealing resin and prevents the occurrence of cracks due to evaporative expansion of absorbed moisture. The purpose is to

「課題を解決するための手段］ 本発明による半導体装置の製造方法は、半導体チップを
リードフレームに接着して樹脂で封止してなる半導体装
置の製造方法において、前記半導体チップを前記樹脂で
封止する前に、前記リードフレームに遠紫外線を照射し
て、前記リードフレームの表面に形成されている酸化物
層を除去する工程を設けるというものである。"Means for Solving the Problems" A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device in which a semiconductor chip is bonded to a lead frame and sealed with a resin, in which the semiconductor chip is sealed with the resin. Before stopping, there is a step of irradiating the lead frame with deep ultraviolet rays to remove an oxide layer formed on the surface of the lead frame.

［作用］ 本発明によれば、リードフレームの表面に形成されてい
る酸化物層を除去した後、半導体チップの樹脂封止が行
われるので、リードフレームと樹脂との密着性を高める
ことができる。[Function] According to the present invention, the resin sealing of the semiconductor chip is performed after removing the oxide layer formed on the surface of the lead frame, so it is possible to improve the adhesion between the lead frame and the resin. .

［実施例］ 以下、第１図及び第２図を参照して、本発明の一実施例
につき説明する。なお、第１図において第３図に対応す
る部分には同一符号を付し、その重複説明は省略する。[Example] Hereinafter, an example of the present invention will be described with reference to FIGS. 1 and 2. In FIG. 1, parts corresponding to those in FIG. 3 are denoted by the same reference numerals, and redundant explanation thereof will be omitted.

第１図は本発明による半導体装置の製造方法の一実施例
を示す図であって、本実施例においては、第１図Ａ〜第
１図りに示すように、第３図Ａ〜第３図りに示すと同様
の工程を実行して、リードフレーム１のステージ２上に
半導体チップ６を接着し、ワイヤボンディングを行う。FIG. 1 is a diagram showing an embodiment of a method for manufacturing a semiconductor device according to the present invention, and in this embodiment, as shown in FIG. 1, the semiconductor chip 6 is bonded onto the stage 2 of the lead frame 1 and wire bonded.

次に、第１図Ｅに示すように、マスク１２を使用して、
半導体チップ６の表面及びリードフレーム１のポンディ
ングパッド４の部分を除き、即ち、リードフレーム１の
アルミニウムメツキがされていない部分にのみ遠紫外線
を照射し、この部分に形成されている酸化＠９を除去す
る。なお、この遠紫外線の照射は、波長１０７〜３５３
．３ｎｍのエキシマレーザを５０Ｊ／ｃｍ２の照射エネ
ルギーで照射して行うことが好適である。Next, as shown in FIG. 1E, using the mask 12,
Excluding the surface of the semiconductor chip 6 and the portion of the bonding pad 4 of the lead frame 1, that is, only the portion of the lead frame 1 that is not plated with aluminum is irradiated with deep ultraviolet rays to remove the oxidation @ 9 formed on this portion. remove. Note that this far ultraviolet irradiation has a wavelength of 107 to 353
．． It is preferable to irradiate with a 3 nm excimer laser with an irradiation energy of 50 J/cm 2 .

次に、第１図Ｆに示すように、エポキシ樹脂等の樹脂８
を使用して半導体チップ６を封止した後、ボストキュア
を行い、即ち、所定温度の下に所定時間放置して樹脂８
を硬化させ、その後、リードフレーム１の不必要な部分
の切断、リード３の部分の折り曲げ、メツキ等の工程を
経て、第１図Ｇに示すように、半導体チップ６をリード
フレーム１に接着して樹脂８で封止してなる半導体装置
を得ることができる。Next, as shown in FIG. 1F, resin 8 such as epoxy resin
After sealing the semiconductor chip 6 using the resin, a boss cure is performed, that is, the resin 8 is left at a predetermined temperature for a predetermined time.
After that, through steps such as cutting unnecessary parts of the lead frame 1, bending the leads 3, and plating, the semiconductor chip 6 is bonded to the lead frame 1 as shown in FIG. A semiconductor device sealed with resin 8 can be obtained.

第２図は、本実施例において、遠紫外線を照射する場合
に使用することができる遠紫外線照射装置の一例の要部
を示す図である。FIG. 2 is a diagram showing essential parts of an example of a far ultraviolet irradiation device that can be used when irradiating far ultraviolet rays in this embodiment.

図中、１３は波長２４８ｎｍのＫｒ（クリプトン）Ｆ（
フッ素）レーザを発生するＫｒＦレーザ発生部、１４は
ＫｒＦレーザ発生部１３から発生したＫｒＦレーザ、１
５．１６．１７はミラー、１８はＫｒＦレーザ１４の通
過を制御するシャッタ、１９はシャッタ１５の開閉を制
御するシャッタコントローラ、２０は照射光学系、２１
はＫｒＦレーザ１４が半導体チップ６やリードフレーム
１のポンディングパッド４の部分に照射しないようにす
るためのマスク、２２は投影レンズ系、２３は半導体チ
ップ６を接着したリードフレームｌを搭載するためのス
テージ、２４はステージ２３のＸＹ力方向移動を制御す
るステージコントローラ、２５は真空吸引器であって、
この遠紫外線照射装置は、ステージ２３上に搭載された
リードフレーム１をいわゆるステップ・アンド・リピー
ト方式で露光しようとするものである。In the figure, 13 is Kr (krypton) F (with a wavelength of 248 nm).
14 is a KrF laser generated from the KrF laser generator 13;
5.16.17 is a mirror, 18 is a shutter that controls passage of the KrF laser 14, 19 is a shutter controller that controls opening and closing of the shutter 15, 20 is an irradiation optical system, 21
2 is a mask for preventing the KrF laser 14 from irradiating the semiconductor chip 6 and the bonding pad 4 of the lead frame 1, 22 is a projection lens system, and 23 is for mounting the lead frame l to which the semiconductor chip 6 is bonded. 24 is a stage controller that controls the movement of the stage 23 in the XY force direction, 25 is a vacuum suction device,
This deep ultraviolet irradiation device is intended to expose the lead frame 1 mounted on the stage 23 in a so-called step-and-repeat method.

なお、このＫｒＦレーザ１４等、遠紫外線の露光は、ス
テップ・アンド・リピート露光の他に、−括露光やスキ
ャン露光でも良く、このスキャン露光の場合はレーザス
キャン方式でも、ステージスキャン方式でも良い。Note that the exposure to far ultraviolet rays such as the KrF laser 14 may be performed by -block exposure or scan exposure in addition to step-and-repeat exposure, and in the case of this scan exposure, a laser scan method or a stage scan method may be used.

かかる本実施例によれば、リードフレーム１のステージ
２上に半導体チップ６を接着し、ワイヤボンディングを
行った後、樹脂８による封止を行う前に、リードフレー
ム１のアルミニウムメツキがされていない部分に遠紫外
線を照射し、この部分に形成されている酸化銅９を除去
するようにしているので、リードフレーム１と樹脂８と
の密着性を高めることができる。したがって、吸収され
た水分の気化膨張によるクラックの発生を効果的に防止
することができる。According to this embodiment, after bonding the semiconductor chip 6 on the stage 2 of the lead frame 1 and performing wire bonding, the aluminum plating of the lead frame 1 is not performed before sealing with the resin 8. Since the portion is irradiated with deep ultraviolet rays to remove the copper oxide 9 formed in this portion, the adhesion between the lead frame 1 and the resin 8 can be improved. Therefore, generation of cracks due to vaporization and expansion of absorbed moisture can be effectively prevented.

なお、ここに、アルゴン（Ａｒ）等のスパッタによって
酸化銅９を除去する方法が考えられるが、この方法では
、半導体チップ６に対するスパッタを避けることができ
ず、半導体チップ６の破壊を招くため、結局、この方法
は採用することができない。Here, a method of removing the copper oxide 9 by sputtering with argon (Ar) or the like may be considered, but with this method, sputtering on the semiconductor chip 6 cannot be avoided, resulting in destruction of the semiconductor chip 6. In the end, this method cannot be adopted.

［発明の効果コ 以上のように、本発明によれば、半導体チップを樹脂で
封止する前に、リードフレームに遠紫外線を照射して、
リードフレームの表面に形成されている酸化物層を除去
するという方法を採用したことにより、即ち、リードフ
レームの表面に形成されている酸化物層を除去した後、
半導体チップの樹脂封止を行うとしたことにより、リー
ドフレームと封止樹脂との密着性を高めることができる
ので、吸収された水分の気化膨張によるクラックの発生
を防止することができる。[Effects of the Invention] As described above, according to the present invention, before sealing the semiconductor chip with resin, the lead frame is irradiated with deep ultraviolet rays,
By adopting a method of removing the oxide layer formed on the surface of the lead frame, that is, after removing the oxide layer formed on the surface of the lead frame,
By sealing the semiconductor chip with resin, it is possible to improve the adhesion between the lead frame and the sealing resin, thereby preventing the occurrence of cracks due to vaporization and expansion of absorbed moisture.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明による半導体装置の製造方法の一実施例
を示す図、 第２図は本発明の一実施例で使用される遠紫外線照射装
置の一例の要部を示す図、 第３図は従来の半導体装置の製造方法の一例を示す図、 第４図は第３図従来例で使用しているリードフレームを
示す平面図、 第５図は第３図従来例の半導体装置の製造方法が有して
いる問題点を説明するための図、第６図は吸湿によるク
ラックの発生過程を示す図である。 １・・・リードフレーム ６・・・半導体チップ ８・・・樹脂 ９・・・酸化銅 （Ａ）　　　　　　　４　　　　　　　４（Ｂ） （Ｃ） 本発明による半導体装置の製造方法の一実施例第１図 遠紫外線 遠紫外線 本発明による半導体装置の製造方法の一実施例第１図 本発明の一実施例で使用される 遠紫外線照射装置の一例の要部 第２図 （Ａ）　　　　　　４　　　　　　４ 従来の半導体装置の製造方法の一例 従来の半導体装置の製造方法の一例 第３図従来例で使用しているリードフレームの平面図第
４図 （Ａ） が有している問題点を説明するための図第５図FIG. 1 is a diagram showing an embodiment of a method for manufacturing a semiconductor device according to the present invention, FIG. 2 is a diagram showing essential parts of an example of a far ultraviolet irradiation device used in an embodiment of the present invention, and FIG. 4 is a plan view showing a lead frame used in the conventional example shown in FIG. 3. FIG. 5 is a diagram showing an example of the conventional method for manufacturing a semiconductor device shown in FIG. 3. FIG. 6 is a diagram illustrating the process of crack generation due to moisture absorption. 1...Lead frame 6...Semiconductor chip 8...Resin 9...Copper oxide (A) 4 4 (B) (C) An embodiment of the method for manufacturing a semiconductor device according to the present invention. Ultraviolet deep ultraviolet rays An embodiment of the method for manufacturing a semiconductor device according to the present invention FIG. 1 Main part of an example of a far ultraviolet irradiation device used in an embodiment of the present invention FIG. 2 (A) 4 4 Conventional semiconductor device An example of a manufacturing method FIG. 3 An example of a conventional semiconductor device manufacturing method FIG. 4 A plan view of a lead frame used in the conventional example FIG. 4 A diagram for explaining the problems of (A) FIG.

Claims (1)

【特許請求の範囲】[Claims] 半導体チップをリードフレームに接着して樹脂で封止し
てなる半導体装置の製造方法において、前記半導体チッ
プを前記樹脂で封止する前に、前記リードフレームに遠
紫外線を照射して、前記リードフレームの表面に形成さ
れている酸化物層を除去することを特徴とする半導体装
置の製造方法。In a method of manufacturing a semiconductor device in which a semiconductor chip is bonded to a lead frame and sealed with a resin, before the semiconductor chip is sealed with the resin, the lead frame is irradiated with deep ultraviolet rays to remove the lead frame. 1. A method of manufacturing a semiconductor device, comprising removing an oxide layer formed on a surface of the semiconductor device.
JP2227217A 1990-08-28 1990-08-28 Manufacture of semiconductor device Pending JPH04107933A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2227217A JPH04107933A (en) 1990-08-28 1990-08-28 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2227217A JPH04107933A (en) 1990-08-28 1990-08-28 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH04107933A true JPH04107933A (en) 1992-04-09

Family

ID=16857334

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2227217A Pending JPH04107933A (en) 1990-08-28 1990-08-28 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH04107933A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000150551A (en) * 1998-11-11 2000-05-30 Orc Mfg Co Ltd Mechanism and method for surface treating lead frame
JP2012523685A (en) * 2009-04-08 2012-10-04 タイコ エレクトロニクス アンプ ゲゼルシャフト ミット ベシュレンクテル ハウツンク Conductor grid for electronic housing and manufacturing method
US8298869B2 (en) * 2008-03-21 2012-10-30 Sumitomo Chemical Company, Limited Resin package and production method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000150551A (en) * 1998-11-11 2000-05-30 Orc Mfg Co Ltd Mechanism and method for surface treating lead frame
US8298869B2 (en) * 2008-03-21 2012-10-30 Sumitomo Chemical Company, Limited Resin package and production method thereof
JP2012523685A (en) * 2009-04-08 2012-10-04 タイコ エレクトロニクス アンプ ゲゼルシャフト ミット ベシュレンクテル ハウツンク Conductor grid for electronic housing and manufacturing method

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