JPH04104520A - Phase lock loop - Google Patents

Abstract

PURPOSE:To always synchronize phases by detecting a phase difference 3/2pi between an input signal and the output signal of a voltage controlled oscillator(VCO) and inverting the output of the VCO by a two-input signal switch as a switch with a 1/2 frequency divider. CONSTITUTION:The phase difference 3/2pi between an input signal (a) and the output signal of a VCO 3 is detected, and the output of the VCO 3 is inverted by a two-input signal switch 5 as the switch with the 1/2 frequency divider. When the input signal frequency is lower than the VCO output frequency, the DC component of the output of a phase comparator 1 is always in the negative level, and feedback is applied in such direction that the frequency of the output signal (b) of the VCO 3 is reduced, and the input signal (a) and the output signal (b) of the VCO 3 are synchronized. When the frequency of the input signal (a) is higher than the frequency of the output signal (b) of the VCO 3, the DC component of the output of the phase comparator 1 is always in the positive level, and feedback is applied in such direction that the frequency of the output signal (b) of the VCO 3 is raised, and they are synchronized. Thus, phases are always synchronized.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は位相同期回路（以下、ＰＬＬ回路と略称する）
に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a phase-locked circuit (hereinafter abbreviated as PLL circuit).
It is related to.

〔従来の技術〕[Conventional technology]

従来のＰＬＬ回路の一例を第４図に示し説明する。 An example of a conventional PLL circuit is shown in FIG. 4 and will be described.

図において、２１は入力信号ｌを入力とする位相比較器
、２２はこの位相比較器２１からの電圧ｊを入力とする
ローパスフィルタであるループフィルタ、２３はこのル
ープフィルタ２２かう出力される直流成分ｋＫよシ発振
周波数が制御される電圧制御発振器（以下、ＶＣＯと略
称する）で、こ７）ＶＣＯ２３７）出力信号ｔζ豆相北
較器２１て噌ｌさルる；うて構成さルてＡる、 第５図に第４図江示した定来すｊＤ位相差とループフィ
ルタ出力１王Ｖｄの関％？示す説明図でありＯ つぎ′／Ｃ第４図に示すＰＬＬ回ｊ！Ｄ動作全説刷すり
０ まず、入力信号ｉζＶＣＯ２３の出力信号ｔが位相比較
器２１に入力されると、それらの位相差に応じたｔＥＥ
ｊを位相比較器２１が出力する。In the figure, 21 is a phase comparator that receives an input signal l, 22 is a loop filter that is a low-pass filter that receives voltage j from this phase comparator 21, and 23 is a DC component outputted from this loop filter 22. A voltage controlled oscillator (hereinafter abbreviated as VCO) in which the oscillation frequency is controlled by KK. What is the relationship between the constant jD phase difference shown in Fig. 4 and the loop filter output Vd in Fig. 5? This is an explanatory diagram showing the PLL times shown in FIG. First, when the output signal t of the input signal iζVCO 23 is input to the phase comparator 21, tEE corresponds to the phase difference between them.
The phase comparator 21 outputs j.

つぎ【、ループフィルタ２２ｒＩ：位相比１１器２１の
出力を入力とし、その直流成分を出方する。そして、Ｖ
ＣＯ２３はこのループフィルタ２２からの直流成分ｋを
制御電圧として受け、それに見合った周波数の信号を発
振する。Next, loop filter 22rI: inputs the output of the phase ratio converter 21, and outputs its DC component. And V
The CO 23 receives the DC component k from the loop filter 22 as a control voltage, and oscillates a signal with a frequency corresponding to the control voltage.

この一連の動作を繰シ返しＶＣＯ２３の出力１号ｔは入
力信号ｌに同期する。This series of operations is repeated until the output No. 1 t of the VCO 23 is synchronized with the input signal l.

〔発明が解決しようとする課題〕 この従来のＰＬＬ回路では、位相比較器によって入力信
号とｖＣｏ出カ出力相差のみ？検出し、ＶＣＯＫ屑還七
かけているので、入力信号とｖＣＯ出力０′７ＩＲ友数
が異ｉるとき、第５図て示す：うて、位相差が０から２
ｘの間全回９続け、位相比較器の出力であるループフィ
ルタ出力電圧Ｙｄは正出力２反出力と繰り返し、直流成
分が検出さｎないことがある。このため、このＰＬＬの
構成では、入力信号とＶＣＯの出力信号の周波数がＡ＆
るとき、ＶＣＯの制御電圧を位相比較器の出力電圧で制
御できず、同期がとれないという課題があった。[Problems to be Solved by the Invention] In this conventional PLL circuit, only the phase difference between the input signal and the vCo output is determined by the phase comparator? Since the input signal and the VCO output are different from each other, the phase difference is from 0 to 2 as shown in Figure 5.
The loop filter output voltage Yd, which is the output of the phase comparator, repeats two positive outputs and two negative outputs for a total of 9 times during x, and the DC component may not be detected. Therefore, in this PLL configuration, the frequencies of the input signal and the output signal of the VCO are A &
When using the VCO, there was a problem in that the control voltage of the VCO could not be controlled by the output voltage of the phase comparator, and synchronization could not be achieved.

〔課題を解決する丸めの手段〕[Rounding method to solve the problem]

本発明のＰＬＬ回路は、位相比較器と、この位相比較器
の出力を入力とするループフィルタと、このループフィ
ルタの出力（よシ発振周波数が制御されるｖＣＯで構成
されるＰＬＬ回路において、入力信号を第１の１分周器
の入力とし、この第１のｉ分周器の出力を上記位相比較
器の第１の入力に接続し、上記ｖＣＯの出力を正２反両
出力を有する第２のｉ分周器に接続し、この第１＞７分
周器の正。The PLL circuit of the present invention includes a phase comparator, a loop filter whose input is the output of the phase comparator, and a vCO whose oscillation frequency is controlled by the output of the loop filter. The signal is input to a first 1 frequency divider, the output of the first i frequency divider is connected to the first input of the phase comparator, and the output of the vCO is connected to a first i frequency divider having positive and negative outputs. Connect to the i divider of 2 and the positive of this first >7 divider.

反両出力を２入力信号切換器のそれぞれの入力とし、こ
の２入力信号切換器の出力を上記位相比較器・Ｄ第２の
入力とし、かつ上記人カ官号？クコツク入力／Ｃ接続し
、上記２入力信号切喚器の出力テデ〜メ入力／？：擬続
した第１のＤ型フリップフコツブ回路と、上記入力信号
のインバーメチ介した反転信号？クコツク入力に接続し
、上記２大力信号切換器の出力とデータ入力に黍伏しｔ
第２のＤ型フリップフロッグ回路と、上記第１の十分周
器の出力と上記第１のＤ型フリッグフ；ツブ回路の出カ
ンよび上記第２のＤ型りリップフロップ回路の出力を３
入力とするナンドゲートｌ設け、このナンドゲートの出
力が上記２入力信号切換器の切換制御信号入力に接続さ
れるよプにし上ものである。The opposite outputs are used as respective inputs of a 2-input signal switch, and the output of the 2-input signal switch is used as the second input of the phase comparator/D. Connect the Kukotoku input/C, and output the output of the above 2-input signal cutter to the input/? : An inverted signal via the pseudo-connected first D-type flip-flop circuit and an inverter of the above input signal? Connect to the Kukotsuk input and connect to the output and data input of the two major signal switchers mentioned above.
A second D-type flip-flop circuit, the output of the first sufficient frequency divider and the first D-type flip-flop; the output of the tube circuit and the output of the second D-type flip-flop circuit
A NAND gate l is provided as an input, and the output of this NAND gate is connected to the switching control signal input of the two-input signal switching device.

〔作用〕[Effect]

本発明くおいては、入力信号とＶｃｏの出力信号の位相
差）πを検出し、ｖｃｏの出力２１分周器付切換器であ
る２人カ信号切換器によって反転させる。In the present invention, the phase difference (π) between the input signal and the output signal of the Vco is detected and inverted by a two-way signal switch, which is a switch with a 21 frequency divider for the output of the VCO.

〔実施例〕〔Example〕

以下、図７ＩＫ基づき本発明の実施例を詳細に説明する
。Hereinafter, embodiments of the present invention will be described in detail based on FIG. 7IK.

第１図は本発ＦｊＡによるＰＬＬ回路の一実施例を云す
ブロック図である。FIG. 1 is a block diagram showing one embodiment of a PLL circuit based on the present FjA.

このｌＸ１図において、１は位相比較器、２ζこの位相
比較器１の出力全入力とするループフィルタ、３にこの
ループフィルタ２の出力に：り発振肩波数がＩＩＪ御さ
ル、ｚＶｃｏ１４ばこの”／ＣＯ３の出力を入力とし正
２反出力を有する奇弁Ｒ器、５はとのｉ分周器４の正１
反両出力を入力としＶＣＯ３の出力の正１反を切プ換え
る２入力信号切換器で）この２入力信号切換器５の出力
は位相比較器１の一方の入力に接続されている。In this l An odd-valve R device which takes the output of /CO3 as input and has two positive and negative outputs, 5 is the positive 1 of the i frequency divider 4 with
The output of this two-input signal switch (5) is connected to one input of the phase comparator (1).

６は入力信号を２分周して出力するＤ型フリップ７ｏン
グ回路である十分周器で、この十分周器６の出力は位相
比較器１の他方の入力に接続されてｈる。７は入力信号
をクロック入力に接続し２入力信号切換器５の出力をデ
ータ入力に接続したＤＩＩ７１Ｊッグ７Ｃ２ツブ回路、
８は入力信号のインバータ９ｔ−介したｙ転信号をクロ
ック入力に接続し２入力信号切換器５の出力をデータ入
力に接続したＤ型７リツプフロツプ回路、１ｏは五分周
器５７）出カニＤ！フリノグフαノブ回路７の出力お二
びＤ型フリノブフコンブ回路り出力２３入力とするナツ
トゲートで、これらは丁分司５５とこもに÷π検出器（
位相差検出回路）１１を構成して・い６゜１２に入力１
号が印加される入力端子であそして、ナンドゲート１０
の出力が２入力信号切換器５の切換制御信号入力に接続
され、この第１図に示す実施例は入力信号の２倍の溝部
の信号全作９、もとの入力信号で一πの地点を′ｒｆＬ
接検出するように構成されている。ここで、入力信号の
立上りとＶＣＯ３の出力信号の立上りが一致するとき位
相差Ｏ（零）と定義し、入力信号の７πの点で’＋１’
ｃｏ３の出力信号が立上がったとき位相差πと定義する
。Reference numeral 6 denotes a sufficient frequency divider which is a D-type flip circuit which divides the frequency of the input signal by 2 and outputs the result.The output of this sufficient frequency divider 6 is connected to the other input of the phase comparator 1. 7 is a DII71J7C2 tube circuit that connects the input signal to the clock input and the output of the 2-input signal switch 5 to the data input;
8 is a D-type 7 lip-flop circuit in which the y-inverted signal of the input signal via the inverter 9t is connected to the clock input, and the output of the 2-input signal switch 5 is connected to the data input; 1o is the quintuple frequency divider 57) output D ! It is a nut gate that has two outputs from the Furinoguf α knob circuit 7 and an output 23 from the D-type Furinoguf knob circuit.
Phase difference detection circuit) 11 is configured and input 1 to 6°12.
At the input terminal to which the signal is applied, the NAND gate 10
The output of is connected to the switching control signal input of the two-input signal switch 5, and the embodiment shown in FIG. ′rfL
is configured to detect contact. Here, when the rising edge of the input signal and the rising edge of the output signal of VCO3 match, the phase difference is defined as O (zero), and at the 7π point of the input signal, the phase difference is '+1'.
When the output signal of co3 rises, the phase difference is defined as π.

第２図は第１図の各部における信号波形を示す図で、入
力信号周波数がＶＣＯ出力出力数波数も低い場合？示し
ている。この第２図において、（ａ）Ｖｉ入力信号ａｔ
−示したものであり、（ｂ）はＶＣＯ３の出力信号す、
ｅは一／２分周器６の出力ｃ、（ｄ）は２入力１号プ換
器５Ｄ出力＆、（ｅ）はＤ型フリノグフコ７・プ回路７
の出力・、（ｆ）ｒｍＤ型フリノブフコノグ回絡８の出
力ｆ、（ｇ）ζナンド°ゲー１−１０の出力ｇを示した
ものである。Fig. 2 is a diagram showing signal waveforms at each part in Fig. 1. What if the input signal frequency is low and the VCO output number wave number is also low? It shows. In this FIG. 2, (a) Vi input signal at
- (b) is the output signal of VCO3,
e is the output c of the 1/2 frequency divider 6, (d) is the 2-input No. 1 pump switch 5D output &, (e) is the D-type furino gufco 7/p circuit 7
, (f) the output f of the rmD-type Furinobufukonog circuit 8, and (g) the output g of the ζNando gate 1-10.

つぎに第１図に示す実施例の動作全第２図を参照して説
明するっ まず、入力信号ａ（第２図（＆）参照）がＤ型フリップ
フロップ回路であるｉ分周器６を通ることによシ波形が
２分周され第２図（ｃ）に示す：うな波形が得られる。Next, the entire operation of the embodiment shown in FIG. 1 will be explained with reference to FIG. 2. First, the input signal a (see FIG. As a result, the frequency of the waveform is divided by two, and a waveform like that shown in FIG. 2(c) is obtained.

また、ＶＣＯ３の出力信号ｂ（第２図（ｂ）参照）はｉ
分周器４を通ることＫよシ分濁されｌ／Ｉ、２図（ｄ）
に示すような波形またはその逆相となる。Also, the output signal b of VCO3 (see FIG. 2(b)) is i
Passing through the frequency divider 4, K is divided into l/I, Figure 2 (d)
The waveform will be as shown in or its opposite phase.

なお、ここで、２入力信号切換器５によシ第２図（ｄ）
Ｋ示すような波形が出力されると仮定する。そして、Ｄ
型フリップフロップ回路１のデータ入力を２入力信号切
換器５の出力ｄ、クロック入入力大入力信号とし、Ｄ型
７リツプ７０ッグ回路８のデータ入力を２入力信号切換
器５の出力ｄ、クロック入力を入力信号１の逆相（イン
バータ９の出力）ｈとすると、Ｄ型フリップフロップ回
路７゜３ｖ出力・、ｆζそ几ぞれ第２図（・）（ｆ）に
示す：う１波形となる。Note that here, the 2-input signal switch 5 is used as shown in FIG. 2(d).
Assume that a waveform as shown in K is output. And D
The data input of the D-type flip-flop circuit 1 is the output d of the 2-input signal switch 5 and the clock input/input large input signal, and the data input of the D-type 7 flip-flop circuit 8 is the output d of the 2-input signal switch 5. If the clock input is the opposite phase of the input signal 1 (output of the inverter 9) h, then the D-type flip-flop circuit 7゜3v output, fζ, respectively, are shown in Fig. 2(・)(f): Another waveform becomes.

ここで、ユ分、、司器Ｉ５の出力、＝０波形ζ入力信号
息とＶＣＯ３の出力１号すの位相差が０〜πのとき高レ
ベルとなり、π〜２にの）：き低レベルと々る。Here, when the phase difference between the input signal ζ and the output of the VCO 3 is 0 to π, the output of the controller I5 is a high level, and the output of the controller I5 is a low level. Totoru.

また、Ｄ型フリップフコツブ回路７の出力ｅＯ波形は位
相差がｏ−’ｗＴ、π〜７：ｃのとき高レベルとなシ、
−〜π、■π〜２πのとき低レベルとなる。Furthermore, the output eO waveform of the D-type flip-flop circuit 7 is at a high level when the phase difference is o-'wT, π~7:c.
The level is low when -~π and ■π~2π.

さらに、Ｄ型フリップフロッグ回路８の出力ｆｖ波形は
位相差が０〜−２π〜ｉπのとき低しベルとなり、ｉ〜
π、ｉπ〜２πのとき高レベルとなる。Furthermore, the output fv waveform of the D-type flip-flop circuit 8 becomes a low bell when the phase difference is 0 to -2π to iπ, and
It becomes a high level when π, iπ to 2π.

したがって、これら７分周器６の出力ＣとＤ型フリップ
７０ツブ回路γの出力・およびＤ型フリップフコツブ回
路８の出力ｆを３入力とするナンドゲート１０の出力ｇ
の波形は入力信号ａとＶＣＯ３の出力信号すの位相差か
ｉπのとき低レベルから高レベルへと切シ換わること（
なる。このナンドゲート１０の出力ｇを制御信号として
２入力信号切換器５はＶＣＯ３の出力信号すの正２反を
切）換見る。Therefore, the output g of the NAND gate 10 whose three inputs are the output C of the 7 frequency divider 6, the output of the D-type flip 70 tube circuit γ, and the output f of the D-type flip tube circuit 8.
The waveform switches from low level to high level when the phase difference between the input signal a and the output signal of VCO3 is iπ (
Become. Using the output g of the NAND gate 10 as a control signal, the two-input signal switch 5 switches between the positive and negative output signals of the VCO 3.

以上のように、入力１号ａとＶＣＯ３の出力１号１１Ｄ
位相差τπを噴出し、ＶＣＯ３の出力信号を切９換える
ことＫよジ、位相比較器１のＩＮ！成分は常に負のレベ
ルになる。これにより、ｖｃｏ３の出力信号すの周波数
は低くなる方向に！還がかかシ、入力信号息とＶＣＯ３
の出力信号すの同期がとれる。As mentioned above, input No. 1 a and output No. 1 11D of VCO3
By ejecting the phase difference τπ and switching the output signal of the VCO 3, the IN of the phase comparator 1! The component will always be at a negative level. As a result, the frequency of the output signal of VCO3 becomes lower! Return, input signal and VCO3
The output signals can be synchronized.

そして、入力信号ａの周波数がＶＣＯの出力信号すの周
波数よりも高い場合には、逆に位相比較器１の出力の直
流成分は常に正レベルとなシ、ＶＣＯ３の出力信号ｂｏ
ｘ波数は嶌くなる方向に帰還がかかシ、同期がとれる。When the frequency of the input signal a is higher than the frequency of the output signal of the VCO, conversely, the DC component of the output of the phase comparator 1 is always at a positive level, and the output signal of the VCO 3 is
The x-wave number returns in the direction of decreasing, and synchronization can be achieved.

第３図に本発明の実施例の位相差とループフィルタ出力
電圧Ｖ、の関係を示す。FIG. 3 shows the relationship between the phase difference and the loop filter output voltage V in the embodiment of the present invention.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、入力信号とＶＣＯの出力
信号の位相差ｉπを検出し、ｖｃｏの出力を！ ｉ分周器付切換器である２入力信号切換器によって反転
させるよう（したので、ｖｃｏを制御するループフィル
タの出力は常ＫＶＣＯの周波数を入力信号Ｃ，１友数に
近づｒ′Ｆ：つとする４Ｄご１ジ１．同期ｔｆ間が短ρ
）くなるという効果を有する。。As explained above, the present invention detects the phase difference iπ between the input signal and the output signal of the VCO, and detects the output of the VCO! Since it is inverted by a 2-input signal switch which is a switch with an i frequency divider, the output of the loop filter that controls the VCO always approaches the frequency of the KVCO to the input signal C, 1 frequency r'F: 1. Synchronization tf interval is short ρ
) has the effect of becoming .

４、図Ｉの聞臘１説調 ｊＥｌＮは本発明疋よる位相同期回路の一実施テｌ全示
すブロック図、８２図はＪｓ１図の各部に２ぐる１号波
形を示す図１．ＪＥ３図は第１図に示す実施例の位相差
とループフィルタ出力電圧の関係？示す説明図、第４図
は従来の位相同期回Ｍ”）−例を示すブロック図、第５
図ζ第４図に示した従来例の位相差とループフィルタ出
力電圧の関係を示す説明図である。4. In Figure 1, ElN is a block diagram showing a complete implementation of a phase-locked circuit according to the present invention, and Figure 82 is a block diagram showing two waveforms in each part of Figure 1. Is diagram JE3 the relationship between the phase difference and loop filter output voltage of the embodiment shown in Figure 1? FIG. 4 is a block diagram illustrating an example of a conventional phase-locked circuit M"), FIG.
FIG. 6 is an explanatory diagram showing the relationship between the phase difference and the loop filter output voltage in the conventional example shown in FIG. 4;

１・・・・位相比較器、２・・・・ループフィルタ、３
・・−・ＶＣＯ（電圧制御発振器）、４・・・・−分周
器、５・・・・２入力信号切換器、６・・・・７分周器
、７，８・・・・Ｄ型フリップフロップ回路、９１１−
・ｅインバータ、１０・・ｌ１１１ナンドゲート。1... Phase comparator, 2... Loop filter, 3
...VCO (voltage controlled oscillator), 4...-frequency divider, 5...2 input signal switcher, 6...7 frequency divider, 7, 8...D Type flip-flop circuit, 911-
・e-inverter, 10...l111 NAND gate.

特徴出１人日本電気株式会社Characteristic 1 person NEC Corporation

Claims (1)

【特許請求の範囲】[Claims] 位相比較器と、この位相比較器の出力を入力とするルー
プフィルタと、このループフィルタの出力により発振周
波数が制御される電圧制御発振器で構成される位相同期
回路において、入力信号を第１の１／２分周器の入力と
し、この第１の１／２分周器の出力を前記位相比較器の
第１の入力に接続し、前記電圧制御発振器の出力を正、
反両出力を有する第２の１／２分周器に接続し、この第
２の１／２分周器の正、反両出力を２入力信号切換器の
それぞれの入力とし、この２入力信号切換器の出力を前
記位相比較器の第２の入力とし、かつ前記入力信号をク
ロック入力に接続し、前記２入力信号切換器の出力をデ
ータ入力に接続した第１のＤ型フリップフロップ回路と
、前記入力信号のインバータを介した反転信号をクロッ
ク入力に接続し、前記２入力信号切換器の出力をデータ
入力に接続した第２のＤ型フリップフロップ回路と、前
記第１の１／２分周器の出力と前記第１のＤ型フリツプ
フロップ回路の出力および前記第２のＤ型フリップフロ
ップ回路の出力を３入力とするナンドゲートを設け、こ
のナンドゲートの出力が前記２入力信号切換器の切換制
御信号入力に接続されることを特徴とする位相同期回路
。In a phase-locked circuit consisting of a phase comparator, a loop filter that receives the output of the phase comparator, and a voltage-controlled oscillator whose oscillation frequency is controlled by the output of the loop filter, the input signal is /2 frequency divider, the output of this first 1/2 frequency divider is connected to the first input of the phase comparator, and the output of the voltage controlled oscillator is positive,
It is connected to a second 1/2 frequency divider having inverse outputs, and the positive and inverse outputs of this second 1/2 frequency divider are used as respective inputs of a 2-input signal switcher, and this 2-input signal a first D-type flip-flop circuit, wherein the output of the switch is a second input of the phase comparator, the input signal is connected to a clock input, and the output of the two-input signal switch is connected to a data input; , a second D-type flip-flop circuit in which an inverted signal of the input signal via an inverter is connected to a clock input, and an output of the two-input signal switch is connected to a data input; A NAND gate having three inputs is the output of the frequency converter, the output of the first D-type flip-flop circuit, and the output of the second D-type flip-flop circuit, and the output of this NAND gate controls the switching of the two-input signal switch. A phase-locked circuit connected to a signal input.