JPH0396138A - Code generator - Google Patents
Code generatorInfo
- Publication number
- JPH0396138A JPH0396138A JP1234241A JP23424189A JPH0396138A JP H0396138 A JPH0396138 A JP H0396138A JP 1234241 A JP1234241 A JP 1234241A JP 23424189 A JP23424189 A JP 23424189A JP H0396138 A JPH0396138 A JP H0396138A
- Authority
- JP
- Japan
- Prior art keywords
- code
- clock
- outputs
- switching means
- code generator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001360 synchronised effect Effects 0.000 claims description 5
- 239000003990 capacitor Substances 0.000 abstract description 3
- 238000005562 fading Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 5
- 238000004891 communication Methods 0.000 description 3
- 238000001228 spectrum Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000000411 transmission spectrum Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野]
本発明は符号発生装置に係り、RZ化されたPN符号を
ベースバンドで発生させるための改良に関する.
C発明の概要]
同期したPNクロックとPNコードとを用いてRZ化さ
れたPN符号をベースバンドで発生させるようにした符
号装置である.
[従来の技術コ
従来のRZ (Return to Zero)符号は
第6図に示すように、R F (Radio Freq
uency )変調されたBPSK符号Bを、適当なゲ
ート手段GによりBPSK符号の各ビットの後半の振幅
をOになるようにゲートをかけることによって生或して
いた。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a code generation device, and relates to an improvement for generating an RZ-converted PN code at baseband. C. Summary of the Invention] This is a coding device that generates an RZ PN code in the baseband using a synchronized PN clock and PN code. [Conventional technology] The conventional RZ (Return to Zero) code is RF (Radio Freq) as shown in FIG.
The modulated BPSK code B was generated by gating the amplitude of the second half of each bit of the BPSK code to O using suitable gating means G.
ゲート手段Gは図示したゲート信号で駆動しRZ化され
たBPSK符号を得ている。The gate means G is driven by the illustrated gate signal to obtain an RZ BPSK code.
【発明が解決しようとする課題]
上述した従来のRZ化方式によると、RZ符号をベース
バンドでは生成することができず、またゲート手段とし
て、例えばミキサを使用すれば高調波成分等が発生する
という問題があった。[Problems to be Solved by the Invention] According to the conventional RZ conversion method described above, it is not possible to generate an RZ code in the baseband, and if a mixer, for example, is used as a gate means, harmonic components etc. are generated. There was a problem.
更に従来、スペクトラム拡散通信に用いられるPN符号
は主にNR Z (Non Return to−Ze
ro)符号であり,特にRZ化された符号を発生させる
装置として適当なものが存在しなかった。Furthermore, conventionally, PN codes used in spread spectrum communications have mainly been NR Z (Non Return to Ze
ro) code, and in particular, there was no device suitable for generating an RZ code.
[考案の目的]
従って本発明の目的はスペクトラム拡散通信に使用する
PN符号を簡易な構或によりベースバンドでRZ化させ
ることを目的とする。[Object of the invention] Accordingly, an object of the present invention is to convert a PN code used in spread spectrum communication into an RZ code in the baseband using a simple structure.
[課題を解決するための手段]
本発明は上記目的を達成するため、同期したPNクロッ
クとPNコードが入力され、該クロックとコードとの所
定論理演算を行って第工及び第2の出力を得る論理回路
と,上記第1及び第2の出力の状態に応じて出力値が変
化するスイッチング手段と、を備えたことを要旨とする
.
[作用]
入力されるPNコードはNRZのものであっても、上記
ズイッチング手段からはRZ化されたPNコードが出力
される。[Means for Solving the Problem] In order to achieve the above object, the present invention receives a synchronized PN clock and a PN code, performs a predetermined logical operation on the clock and the code, and generates a first output and a second output. The present invention is characterized in that the present invention is provided with a logic circuit that obtains the output value, and a switching means that changes the output value depending on the states of the first and second outputs. [Operation] Even if the input PN code is an NRZ code, the RZ converted PN code is output from the above-mentioned switching means.
[実施例コ
以下図面に示す実施例を参照して本発明を説明する。第
1図は本発明による符号発生装置の一実施例を示し、l
はNRZ−PN符号発生器、2は論理回路,3はスイッ
チング回路である.第2図は上記論理回路の一構或例で
、ゲートGエ及びG2から或り、また第3図は上記スイ
ッチ?グ回路の一構成例で、工対のトランジスタQAf
Qa、コンデンサCエ,C2、抵抗R1〜R7から或る
。[Embodiments] The present invention will be described below with reference to embodiments shown in the drawings. FIG. 1 shows an embodiment of a code generator according to the present invention,
is an NRZ-PN code generator, 2 is a logic circuit, and 3 is a switching circuit. FIG. 2 shows an example of the structure of the above logic circuit, consisting of gates G and G2, and FIG. 3 shows the above switch? This is an example of the configuration of a switching circuit.
Qa, capacitors Ce, C2, and resistors R1 to R7.
NRZ−PN符号発生器1からは第4図に示す如<PN
クロックに同期したNRZのPNコードが出力される。From the NRZ-PN code generator 1, <PN
An NRZ PN code synchronized with the clock is output.
この同期したPNクロックとNRZのPNコードは論理
回路2を構或するゲートGエ,G2に与えられ、これら
ゲートによる論理演算により第4図に示す2つの信号a
エ及びbiが生或される。The synchronized PN clock and the NRZ PN code are applied to gates Ge and G2 that constitute the logic circuit 2, and the logic operations by these gates produce the two signals a shown in FIG.
d and bi are generated.
上記信号at+ b,は第3図のスイッチング回路に与
えられるが,上記PNコードのパターンはOと1の数が
ほぼ等しいという性質を有しているため,コンデンサC
■及びC2を介してとり出すことにより信号a1及びb
■のDC或分を除去して第4図に示す信号az+ b2
を得る。なお、第4図の信号azt bzにおいては
+v.I 弁 lvi’lt Iv21与Iv2’
l,IVil v2″
という関係が成立している.
次に第3図において、信号ag+ b,のtエの状態で
トランジスタQAはオン、QBはオフ、t2の状態にお
いてはトランジスタQA? QBは共にオフ、t,の状
態ではトランジスタQAがオフ、QBがオン,t4の状
態ではトランジスタQAt QBは共にオフとなる。そ
の結果,第4図に示すようにRZ化されたPN符号を得
ることができる.なお上記スイング回路は加算器で置き
換えることもできる。The above signal at+b is given to the switching circuit shown in Fig. 3, but since the above PN code pattern has a property that the number of O's and 1's are almost equal, the capacitor C
■ Signals a1 and b are extracted via C2 and C2.
By removing a certain amount of DC in (2), the signal az+b2 shown in FIG.
get. In addition, in the signal azt bz of FIG. 4, +v. I valve lvi'lt Iv21 given Iv2'
l,IVil v2'' is established.Next, in Fig. 3, in the state of te of the signal ag+b, the transistor QA is on and QB is off, and in the state of t2, the transistors QA?QB are both In the off state, t, transistor QA is off and transistor QB is on, and in the state t4, both transistors QAt and QB are off.As a result, an RZ-converted PN code can be obtained as shown in Fig. 4. Note that the swing circuit described above can also be replaced with an adder.
[発明の効果]
以上説明したように本発明によればスペクトラム拡散通
信等で使用するPN符号をRZ化することにより,第5
図に示すようにPNクロック周波数は同一でも送信スペ
クトラムの広帯域化(B→2B)を実現することができ
、酎フェージング特性及び耐妨害特性が改善される。[Effect of the invention] As explained above, according to the present invention, by converting the PN code used in spread spectrum communication etc. into RZ, the fifth
As shown in the figure, even if the PN clock frequency is the same, the transmission spectrum can be made wider (B→2B), and the fading characteristics and anti-jamming characteristics are improved.
第1図は本発明の一実施例を示すブロック図、第2図は
該実施例における論理回路の一構或例を示す図,第3図
は上記実施例におけるスイッチング回路の一構成例を示
す回路図,第4図は上記実施例の動作説明用タイムチャ
ート、第5図は本発明の効果の説明図、第6図は従来技
術の説明図である。
1・・・・・・・・・NZR−PN符号発生器、2・・
・・・・・・・論理回路,3・・・・・・・・・スイッ
チング回路。FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing an example of the configuration of a logic circuit in the embodiment, and FIG. 3 is a diagram showing an example of the configuration of a switching circuit in the above embodiment. 4 is a time chart for explaining the operation of the above embodiment, FIG. 5 is a diagram for explaining the effects of the present invention, and FIG. 6 is a diagram for explaining the prior art. 1...NZR-PN code generator, 2...
・・・・・・Logic circuit, 3・・・・・・・・・Switching circuit.
Claims (1)
ックとコードとの所定論理演算を行って第1及び第2の
出力を得る論理回路と、 上記第1及び第2の出力の状態に応じて出力値が変化す
るスイッチング手段と、 を備えたことを特徴とする符号発生装置。[Scope of Claims] A logic circuit that receives a synchronized PN clock and a PN code, performs a predetermined logical operation on the clock and the code, and obtains first and second outputs; and the first and second outputs. A code generator comprising: a switching means whose output value changes according to the state of the code generator;
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1234241A JPH0396138A (en) | 1989-09-08 | 1989-09-08 | Code generator |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1234241A JPH0396138A (en) | 1989-09-08 | 1989-09-08 | Code generator |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0396138A true JPH0396138A (en) | 1991-04-22 |
Family
ID=16967894
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1234241A Pending JPH0396138A (en) | 1989-09-08 | 1989-09-08 | Code generator |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0396138A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04159836A (en) * | 1990-10-23 | 1992-06-03 | Kubota Corp | Digital signal modulator |
JPH05122193A (en) * | 1991-10-25 | 1993-05-18 | G D S:Kk | Spread spectrum communication equipment |
JP2005181193A (en) * | 2003-12-22 | 2005-07-07 | Tdk Corp | Pulse-wave radar apparatus |
JP2006194802A (en) * | 2005-01-17 | 2006-07-27 | Fujitsu Component Ltd | Distance measuring apparatus |
KR20070071414A (en) * | 2005-12-30 | 2007-07-04 | 두산인프라코어 주식회사 | Pendant dual supporting structure for operating plate |
-
1989
- 1989-09-08 JP JP1234241A patent/JPH0396138A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04159836A (en) * | 1990-10-23 | 1992-06-03 | Kubota Corp | Digital signal modulator |
JPH05122193A (en) * | 1991-10-25 | 1993-05-18 | G D S:Kk | Spread spectrum communication equipment |
JP2005181193A (en) * | 2003-12-22 | 2005-07-07 | Tdk Corp | Pulse-wave radar apparatus |
JP2006194802A (en) * | 2005-01-17 | 2006-07-27 | Fujitsu Component Ltd | Distance measuring apparatus |
KR20070071414A (en) * | 2005-12-30 | 2007-07-04 | 두산인프라코어 주식회사 | Pendant dual supporting structure for operating plate |
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