JPH039607A - D-class power amplifier with low distortion factor - Google Patents
D-class power amplifier with low distortion factorInfo
- Publication number
- JPH039607A JPH039607A JP1142156A JP14215689A JPH039607A JP H039607 A JPH039607 A JP H039607A JP 1142156 A JP1142156 A JP 1142156A JP 14215689 A JP14215689 A JP 14215689A JP H039607 A JPH039607 A JP H039607A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- operational amplifier
- output
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000003321 amplification Effects 0.000 claims abstract description 15
- 238000003199 nucleic acid amplification method Methods 0.000 claims abstract description 15
- 230000008929 regeneration Effects 0.000 claims description 9
- 238000011069 regeneration method Methods 0.000 claims description 9
- 230000004913 activation Effects 0.000 abstract description 9
- 238000010586 diagram Methods 0.000 description 5
- 230000003213 activating effect Effects 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
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- Amplifiers (AREA)
Abstract
Description
【発明の詳細な説明】
「産業上の利用分野」
本発明は電気信号の電力を増幅するＤ級電力増幅装置に
関する。DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a class D power amplification device that amplifies the power of an electrical signal.
「従来の技術ｊ
１氏周波の電気信号を高電力効率で増幅する装置として
ＢＤ級電力増幅器が知られている。``Prior Art J'' A BD class power amplifier is known as a device that amplifies a 1 degree frequency electrical signal with high power efficiency.
この増幅器は、アナログ人力信号を正半波と負半波の二
系統の半波信号に分解し、各々をパルス幅変調器で高周
波の二値信号に変換し、スイッチングトランジスタおよ
び直流電源からなる二値ＩＮ号増幅器によりこれらを電
力増幅してから加え合わせ、復調用ＬＣローパスフィル
タにより低周波基本信号を取り出して負荷抵抗に供給す
る。This amplifier decomposes an analog human input signal into two half-wave signals, a positive half-wave and a negative half-wave, and converts each into a high-frequency binary signal using a pulse width modulator. The power of these signals is amplified by a value IN amplifier and then added together, and a low frequency fundamental signal is extracted by a demodulating LC low-pass filter and supplied to a load resistor.
この増幅器の二値信号増幅用トランジスタはオン・オフ
のスイッチ動作を行うため、電力損失がＡ級、Ｂ級動作
の場合に比べ著しく低減され９０％を越える高い電力効
率が得られる。Since the binary signal amplifying transistor of this amplifier performs an on/off switching operation, power loss is significantly reduced compared to the case of class A or class B operation, and a high power efficiency of over 90% can be obtained.
「発明が解決しようとする課題」
しかし、この増幅器は、信号電圧の零レベル付近で正・
負信号系統が交代するため、この付近に除去困難な不感
帯が生じ大きなりロスオーバ歪みを発生する欠点があっ
た。この増幅器の他の欠点は、二値信号電力増幅用トラ
ンジスタとして正半波用と負半波用の一組の相補形トラ
ンジスタを要する点にある。これらは高周波、大電力信
号を扱うため高価であり種類も少ない。これらの欠点が
実用化および低価格化の障害となっていた。``Problem to be solved by the invention'' However, this amplifier is not positive near the zero level of the signal voltage.
Since the negative signal system alternates, a dead zone that is difficult to eliminate occurs in this vicinity, resulting in a large lossover distortion. Another drawback of this amplifier is that it requires a pair of complementary transistors for positive half waves and negative half waves as transistors for binary signal power amplification. These are expensive because they handle high-frequency, high-power signals, and there are only a few types. These drawbacks have been an obstacle to practical application and price reduction.
［課題を解決するための手段ｊ
これらの欠点を改善するため、本発明の増幅装置は、絶
対値回路、極性再生回路、および制御回路を用いて二値
信号増幅系を一系統に低減している。従って、相補形ト
ランジスタを要しない。また、極性再生回路内の終段ト
ランジスタ群に印加された活性化電圧によりクロスオー
バ歪みが除去される。新たに付加された回路では低周波
信号のみを扱うため、これに用い得る半導体の種類は豊
富であり価格も低い。[Means for Solving the Problems j] In order to improve these drawbacks, the amplifier device of the present invention reduces the binary signal amplification system to a single system using an absolute value circuit, a polarity regeneration circuit, and a control circuit. There is. Therefore, complementary transistors are not required. Furthermore, crossover distortion is removed by the activation voltage applied to the final stage transistor group in the polarity regeneration circuit. Since the newly added circuit handles only low-frequency signals, there are a wide variety of semiconductors that can be used, and the prices are low.
「作用」
この増幅装置では、アナログ入力信号が絶対値回路で絶
対値信号に変換され、これに終段トランジスタ活性化用
電圧が加算されて一系統のみの増幅用信号となる。この
信号がパルス幅変調器で二値化され、二値信号増幅用ト
ランジスタにより電力増幅され、ＬＣフィルタにより復
調される。"Operation" In this amplifier, an analog input signal is converted into an absolute value signal by an absolute value circuit, and a voltage for activating a final stage transistor is added to this signal to form a signal for amplification of only one system. This signal is binarized by a pulse width modulator, power amplified by a binary signal amplification transistor, and demodulated by an LC filter.
この復調出力電力のうち、絶対値信号成分は極性再生回
路内の終段トランジスタ群により正・負極性が付与され
て負荷に供給され、活性化電力成分は極性再生回路内の
終段トランジスタｕ′Ｆ−の活性化に費やされる。Of this demodulated output power, the absolute value signal component is given positive and negative polarity by the final stage transistor group in the polarity regeneration circuit and is supplied to the load, and the activated power component is supplied to the final stage transistor u' in the polarity regeneration circuit. It is spent on activation of F-.
制御回路は、分割された人力信号から正半波に対応する
信号と負半波に対応する信号とを発生する。これらの信
号は前記極性再生回路内の終段トランジスタ群の制御電
極に人力され、負荷電流の方向と流量が制御される。二
値増幅の際に発生した歪み電力は、終段トランジスタＪ
ｒｌ−の活性と負帰還により除去される。The control circuit generates a signal corresponding to a positive half wave and a signal corresponding to a negative half wave from the divided human power signal. These signals are input to the control electrodes of the final stage transistor group in the polarity regeneration circuit, and the direction and flow rate of the load current are controlled. Distortion power generated during binary amplification is transferred to the final stage transistor J
It is removed by activation of rl- and negative feedback.
「実施例」 次に本発明を実施例を用いて説明する。"Example" Next, the present invention will be explained using examples.
第１図は、本発明を応用した増幅装置の絶対値回路、パ
ルス幅変調回路、二値信号増幅回路、および復調回路の
結線図である。FIG. 1 is a wiring diagram of an absolute value circuit, a pulse width modulation circuit, a binary signal amplification circuit, and a demodulation circuit of an amplifier to which the present invention is applied.
低周波アナログ信号源１からの入力信号は、抵抗および
キャパシタからなる位相補正回路により進相され絶対値
回路に導かれる。絶対値回路は、演算増幅器４とダイオ
ードおよび抵抗からなる半波分類回路と、この出力と進
相信号を加算する抵抗２および３から成る。端子５には
入力信号電圧の絶対値に比例する信号電流と抵抗６から
の終段トランジスタ活性化用バイアス電流を加えた増幅
用信号電流が流れ、演暮増幅器７の出力端子８に負極性
の増幅用電圧信号が発生する。An input signal from a low frequency analog signal source 1 is advanced in phase by a phase correction circuit consisting of a resistor and a capacitor and is guided to an absolute value circuit. The absolute value circuit consists of an operational amplifier 4, a half-wave classification circuit made up of a diode and a resistor, and resistors 2 and 3 that add the output of this half-wave classification circuit and an advanced signal. A signal current for amplification, which is a signal current proportional to the absolute value of the input signal voltage and a bias current for activating the final stage transistor from the resistor 6, flows through the terminal 5, and a negative polarity signal flows into the output terminal 8 of the performance amplifier 7. A voltage signal for amplification is generated.
この電圧信号は、パルス幅変調器９により二値信号に変
換され、二値信号増幅用のＮＭＯ３形スイッチングトラ
ンジスタｌＯにより電力増幅され、ＬＣＣコロ−パスフ
ィルタ１２１３により復調され端子１５に出力される。This voltage signal is converted into a binary signal by the pulse width modulator 9, power amplified by the NMO3 type switching transistor IO for binary signal amplification, demodulated by the LCC co-pass filter 1213, and output to the terminal 15.
１４はキャッチダイオード、１１は３０ｖの直流電源で
ある。無人力信号時は約−１ｖの静活性化電圧のみが端
子１５に出力される。14 is a catch diode, and 11 is a 30V DC power supply. At the time of an unmanned power signal, only a static activation voltage of about -1V is output to the terminal 15.
本例のパルス幅変調器９は自励形ＰＷＭ回路に相当する
が、他励形回路を用いてもよい。Although the pulse width modulator 9 of this example corresponds to a self-excited PWM circuit, a separately excited type circuit may also be used.
以上の回路構成によれば、一系統の二値信号系で全波が
増幅され、低性能で高価なＰチャンネル形電界効果トラ
ンジスタの使用を回避できる。According to the above circuit configuration, a full wave is amplified by one binary signal system, and the use of low-performance and expensive P-channel field effect transistors can be avoided.
第二図は、第一図の回路に接続される極性再生回路およ
び制御回路の結線図である。FIG. 2 is a wiring diagram of a polarity regeneration circuit and a control circuit connected to the circuit of FIG. 1.
信号源１から分割入力されたアナログ信号は、可変抵抗
１６により振幅調整されて制御回路内の半波分離回路に
加えられる。演算増幅器１７とダイオードおよび抵抗の
一部は半波分離回路を構成しており、端子工８には人力
信号電圧の負半波に相当する信号が正極性電圧として発
生する。この電圧と可変抵抗１６の端子電圧の和から入
力信号電圧の正半波に相当する差信号を作り端子１９に
出力する。The analog signal divided and inputted from the signal source 1 is amplitude-adjusted by a variable resistor 16 and is applied to a half-wave separation circuit in the control circuit. The operational amplifier 17, a diode, and a portion of the resistor constitute a half-wave separation circuit, and a signal corresponding to the negative half-wave of the human input signal voltage is generated at the terminal 8 as a positive polarity voltage. A difference signal corresponding to a positive half wave of the input signal voltage is generated from the sum of this voltage and the terminal voltage of the variable resistor 16 and output to the terminal 19.
２０および２１はダイオード間に０．６ｖの順バイアス
電圧を加え応答時間を短縮するための定電流ダイオード
と抵抗であり、２２は信号電圧の１％に相当。20 and 21 are constant current diodes and resistors for shortening the response time by applying a forward bias voltage of 0.6 V between the diodes, and 22 corresponds to 1% of the signal voltage.
する動的活性化電圧を加えるための抵抗である。This is a resistor for applying a dynamic activation voltage.
端子工８から抵抗２３を介して極性再生回路内の演算増
幅器２４に入力された負半波制御信号は、反転され半ブ
リッジを形成する終段トランジスタ２５・２６のベース
に人力される。復調出力に挿入された一１ｖの活性化電
圧は、小入力信号時にはトランジスタ２５・２６のコレ
クタ・エミッタ間にほぼ−０，５ｖずつ配分されこれら
のトランジスタを活性領域に置く。従って、出力端子２
７には入力信号の負半波にほぼ比例した信号電圧が得ら
れる。２８は端子２７の無信号時直流電位を約−０，５
ｖに規定するための抵抗であり、２９および３０はトラ
ンジスタ２５・２６に５ｉＡのアイドリング電流を与え
るための抵抗および定電流ダイオードである。トランジ
スタ２５・２６への電力は復調出力端子１５から供給さ
れる。The negative half-wave control signal input from the terminal 8 to the operational amplifier 24 in the polarity recovery circuit via the resistor 23 is inverted and input to the bases of final stage transistors 25 and 26 forming a half bridge. The activation voltage of -1 V inserted into the demodulated output is distributed approximately -0.5 V between the collectors and emitters of the transistors 25 and 26 when the input signal is small, placing these transistors in the active region. Therefore, output terminal 2
7, a signal voltage approximately proportional to the negative half wave of the input signal is obtained. 28 sets the DC potential of terminal 27 during no signal to approximately -0.5
29 and 30 are resistors and constant current diodes for providing an idling current of 5 iA to the transistors 25 and 26. Power to the transistors 25 and 26 is supplied from the demodulation output terminal 15.
一方、端子１９から極性再生回路内に人力された差制御
信号は、演算増幅器３１により極性が反転され他の半ブ
リッジを形成する終段トランジスタ３２・３３のベース
に人力される。この回路の動作は前記半ブリッジと同様
である。従って、出力端子３４には入力信号の正半波に
ほぼ比例する負極性の差信号電圧が得られる。On the other hand, the polarity of the difference control signal input from the terminal 19 into the polarity regeneration circuit is inverted by the operational amplifier 31, and input to the bases of the final stage transistors 32 and 33 forming the other half bridge. The operation of this circuit is similar to the half-bridge described above. Therefore, a negative difference signal voltage approximately proportional to the positive half wave of the input signal is obtained at the output terminal 34.
８Ωの負荷抵抗３７への出力電圧は、出力端子２７と３
４の電位差となるため負小波成分が打消され入力信号の
増幅電圧となる。打消し量は可変抵抗２３により微調節
される。抵抗３５および３６による負帰還により終段ト
ランジスタ群で発生した歪とこれらに印加された復調電
力の歪み成分が除去されるため、歪率が０．２％以下に
低減される。また、電力効率は大出力時には８８％程度
に達し、電源１１の電圧がより尚い場合には更に上昇す
る。The output voltage to the 8Ω load resistor 37 is output from output terminals 27 and 3.
Since the potential difference is 4, the negative small wave component is canceled and becomes the amplified voltage of the input signal. The amount of cancellation is finely adjusted by the variable resistor 23. Negative feedback by the resistors 35 and 36 removes the distortion generated in the final stage transistor group and the distortion components of the demodulated power applied thereto, so that the distortion factor is reduced to 0.2% or less. Further, the power efficiency reaches about 88% at high output, and increases further when the voltage of the power supply 11 is lower.
「発明の効果」
本発明による増幅装置は以上の説明のように構成されて
いる結果、二値信号増幅回路で発生する歪みを大幅に低
減することが可能となり、大電力増幅器および携帯用機
器等えの応用が著しく促進される。また、高周波型カス
イツチング素子−個で全波の電力が増幅されるため、Ｐ
チャンネル形スイッチング素子の使用が回避され、増幅
回路の集積化、小型化、低価格化が容易になる。"Effects of the Invention" As a result of the amplification device according to the present invention being configured as described above, it is possible to significantly reduce distortion generated in a binary signal amplification circuit, and it can be used in large power amplifiers, portable devices, etc. The application of technology will be significantly promoted. In addition, since the full-wave power is amplified by the high-frequency customizing element, P
The use of channel-type switching elements is avoided, making it easier to integrate, miniaturize, and lower the cost of the amplifier circuit.
第一図は本発明を応用した増幅装置の絶対値回路、パル
ス幅変調回路、二値信号増幅回路、および復調回路の結
線図、第二図は第一図に示した回路に接続される極性再
生回路および制御回路の結線図である。
１・・信号源、９・・変調器、１１・・直流電源２０・
・定電流ダイオード、３７・・負荷抵抗。Figure 1 is a wiring diagram of the absolute value circuit, pulse width modulation circuit, binary signal amplification circuit, and demodulation circuit of the amplifier to which the present invention is applied, and Figure 2 is the polarity diagram connected to the circuit shown in Figure 1. FIG. 3 is a wiring diagram of a reproduction circuit and a control circuit. 1. Signal source, 9. Modulator, 11. DC power supply 20.
- Constant current diode, 37...Load resistance.
Claims (1)
出力信号を二値信号に変調して信号電力を増幅する回路
と、この増幅出力を復調するＬＣフィルタ回路と、その
復調出力を負荷に供給する際の電流の向きを制御する極
性再生回路と、前記入力信号から前記極性再生回路への
制御信号を発生する制御回路を備えることを特徴とする
電気信号増幅装置。"1" A circuit that outputs the absolute value of an electrical input signal, a circuit that modulates this output signal into a binary signal and amplifies the signal power, an LC filter circuit that demodulates this amplified output, and a circuit that outputs the demodulated output. An electrical signal amplification device comprising: a polarity regeneration circuit that controls the direction of current when supplied to a load; and a control circuit that generates a control signal from the input signal to the polarity regeneration circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1142156A JPH0744403B2 (en) | 1989-06-06 | 1989-06-06 | Low distortion class D power amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1142156A JPH0744403B2 (en) | 1989-06-06 | 1989-06-06 | Low distortion class D power amplifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH039607A true JPH039607A (en) | 1991-01-17 |
| JPH0744403B2 JPH0744403B2 (en) | 1995-05-15 |
Family
ID=15308666
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1142156A Expired - Fee Related JPH0744403B2 (en) | 1989-06-06 | 1989-06-06 | Low distortion class D power amplifier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0744403B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5376216A (en) * | 1993-03-31 | 1994-12-27 | Dainippon Screen Mfg. Co., Ltd. | Device for holding and rotating a substrate |
| US5375291A (en) * | 1992-05-18 | 1994-12-27 | Tokyo Electron Limited | Device having brush for scrubbing substrate |
| US5421056A (en) * | 1993-04-19 | 1995-06-06 | Tokyo Electron Limited | Spin chuck and treatment apparatus using same |
| US5775000A (en) * | 1996-05-13 | 1998-07-07 | Ebara Corporation | Substrate gripper device for spin drying |
| JP2003506944A (en) * | 1999-07-29 | 2003-02-18 | トリパス テクノロジー インコーポレイテッド | Break-before-make distortion compensation for digital amplifiers |
-
1989
- 1989-06-06 JP JP1142156A patent/JPH0744403B2/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5375291A (en) * | 1992-05-18 | 1994-12-27 | Tokyo Electron Limited | Device having brush for scrubbing substrate |
| US5376216A (en) * | 1993-03-31 | 1994-12-27 | Dainippon Screen Mfg. Co., Ltd. | Device for holding and rotating a substrate |
| US5421056A (en) * | 1993-04-19 | 1995-06-06 | Tokyo Electron Limited | Spin chuck and treatment apparatus using same |
| US5775000A (en) * | 1996-05-13 | 1998-07-07 | Ebara Corporation | Substrate gripper device for spin drying |
| USRE37347E1 (en) | 1996-05-13 | 2001-09-04 | Ebara Corporation | Substrate gripper device for spin drying |
| JP2003506944A (en) * | 1999-07-29 | 2003-02-18 | トリパス テクノロジー インコーポレイテッド | Break-before-make distortion compensation for digital amplifiers |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0744403B2 (en) | 1995-05-15 |
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