JPH039404Y2 - - Google Patents
Info
- Publication number
- JPH039404Y2 JPH039404Y2 JP1984076207U JP7620784U JPH039404Y2 JP H039404 Y2 JPH039404 Y2 JP H039404Y2 JP 1984076207 U JP1984076207 U JP 1984076207U JP 7620784 U JP7620784 U JP 7620784U JP H039404 Y2 JPH039404 Y2 JP H039404Y2
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- collector
- circuit
- signal strength
- differential amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003990 capacitor Substances 0.000 claims description 9
- 230000003321 amplification Effects 0.000 claims description 8
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 8
- 238000009499 grossing Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 5
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 2
- 230000001629 suppression Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Circuits Of Receivers In General (AREA)
- Monitoring And Testing Of Transmission In General (AREA)
Description
【考案の詳細な説明】
本考案はFM受信機の信号強度指示計の駆動回
路に関する。[Detailed Description of the Invention] The present invention relates to a drive circuit for a signal strength indicator of an FM receiver.
第１図は従来の信号強度指示計の駆動回路の一
例を示す回路である。１は中間周波増幅段であ
り、２はFM検波器、３は平滑回路、４は駆動回
路、５は信号強度指示計である。斯かる回路は、
平滑回路３に多数のコンデンサを用いており、こ
れらが一般に半導体基板に形成されている為に、
素子面積が大きくなる欠点があり、安価なFM受
信機等には利用できない。更に、第１図に示すよ
うな従来の信号強度指示計の駆動回路は、中間周
波増幅段１と平滑回路３とがコンデンサによつて
容量結合されている為に、中間周波増幅段１に乗
つた僅かなAM信号の為に、中間周波信号がコン
デンサによつて位相変調され、FM信号にAMノ
イズが重畳されて取り出される欠点がある。所謂
AM抑圧比特性を劣化させる欠点があり、コンデ
ンサを除去することが望まれる。 FIG. 1 shows an example of a drive circuit for a conventional signal strength indicator. 1 is an intermediate frequency amplification stage, 2 is an FM detector, 3 is a smoothing circuit, 4 is a drive circuit, and 5 is a signal strength indicator. Such a circuit is
A large number of capacitors are used in the smoothing circuit 3, and since these are generally formed on a semiconductor substrate,
The disadvantage is that the element area is large, so it cannot be used in inexpensive FM receivers. Furthermore, in the drive circuit of a conventional signal strength indicator as shown in FIG. Because of the small amount of AM signals present, the intermediate frequency signal is phase modulated by the capacitor, and the disadvantage is that AM noise is superimposed on the FM signal and extracted. so-called
It has the disadvantage of deteriorating the AM suppression ratio characteristics, so it is desirable to eliminate the capacitor.
本考案は上述の如き課題に基づきなされたもの
であつて、FM受信機に用いられる安価で簡便な
信号強度指示計の駆動回路を提供することを主な
目的とする。 The present invention has been made based on the above-mentioned problems, and its main purpose is to provide an inexpensive and simple drive circuit for a signal strength indicator used in an FM receiver.
本考案の他の目的は、中間周波増幅段からの出
力でカツプリング・コンデンサを用いることな
く、信号強度指示計を駆動できる回路を提供する
にある。 Another object of the invention is to provide a circuit capable of driving a signal strength indicator with the output from an intermediate frequency amplifier stage without the use of a coupling capacitor.
本考案の信号強度指示計の駆動回路は、受信さ
れた電波が中間周波数に変換されて供給される複
数の差動対で形成された中間周波増幅段と、該中
間周波増幅段を形成する差動対の何れか一つの段
から互いに位相の反転した出力を得て、夫々の出
力を等しい直流バイアス電圧に重畳する為の第１
と第２のバツフア回路と、該第１と該第２のバツ
フア回路を介して得られる出力が夫々供給され、
それらの出力を半波整流、或いは全波整流する差
動増幅器と、該差動増幅器からの出力電流が平滑
されて供給される信号強度指示計とから構成され
たものである。 The drive circuit of the signal strength indicator of the present invention includes an intermediate frequency amplification stage formed by a plurality of differential pairs to which received radio waves are converted to an intermediate frequency and supplied, and a differential pair forming the intermediate frequency amplification stage. The first step is to obtain outputs whose phases are inverted to each other from any one stage of the dynamic pair, and to superimpose each output on an equal DC bias voltage.
and a second buffer circuit, and outputs obtained through the first and second buffer circuits are supplied, respectively;
It is composed of a differential amplifier that performs half-wave rectification or full-wave rectification of the outputs thereof, and a signal strength indicator to which the output current from the differential amplifier is supplied after being smoothed.
以下、本考案の信号強度指示計の駆動回路に就
いて第２図乃至第５図に基づき説明する。 Hereinafter, the driving circuit of the signal strength indicator of the present invention will be explained based on FIGS. 2 to 5.
第２図に於いて、中間周波増幅段１から互いに
位相の反転した出力を得て、バツフア回路６，７
を介し得られる互いに位相の反転した出力を等し
い直流レベルに重畳し、整流作用を有する差動増
幅器８に印加される。差動増幅器８によつて直流
成分は互いに打ち消され、出力段のトランジスタ
Ｑ８を介し平滑されて信号強度指示計５に駆動電
流が流し込まれる。又、中間周波増幅段１は複数
の差動対から形成され、何れかの差動対から出力
を得て整流回路に供給される。尚、第２図の実施
例は半波整流回路であり、第５図のは全整流回路
の実施例である。 In FIG. 2, outputs with mutually inverted phases are obtained from the intermediate frequency amplification stage 1, and buffer circuits 6 and 7 are connected.
The outputs obtained through the DC voltages and having mutually inverted phases are superimposed on an equal DC level and applied to a differential amplifier 8 having a rectifying function. The DC components are mutually canceled by the differential amplifier 8, smoothed through the output stage transistor Q8, and a drive current is supplied to the signal strength indicator 5. Further, the intermediate frequency amplification stage 1 is formed of a plurality of differential pairs, and an output is obtained from one of the differential pairs and supplied to a rectifier circuit. The embodiment shown in FIG. 2 is a half-wave rectifier circuit, and the embodiment shown in FIG. 5 is a full rectifier circuit.
第２図の差動増幅器８は差動対トランジスタＱ
１，Ｑ２と定電流回路９と能動負荷回路とから形
成されている。能動負荷回路はダイオード（ベー
スとコレクタが共通接続されたトランジスタ）Ｑ
５，Ｑ７とトランジスタＱ６から形成され、トラ
ンジスタＱ１，Ｑ２の夫々のコレクタにダイオー
ドＱ５，Ｑ７のカソードが夫々接続され、且つト
ランジスタＱ６のコレクタがトランジスタＱ１の
コレクタに接続され、トランジスタＱ６のベース
がダイオードＱ７のカソードに接続されている。
差動増幅器８の出力段のトランジスタＱ８のベー
スがトランジスタＱ１のコレクタに接続され、ト
ランジスタＱ８のコレクタに抵抗を介し信号強度
指示計５とコンデンサＣ１が接続される。 The differential amplifier 8 in FIG. 2 is a differential pair transistor Q.
1, Q2, a constant current circuit 9, and an active load circuit. The active load circuit is a diode (a transistor whose base and collector are commonly connected) Q
5, Q7 and a transistor Q6, the cathodes of diodes Q5 and Q7 are connected to the collectors of transistors Q1 and Q2, respectively, the collector of transistor Q6 is connected to the collector of transistor Q1, and the base of transistor Q6 is connected to a diode. Connected to the cathode of Q7.
The base of the transistor Q8 in the output stage of the differential amplifier 8 is connected to the collector of the transistor Q1, and the signal strength indicator 5 and the capacitor C1 are connected to the collector of the transistor Q8 via a resistor.
バツフア回路６，７はトランジスタＱ３，Ｑ４
とそのエミツタに接続された抵抗Ｒ１，Ｒ２から
夫々形成され、差動増幅器８の差動対トランジス
タＱ１，Ｑ２のベースに印加される出力は、等し
い直流電圧E0に重畳された中間周波信号が供給
されるようになされている。 Buffer circuits 6 and 7 are transistors Q3 and Q4
and resistors R1 and R2 connected to their emitters, respectively, and the output applied to the bases of the differential pair transistors Q1 and Q2 of the differential amplifier 8 is an intermediate frequency signal superimposed on an equal DC voltage E0. It is made to be supplied.
次に、第４図に基づきその動作について説明す
る。差動増幅器８の差動対のトランジスタＱ１，
Ｑ２に印加される信号は、互いに位相の反転した
信号を等しい直流電圧E0に重畳された信号であ
り、トランジスタＱ１のベースに第４図のイの波
形を有する電圧が印加されるのに対し、トランジ
スタＱ２のベースにロの波形を有する電圧が印加
される。トランジスタＱ１，Ｑ２のベースに印加
される電圧が互いに等しいP0点の場合、トラン
ジスタＱ１とＱ２のコレクタ電流が夫々I1，I2と
すると、トランジスタＱ６，Ｑ７からなる電流ミ
ラー回路を介してコレクタ電流I2に等しい電流I1
が流し込まれる。定電流源回路９には（I1＋I2）
の電流I3が流れるので、ダイオードＱ５には電流
が流れずカツトオフとなる。従つて、ダイオード
Ｑ５によつてバイアスされるトランジスタＱ８も
カツトオフとなる。そして、トランジスタＱ２の
ベース電圧が上昇すると、トランジスタＱ２のコ
レクタ電流は（I2＋△ｉ）となる。しかし、トラ
ンジスタＱ１のコレクタ電流はトランジスタＱ６
を介して供給される為に、ダイオードＱ５はカツ
トオフの状態を保持しており、トランジスタＱ８
もカツトオフ状態である。一方、トランジスタＱ
１のベース電圧が上昇すると、トランジスタＱ１
のコレクタ電流は（I1＋△ｉ）となり、トランジ
スタＱ２のコレクタ電流は（I2−△ｉ）となる。
従つて、ダイオードＱ５には２△ｉの電流が流れ
て、トランジスタＱ８のコレクタ電流として２△
ｉの電流が流れる。第４図ｂのハのごとき半波整
流された出力が得られ、且つコンデンサＣ１によ
つて平滑された出力ニが得られる。無論、トラン
ジスタＱ８のエミツタ面積をダイオードＱ５をな
すトランジスタのエミツタ面積の二倍とすると、
４△ｉの電流がコレクタ電流として流れる。第３
図は本考案の信号強度指示計の駆動回路の他の実
施例であり、抵抗Ｒ２と並行にコンデンサＣ２が
接続されており、高周波信号が遮断されて、直流
電圧E0のみがトランジスタＱ２のベースに印加
され、半波整流された出力が得られる。 Next, the operation will be explained based on FIG. Transistor Q1 of the differential pair of the differential amplifier 8,
The signal applied to Q2 is a signal in which signals whose phases are inverted to each other are superimposed on an equal DC voltage E0 . , a voltage having a waveform of (b) is applied to the base of transistor Q2. When the voltages applied to the bases of transistors Q1 and Q2 are equal to each other at point P 0 , if the collector currents of transistors Q1 and Q2 are I 1 and I 2 respectively, the collector currents flow through the current mirror circuit consisting of transistors Q6 and Q7. Current I 1 equal to current I 2
is poured in. Constant current source circuit 9 has (I 1 + I 2 )
Since the current I3 flows through the diode Q5, no current flows through the diode Q5 and the diode Q5 is cut off. Transistor Q8, which is biased by diode Q5, is therefore also cut off. Then, when the base voltage of the transistor Q2 increases, the collector current of the transistor Q2 becomes (I 2 +Δi). However, the collector current of transistor Q1 is
, the diode Q5 maintains the cut-off state, and the transistor Q8
is also in a cut-off state. On the other hand, transistor Q
When the base voltage of transistor Q1 increases,
The collector current of transistor Q2 becomes (I 1 +△i), and the collector current of transistor Q2 becomes (I 2 -△i).
Therefore, a current of 2△i flows through the diode Q5, and the collector current of the transistor Q8 is 2△.
A current of i flows. A half-wave rectified output such as C in FIG. 4B is obtained, and an output D smoothed by the capacitor C1 is obtained. Of course, if the emitter area of transistor Q8 is twice that of the transistor forming diode Q5, then
A current of 4Δi flows as a collector current. Third
The figure shows another embodiment of the drive circuit for the signal strength indicator of the present invention, in which a capacitor C2 is connected in parallel with the resistor R2, the high frequency signal is blocked, and only the DC voltage E0 is applied to the base of the transistor Q2. A half-wave rectified output is obtained.
一方、第５図は全波整流出力として搬送波の信
号強度を得る為の二重平衡形差動増幅回路１９の
実施例である。第３図の差動増幅回路と基本的に
同じ動作であり、差動対14に応じて差動対１２，
１３が交互に差動的に動作して、能動負荷回路１
５を介して全波整流された出力が得られる。１
７，１８はバツフア回路である。 On the other hand, FIG. 5 shows an embodiment of a double-balanced differential amplifier circuit 19 for obtaining the signal strength of a carrier wave as a full-wave rectified output. The operation is basically the same as that of the differential amplifier circuit shown in FIG. 3, and the differential pair 12,
13 are alternately operated differentially, and the active load circuit 1
5, a full-wave rectified output is obtained. 1
7 and 18 are buffer circuits.
上述の如く、本考案の信号強度指示計の駆動回
路は、従来のものと比較して、AM抑圧比特性を
悪化されることなく、素子数が低減できると共
に、差動増幅器で構成されている為に、所定の利
得を有する簡便な回路によつて形成できる利点が
ある。 As mentioned above, compared to conventional circuits, the drive circuit for the signal strength indicator of the present invention can reduce the number of elements without deteriorating the AM suppression ratio characteristics, and is composed of differential amplifiers. Therefore, there is an advantage that it can be formed by a simple circuit having a predetermined gain.
また、中間周波増幅段１から、カツプリング・
コンデンサを用いることなく、中間周波信号のみ
を得ることができる極めて効果的な信号強度指示
計の駆動回路を提供できる利点がある。 Also, from intermediate frequency amplification stage 1, coupling
It is advantageous to provide a highly effective signal strength indicator drive circuit that can obtain only an intermediate frequency signal without using a capacitor.
第１図は一般的な信号強度指示計の駆動回路の
例を示す回路図、第２図は本考案に係る信号強度
指示計の駆動回路の一実施例を示す回路図、第３
図は本考案に係る他の実施例を示す回路図、第４
図は本考案に係る信号強度指示計の駆動回路の動
作を説明する図、第５図は本考案に係る信号強度
指示計の駆動回路の他の実施例を示す回路図であ
る。
１：中間周波増幅段、２：FM検波回路、５：
信号強度指示計、６，７：バツフア回路、８：差
動増幅回路、９：定電流源回路、１２，１３，１
４：差動対、１５：能動負荷回路、１６：定電流
源回路、１７，１８：バツフア回路。
FIG. 1 is a circuit diagram showing an example of a drive circuit for a general signal strength indicator, FIG. 2 is a circuit diagram showing an embodiment of a drive circuit for a signal strength indicator according to the present invention, and FIG.
The figure is a circuit diagram showing another embodiment of the present invention.
The figure is a diagram for explaining the operation of the drive circuit for the signal strength indicator according to the present invention, and FIG. 5 is a circuit diagram showing another embodiment of the drive circuit for the signal strength indicator according to the present invention. 1: Intermediate frequency amplification stage, 2: FM detection circuit, 5:
Signal strength indicator, 6, 7: Buffer circuit, 8: Differential amplifier circuit, 9: Constant current source circuit, 12, 13, 1
4: differential pair, 15: active load circuit, 16: constant current source circuit, 17, 18: buffer circuit.
Claims (1)
出力がバツフア回路６，７を介して供給される
差動増幅器８と、該差動増幅器８に出力段に接
続された信号強度指示計５とを含み、該差動増
幅器８が該バツフア回路６，７からの出力が
夫々ベースに供給される差動対をなすトランジ
スタＱ１，Ｑ２と、該トランジスタＱ１，Ｑ２
の共通接続されたエミツタに接続された定電流
源回路９と、該差動対の能動負荷回路とからな
り、該能動負荷回路が差動対のトランジスタＱ
１，Ｑ２の夫々のコレクタにダイオードＱ５，
Ｑ７にカソードが夫々接続され、トランジスタ
Ｑ１のコレクタとダイオードＱ５のカソードに
トランジスタＱ６のコレクタが接続され、トラ
ンジスタＱ６のベースがトランジスタＱ２のコ
レクタとダイオードＱ７のカソードに接続さ
れ、ダイオードＱ５，Ｑ７のアノードとトラン
ジスタＱ６のエミツタが端子１０に接続されて
なり、トランジスタＱ１，Ｑ６のコレクタとダ
イオードＱ５のカソードに該差動増幅器８の出
力段のトランジスタＱ８のベースが接続され、
トランジスタＱ８のコレクタに平滑用のコンデ
ンサＣ１と信号強度指示計５が接続されてなる
ことを特徴とする信号強度指示計の駆動回路。 (2) 前記差動増幅器が二重平衡形の差動増幅器で
形成された実用新案登録請求の範囲第１項記載
の信号強度指示計の駆動回路。[Claims for Utility Model Registration] (1) A differential amplifier 8 to which outputs with mutually inverted phases are supplied from the intermediate frequency amplification stage 1 via buffer circuits 6 and 7; The differential amplifier 8 includes transistors Q1 and Q2 forming a differential pair whose bases are supplied with the outputs from the buffer circuits 6 and 7, respectively, and the transistors Q1 and Q2.
It consists of a constant current source circuit 9 connected to the commonly connected emitters of the transistor Q, and an active load circuit of the differential pair.
A diode Q5 is connected to the collector of each of Q1 and Q2,
The cathodes of the transistor Q7 are connected to each other, the collector of the transistor Q6 is connected to the collector of the transistor Q1 and the cathode of the diode Q5, the base of the transistor Q6 is connected to the collector of the transistor Q2 and the cathode of the diode Q7, and the anodes of the diodes Q5 and Q7 are connected to each other. The emitter of the transistor Q6 is connected to the terminal 10, and the base of the transistor Q8 in the output stage of the differential amplifier 8 is connected to the collectors of the transistors Q1 and Q6 and the cathode of the diode Q5.
A drive circuit for a signal strength indicator, characterized in that a smoothing capacitor C1 and a signal strength indicator 5 are connected to the collector of a transistor Q8. (2) The drive circuit for a signal strength indicator according to claim 1, wherein the differential amplifier is formed of a double-balanced differential amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984076207U JPS60189152U (en) | 1984-05-24 | 1984-05-24 | Signal strength indicator drive circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984076207U JPS60189152U (en) | 1984-05-24 | 1984-05-24 | Signal strength indicator drive circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60189152U JPS60189152U (en) | 1985-12-14 |
| JPH039404Y2 true JPH039404Y2 (en) | 1991-03-08 |
Family
ID=30618140
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1984076207U Granted JPS60189152U (en) | 1984-05-24 | 1984-05-24 | Signal strength indicator drive circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60189152U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4974572A (en) * | 1972-11-15 | 1974-07-18 | ||
| JPS5528513A (en) * | 1978-08-18 | 1980-02-29 | Pioneer Electronic Corp | Erasion magnetic head |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50153844U (en) * | 1974-06-07 | 1975-12-20 |
-
1984
- 1984-05-24 JP JP1984076207U patent/JPS60189152U/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4974572A (en) * | 1972-11-15 | 1974-07-18 | ||
| JPS5528513A (en) * | 1978-08-18 | 1980-02-29 | Pioneer Electronic Corp | Erasion magnetic head |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60189152U (en) | 1985-12-14 |
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