JPH0380565A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0380565A JPH0380565A JP21792489A JP21792489A JPH0380565A JP H0380565 A JPH0380565 A JP H0380565A JP 21792489 A JP21792489 A JP 21792489A JP 21792489 A JP21792489 A JP 21792489A JP H0380565 A JPH0380565 A JP H0380565A
- Authority
- JP
- Japan
- Prior art keywords
- type
- buried layer
- layer
- oxide film
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 239000012535 impurity Substances 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 6
- 239000011574 phosphorus Substances 0.000 abstract description 6
- 230000003071 parasitic effect Effects 0.000 abstract description 5
- 238000005468 ion implantation Methods 0.000 abstract description 4
- 230000008054 signal transmission Effects 0.000 abstract description 4
- 230000003647 oxidation Effects 0.000 abstract description 3
- 238000007254 oxidation reaction Methods 0.000 abstract description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract 2
- 229910052796 boron Inorganic materials 0.000 abstract 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 27
- 239000011229 interlayer Substances 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の構造に関し、特にBiCMO8型
半導体装置の電気的特性を改善するための構造に関する
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a semiconductor device, and particularly to a structure for improving the electrical characteristics of a BiCMO8 type semiconductor device.
この種の半導体装置の従来例を第2図(a)。 FIG. 2(a) shows a conventional example of this type of semiconductor device.
(b)を用いて説明する。まず、第2図(a)に示した
ようにシリコンからなるP型半導体基板201に公知の
手段によりN型埋込層202、P型埋込層203を形成
した後に、N型エピタキシャル層204を積層する。次
に第2図(b)に示したようにN型埋込層202上にN
型ウェル205、P型埋込層203上にP型ウェル20
6を形成し、選択酸化法によりフィールド酸化膜207
を設ける。This will be explained using (b). First, as shown in FIG. 2(a), an N-type buried layer 202 and a P-type buried layer 203 are formed on a P-type semiconductor substrate 201 made of silicon by known means, and then an N-type epitaxial layer 204 is formed. Stack. Next, as shown in FIG. 2(b), N
type well 205, P type well 20 on the P type buried layer 203
6 is formed, and a field oxide film 207 is formed by selective oxidation method.
will be established.
この後、公知の手段によりゲート酸化膜208、多結晶
シリコンによるゲート電極209、P型ソース・ドレイ
ン領域210、図には示していないN型ソース・ドレイ
ン領域、バイポーラトランジスタのコレクタ抵抗低減用
の高濃度N型領域211、ベース用P型領域212、層
間絶縁用の酸化膜213、多結晶シリコンを用いたバイ
ポーラトランジスタのエミッタ電極214、エミッタ用
のN型領域215を形成する。次に層間絶縁膜、コンタ
クト部開口、配線用アルミ電極の形成等を行なえば半導
体装置が完成する。Thereafter, by known means, a gate oxide film 208, a gate electrode 209 made of polycrystalline silicon, a P-type source/drain region 210, an N-type source/drain region (not shown in the figure), and a height for reducing the collector resistance of the bipolar transistor are formed. A doped N-type region 211, a P-type region 212 for a base, an oxide film 213 for interlayer insulation, an emitter electrode 214 of a bipolar transistor using polycrystalline silicon, and an N-type region 215 for an emitter are formed. Next, the semiconductor device is completed by forming an interlayer insulating film, contact openings, aluminum electrodes for wiring, etc.
上述した従来の半導体装置は不純物濃度101016a
to/cnt程度のP型半導体基板に高濃度(10”〜
10 ”atoms/cnt)のN型埋込層を形成して
いるため1μm程度の空乏層がP型半導体基板とN型埋
込層の間で広がっている。高濃度N型埋込層のため空乏
層の幅が狭く、寄生容量成分が生じるため信号伝達の遅
延時間を増加させる原因の一つとなっている。The conventional semiconductor device described above has an impurity concentration of 101016a.
High concentration (10”~
Since an N-type buried layer of 10" atoms/cnt) is formed, a depletion layer of about 1 μm spreads between the P-type semiconductor substrate and the N-type buried layer. Because of the highly concentrated N-type buried layer, The width of the depletion layer is narrow and a parasitic capacitance component is generated, which is one of the causes of increasing signal transmission delay time.
本発明の半導体装置はP型半導体基板に設けた高濃度の
N型埋込層と、N型埋込層の底部に設けた低濃度のN型
領域と、N型埋込層の上部に形成したN型ウェルとを有
している。このため埋込層部の寄生容量が減り、信号伝
達遅延時間を低減することができる。The semiconductor device of the present invention includes a highly doped N-type buried layer provided in a P-type semiconductor substrate, a lightly doped N-type region provided at the bottom of the N-type buried layer, and a lightly doped N-type region formed on the top of the N-type buried layer. It has an N-type well. Therefore, the parasitic capacitance of the buried layer portion is reduced, and the signal transmission delay time can be reduced.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図(a)、 (b)は本発明の一実施例の縦断面図
である。FIGS. 1(a) and 1(b) are longitudinal sectional views of an embodiment of the present invention.
まず、第1図(a)に示したようにシリコンからなる抵
抗率10〜14Ω・印のP型半導体基板101の一生面
上に図には示していない表面保護用酸化膜を20〜40
nmの厚さに形成した後にイオン注入法を用いてリンを
1013〜I O”atoms/ cntの濃度で導入
し、1000℃程度の熱処理により低濃度N型領域12
0を形成する。次にイオン注入法によりヒ素を10 ′
5〜101aatoms/ cntの濃度で導入し、1
OOO℃程度の熱処理により高濃度のN型埋込層102
を形成する。この場合、ヒ素を拡散させるための熱処理
により先に導入したリンの拡散も進行するため、低濃度
N型領域120が広がり過ぎないようにリン注入後の熱
処理時間を適当に調節する必要がある。次にイオン注入
法によりポロンを1013〜10 ”atoms/cn
iの濃度で導入し、熱処理を行なってP型埋込層103
を形成する。この後、表面保護用酸化膜を除去し、N型
エピタキシャル層104を1〜2μmの厚さに形成する
。次に第1図(b)に示したように埋込層の形成と同様
の手段により1012〜10101sato/crAの
リンおよび1013〜1014atoms/cnfのポ
ロンを導入してN型ウェル105とP型ウェル106を
埋込層上に形成し、選択酸化法によりフィールド酸化膜
107を500〜600nmの厚さに設ける。この後、
公知の手段により15〜30nm厚のゲート酸化膜10
8、多結晶シリコンによるゲート電極109.P型ソー
ス・ドレイン領域110、図には示していないN型ソー
ス・ドレイン領域、バイポーラトランジスタのコレクタ
用の高濃度N型領域111、ベース用P型領域工12、
層間絶縁用の酸化膜113、多結晶シリコンを用いたバ
イポーラトランジスタのエミッタ電極114、エミッタ
用のN型領域115を形成する。しかる後に層間絶縁膜
、コンタクト部開口、配線用アルミ電極の形成等を行な
えば半導体装置が完成する。First, as shown in FIG. 1(a), a surface protective oxide film (not shown in the figure) of 20 to 40 Ω is coated on the whole surface of a P-type semiconductor substrate 101 made of silicon and having a resistivity of 10 to 14 Ω.
After forming the N-type region 12 nm thick, phosphorus is introduced at a concentration of 1013 to 10" atoms/cnt using an ion implantation method, and a low concentration N-type region 12 is formed by heat treatment at about 1000°C.
form 0. Next, 10' of arsenic was added using the ion implantation method.
Introduced at a concentration of 5-101 aatoms/cnt, 1
A high concentration N-type buried layer 102 is formed by heat treatment at about OOO°C.
form. In this case, since the heat treatment for diffusing arsenic also progresses the diffusion of the previously introduced phosphorus, it is necessary to appropriately adjust the heat treatment time after the phosphorus implantation so that the low concentration N-type region 120 does not spread too much. Next, poron was implanted at 1013 to 10 ”atoms/cn by ion implantation method.
P-type buried layer 103 is introduced at a concentration of i and subjected to heat treatment.
form. Thereafter, the surface protective oxide film is removed, and an N-type epitaxial layer 104 is formed to a thickness of 1 to 2 μm. Next, as shown in FIG. 1(b), phosphorus at 1012 to 10101 sato/crA and poron at 1013 to 1014 atoms/cnf are introduced into the N-type well 105 and the P-type well by the same means as for forming the buried layer. 106 is formed on the buried layer, and a field oxide film 107 with a thickness of 500 to 600 nm is provided by selective oxidation. After this,
A gate oxide film 10 with a thickness of 15 to 30 nm is formed by known means.
8. Gate electrode 109 made of polycrystalline silicon. P-type source/drain region 110, N-type source/drain region (not shown), high concentration N-type region 111 for collector of bipolar transistor, P-type region for base 12,
An oxide film 113 for interlayer insulation, an emitter electrode 114 of a bipolar transistor using polycrystalline silicon, and an N-type region 115 for an emitter are formed. Thereafter, an interlayer insulating film, contact openings, wiring aluminum electrodes, etc. are formed, and the semiconductor device is completed.
本発明の別の実施例を次に説明する。Another embodiment of the invention will now be described.
前述の実施例と同様にP型半導体基板に低濃度のN型領
域、高濃度のN型埋込層を形成した後にP型のエピタキ
シャル層を形成する。この後、N型埋込層上にN型ウェ
ルを形成し、MOS)ランジスタおよびバイポーラトラ
ンジスタの形成を同様に行なう。この場合、P型埋込層
とP型ウェルが不要となるため、工程を大幅に減らすこ
とが可能となる。As in the previous embodiment, after forming a lightly doped N-type region and a heavily doped N-type buried layer in a P-type semiconductor substrate, a P-type epitaxial layer is formed. Thereafter, an N-type well is formed on the N-type buried layer, and MOS transistors and bipolar transistors are formed in the same manner. In this case, since the P-type buried layer and the P-type well are not required, the number of steps can be significantly reduced.
以上説明したように本発明はP型半導体基板と高濃度N
型埋込層の間に低濃度N型領域を設けることにより、空
乏層による寄生容量を減らし、信号伝達速度を速くする
ことができる。As explained above, the present invention utilizes a P-type semiconductor substrate and a high concentration N.
By providing a lightly doped N-type region between the type buried layers, parasitic capacitance due to the depletion layer can be reduced and signal transmission speed can be increased.
第1図(a)、 (b)は本発明の実施例の縦断面図、
第2図(a)、 (b)は従来例の縦断面図である。
101.201・・・・・・P型半導体基板、102゜
202・・・・・・N型埋込層、103,203・・・
・・・P型埋込層、104,204・・・・・・N型エ
ピタキシャル層、105,205・・・・・・N型ウェ
ル、106゜206・・・・・・P型ウェル、120・
・・・・・低濃度N型領域、109,209・・・・・
・ゲート電極、114゜214・・・・・・エミッタ電
極。FIGS. 1(a) and 1(b) are longitudinal sectional views of an embodiment of the present invention,
FIGS. 2(a) and 2(b) are longitudinal sectional views of a conventional example. 101.201...P-type semiconductor substrate, 102°202...N-type buried layer, 103,203...
...P type buried layer, 104,204...N type epitaxial layer, 105,205...N type well, 106°206...P type well, 120・
...Low concentration N-type region, 109,209...
・Gate electrode, 114°214...Emitter electrode.
Claims (1)
電型の高不純物密度の第1半導体領域と、該第1半導体
領域を内部に含むように設けた第2導電型の低不純物密
度の第2半導体領域と、前記第1導電型半導体基板上に
設けたエピタキシャル層と、前記第1半導体領域の少な
くとも1つに接するように前記エピタキシャル層内に形
成した第2導電型の第3半導体領域とを含むことを特徴
とする半導体装置。A first semiconductor region of a second conductivity type with a high impurity density provided in at least a portion of a first conductivity type semiconductor substrate; a second semiconductor region, an epitaxial layer provided on the first conductivity type semiconductor substrate, and a third semiconductor region of a second conductivity type formed in the epitaxial layer so as to be in contact with at least one of the first semiconductor region. A semiconductor device comprising:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21792489A JPH0380565A (en) | 1989-08-23 | 1989-08-23 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21792489A JPH0380565A (en) | 1989-08-23 | 1989-08-23 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0380565A true JPH0380565A (en) | 1991-04-05 |
Family
ID=16711865
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21792489A Pending JPH0380565A (en) | 1989-08-23 | 1989-08-23 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0380565A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100448085B1 (en) * | 1997-05-21 | 2004-12-03 | 삼성전자주식회사 | Semiconductor device with reduced parasitic capacitance of pad to improve input impedance characteristic when high frequency signal is inputted or outputted in analog integrated circuit |
-
1989
- 1989-08-23 JP JP21792489A patent/JPH0380565A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100448085B1 (en) * | 1997-05-21 | 2004-12-03 | 삼성전자주식회사 | Semiconductor device with reduced parasitic capacitance of pad to improve input impedance characteristic when high frequency signal is inputted or outputted in analog integrated circuit |
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