JPH0380361B2 - - Google Patents
Info
- Publication number
- JPH0380361B2 JPH0380361B2 JP11324482A JP11324482A JPH0380361B2 JP H0380361 B2 JPH0380361 B2 JP H0380361B2 JP 11324482 A JP11324482 A JP 11324482A JP 11324482 A JP11324482 A JP 11324482A JP H0380361 B2 JPH0380361 B2 JP H0380361B2
- Authority
- JP
- Japan
- Prior art keywords
- diodes
- strip line
- diode
- micro
- bias
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004020 conductor Substances 0.000 claims description 11
- 239000003990 capacitor Substances 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 description 17
- 238000006243 chemical reaction Methods 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Junction Field-Effect Transistors (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Description
【発明の詳細な説明】
発明の技術分野
本発明は、例えばGaAs−FET等の半導体デバ
イスに於ける特性を測定する際に使用して好適な
スタブ・チユーナに関する。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a stub tuner suitable for use in measuring characteristics of semiconductor devices such as GaAs-FETs.
従来技術と問題点
一般に、GaAs−FET等の半導体デバイスに於
ける出力パワー、利得、雑音等の特性測定には該
半導体デバイスと測定器等を接続する為のスタ
ブ・チユーナを必要とする。Prior Art and Problems Generally, in order to measure the characteristics of semiconductor devices such as GaAs-FETs, such as output power, gain, and noise, a stub tuner is required to connect the semiconductor device to a measuring instrument, etc.
第１図は、従来のスタブ・チユーナの説明図で
あつて、１はスタブ・チユーナ、１Ａは同軸ケー
ブルの内導体、１Ｂはスタブ、２は同軸ケーブ
ル、３は同軸コネクタ、４は変換治具、５はマイ
クロ・ストリツプ線路型チツプ・キヤリヤ、６は
半導体チツプをそれぞれ示す。 FIG. 1 is an explanatory diagram of a conventional stub tuner, in which 1 is a stub tuner, 1A is an inner conductor of a coaxial cable, 1B is a stub, 2 is a coaxial cable, 3 is a coaxial connector, and 4 is a conversion jig. , 5 represents a micro-strip line type chip carrier, and 6 represents a semiconductor chip.
この従来例では、スタブ１Ｂを機械的に移動さ
せてチユーニングを行うようにしているが、種々
の欠点を持つている。 In this conventional example, tuning is performed by mechanically moving the stub 1B, but it has various drawbacks.
例えば、コネクタ部分が同軸型であるから、マ
イクロ・ストリツプ線路型のチツプ・キヤリヤ５
と直に接続することができず、図に見られるよう
に、同軸コネクタ３とチツプ・キヤリヤ５との間
に同軸ケ−ブルからマイクロ・ストリツプ線路へ
の変換治具４を用いなければならない。また、変
換治具４使用すれば、多かれ少なかれ必ず不整合
が発生するので、電力の反射及び損失は避けられ
ず、半導体デバイスと50〔Ω〕ソースとの間のイ
ンピーダンス比が大きい場合にはチユーニング損
失の増大を招来する。更にまた、チユーニングは
スタブ１Ｂを機械的にスライドして行うので、微
細なインピーダンスの制御を必要とする際には操
作性の面で限界がある。 For example, since the connector part is a coaxial type, a micro strip line type chip carrier 5
As shown in the figure, a coaxial cable to micro strip line conversion jig 4 must be used between the coaxial connector 3 and the chip carrier 5. Furthermore, if the conversion jig 4 is used, a mismatch will more or less always occur, so reflection and loss of power are unavoidable, and if the impedance ratio between the semiconductor device and the 50 [Ω] source is large, tuning This will lead to increased losses. Furthermore, since tuning is performed by mechanically sliding the stub 1B, there is a limit in terms of operability when fine impedance control is required.
発明の目的
本発明は、低損失で、マイクロ・ストリツプ線
路型チツプ・キヤリヤに結合するのが容易である
スタブ・チユーナを提供するものである。OBJECTS OF THE INVENTION The present invention provides a stub tuner that has low losses and is easy to couple to a micro-stripline chip carrier.
発明の実施例
第２図は、本発明一実施例の要部切断斜面図で
ある。Embodiment of the Invention FIG. 2 is a cutaway perspective view of essential parts of an embodiment of the invention.
図に於いて、１０は例えばGaAsからなる半絶
縁性基板、１１，１２，１３，１４は二酸化シリ
コン膜等の誘導体膜、１５，１６，１７，１８，
１９はマイクロ・ストリツプ線路、２０，２１，
２２は例えばGaAsからなるｎ型半導体領域（活
性層）、２３，２４，２５は例えばGaAsからな
るn+型半導体領域（アノード）、２６，２７，２
８は例えばアルミニウムからなるカソード電極、
２９はn+型半導体領域２３，２４，２５の下に
形成されたバイア（via）・ホールと呼ばれている
貫通孔に充填された金（Au）等の導体、３０は
導体２９と接続されている接地導体、３１はスト
リツプ線路、３２は高周波バイパス用コンデンサ
をそれぞれ示している。 In the figure, 10 is a semi-insulating substrate made of, for example, GaAs, 11, 12, 13, 14 are dielectric films such as silicon dioxide films, 15, 16, 17, 18,
19 is a micro strip line, 20, 21,
22 is an n-type semiconductor region (active layer) made of, for example, GaAs; 23, 24, 25 are n + -type semiconductor regions (anode) made of, for example, GaAs; 26, 27, 2
8 is a cathode electrode made of aluminum, for example;
29 is a conductor such as gold (Au) filled in through-holes called vias formed under the n + type semiconductor regions 23, 24, and 25, and 30 is connected to the conductor 29. 31 is a strip line, and 32 is a high frequency bypass capacitor.
本実施例に於いて、カソード電極２６，２７，
２８はｎ型半導体領域２０，２１，２２にシヨツ
トキ・コンタクトしているので、そこにはシヨツ
トキ・ダイオードＤ１，Ｄ２，Ｄ３が形成されて
いる。このシヨツトキ・ダイオードはλ／４の距
離をおいて配置されている。そして、カソード電
極２６，２７，２８はマイクロ・ストリツプ線路
１５乃至１９の内１６，１７，１８の部分に接続
され、活性層であるｎ型半導体領域２０，２１，
２２はアノードであるn+型半導体領域２３，２
４，２５及び導体２９を介して接地導体３０に接
続されている。この構成に依るとダイオードＤ
１，Ｄ２，Ｄ３の直列抵抗分は極めて小さくな
り、従つて、該ダイオードＤ１，Ｄ２，Ｄ３での
電力損失は低減される。 In this embodiment, the cathode electrodes 26, 27,
Since 28 is in shot contact with the n-type semiconductor regions 20, 21, and 22, shot diodes D1, D2, and D3 are formed there. The shot diodes are placed at a distance of λ/4. The cathode electrodes 26, 27, 28 are connected to portions 16, 17, 18 of the micro strip lines 15 to 19, and the n-type semiconductor regions 20, 21, which are active layers,
22 is an n + type semiconductor region 23, 2 which is an anode.
4, 25 and a ground conductor 30 via a conductor 29. According to this configuration, the diode D
The series resistance of diodes D1, D2, and D3 becomes extremely small, and therefore the power loss in the diodes D1, D2, and D3 is reduced.
さて、本実施例に於いて、ダイオードＤ１乃至
Ｄ３に印加する電圧を適宜変化させて容量を制御
すると、マイクロ・ストリツプ線路１５から１９
に至るまでのリアクタンスが制御されることにな
り、それに依りチユーニングをとることができ
る。即ち、ダイオードＤ１乃至Ｄ３はスタブの役
割をはたしている。これら、ダイオードＤ１乃至
Ｄ３に電圧を印加するには、λ／４共振器を構成
しているストリツプ線路３１及びコンデンサ３２
からなるバイアス回路を介して行うようになつて
いる。尚、電圧は、電源（図示せず）から高周波
バイパス用コンデンサ３２の上側電極に印加され
るようになつている。また、測定すべき半導体デ
バイスにバイアス電圧を供給する回路も前記の如
き共振器となつている。第３図は前記実施例の３
スタブ・チユーナを用いた測定治具の要部斜面図
である。 Now, in this embodiment, if the capacitance is controlled by appropriately changing the voltage applied to the diodes D1 to D3, the micro strip lines 15 to 19
The reactance up to this point is controlled, and tuning can be achieved accordingly. That is, the diodes D1 to D3 serve as stubs. In order to apply voltage to these diodes D1 to D3, a strip line 31 and a capacitor 32 constituting a λ/4 resonator are required.
This is done via a bias circuit consisting of: Note that the voltage is applied to the upper electrode of the high frequency bypass capacitor 32 from a power source (not shown). Further, the circuit for supplying a bias voltage to the semiconductor device to be measured is also a resonator as described above. Figure 3 shows the third example of the above embodiment.
FIG. 2 is a perspective view of a main part of a measurement jig using a stub tuner.
図に於いて、３３は銅製の基台、３４は基台３
３に搭載したスタブ・チユーナ、３５は測定すべ
き半導体デバイスをそれぞれ示す。 In the figure, 33 is the copper base, 34 is the base 3
3 is a stub tuner mounted thereon, and 35 is a semiconductor device to be measured.
この測定治具に依れば、半導体デバイス３５に
対する入出力のチユーニングを容易に行うことが
でき、そして、チユーニングは半導体デバイス３
５のごく近傍で行なわれるので、電力の損失は極
めて少ない。 According to this measurement jig, input/output tuning to the semiconductor device 35 can be easily performed, and the tuning can be performed easily.
5, the power loss is extremely small.
本発明に於いては、種々の改変をすることがで
き、例えば、シヨツトキ・ダイオードＤ１乃至Ｄ
３をpn接合ダイオードに代替するなどは任意で
ある。 Various modifications can be made to the present invention, for example, the shot diodes D1 to D
It is optional to replace 3 with a pn junction diode.
発明の効果
本発明に依るスタブ・チユーナに於いては、半
絶縁性基板上に略λ／４の距離をおいて形成され
た３個のダイオード、該各ダイオードの一方の電
極に結合されて延在するマイクロ・ストリツプ線
路、該各ダイオードの他方の側と前記基板に形成
された貫通孔を埋める導体を介して結合された接
地導体膜、前記各ダイオードに接続されてバイア
ス電圧を印加する為のストリツプ線路並びに高周
波バイパス用コンデンサからなる複数のバイアス
回路、前記各ダイオードにそれぞれ独立のバイア
ス電圧を印加する為に隣接する前記バイアス回路
間の前記マイクロ・ストリツプ線路に設けられた
電流直流成分カツト用コンデンサを備える構成に
なつていて、各ダイオードに印加される電圧を制
御して容量を変え、それに依り、前記マイクロ・
ストリツプ線路のリアクタンスを変化させチユー
ニングをとるものであり、測定すべき半導体デバ
イスとスタブ・チユーナのマイクロ・ストリツプ
線路とは直に接続できるので従来技術に於けるよ
うな変換治具を必要とせず、電力の反射及び損失
は極めて少ない。Effects of the Invention In the stub tuner according to the present invention, three diodes are formed on a semi-insulating substrate at a distance of approximately λ/4, and the diodes are coupled to one electrode of each diode. a ground conductor film connected to the other side of each of the diodes via a conductor filling the through hole formed in the substrate; A plurality of bias circuits consisting of strip lines and high-frequency bypass capacitors, and a current DC component cutting capacitor provided on the micro strip line between adjacent bias circuits in order to apply independent bias voltages to each of the diodes. The capacitance is changed by controlling the voltage applied to each diode, thereby controlling the micro-
Tuning is achieved by changing the reactance of the strip line, and since the semiconductor device to be measured and the micro strip line of the stub tuner can be directly connected, there is no need for a conversion jig as in conventional technology. Power reflections and losses are extremely low.
そして、チユーニングはダイオードに印加する
電圧を制御するだけで良いから、簡単であるとと
もに微細なインピーダンス制御を必要とする際の
操作性が良好である。 Since tuning only requires controlling the voltage applied to the diode, it is simple and has good operability when fine impedance control is required.
第１図は従来例の説明図、第２図は本発明一実
施例の要部切断斜面図、第３図は第２図実施例を
用いた測定治具の要部斜面図である。
図に於いて、１０は半絶縁性基板、１１，１
２，１３，１４は誘電体膜、１５，１６，１７，
１８，１９はマイクロ・ストリツプ線路、２０，
２１，２２はｎ型半導体領域、２３，２４，２５
n+型半導体領域、２６，２７，２８はカソード
電極、２９は導体、３０は接地導体、３１はスト
リツプ線路、３２は高周波バイパス用コンデン
サ、Ｄ１，Ｄ２，Ｄ３はダイオードである。
FIG. 1 is an explanatory diagram of a conventional example, FIG. 2 is a cutaway perspective view of a main part of an embodiment of the present invention, and FIG. 3 is a perspective view of a main part of a measuring jig using the embodiment shown in FIG. In the figure, 10 is a semi-insulating substrate, 11, 1
2, 13, 14 are dielectric films, 15, 16, 17,
18, 19 are micro strip lines, 20,
21, 22 are n-type semiconductor regions, 23, 24, 25
n + -type semiconductor regions, 26, 27, and 28 are cathode electrodes, 29 is a conductor, 30 is a ground conductor, 31 is a strip line, 32 is a capacitor for high frequency bypass, and D1, D2, and D3 are diodes.
Claims (1)
成された３個のダイオード、 該各ダイオードの一方の電極に結合されて延在
するマイクロ・ストリツプ線路、 該各ダイオードの他方の側と前記基板に形成さ
れた貫通孔を埋める導体を介して結合された接地
導体膜、 前記各ダイオードに接続されてバイアス電圧を
印加する為のストリツプ線路並びに高周波バイパ
ス用コンデンサからなる複数のバイアス回路、 前記各ダイオードにそれぞれ独立のバイアス電
圧を印加する為に隣接する前記バイアス回路間の
前記マイクロ・ストリツプ線路に設けられた電流
直流成分カツト用コンデンサ を備えてなることを特徴とするスタブ・チユー
ナ。[Scope of Claims] 1. Three diodes formed on a semi-insulating substrate at a distance of approximately λ/4; a micro-strip line connected to one electrode of each diode and extending; A ground conductor film connected to the other side of each diode via a conductor filling the through hole formed in the substrate, a strip line connected to each diode to apply a bias voltage, and a high frequency bypass capacitor. a plurality of bias circuits, comprising a current DC component cutting capacitor provided on the micro-strip line between adjacent bias circuits in order to apply independent bias voltages to each of the diodes. Stub Chiyuna.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11324482A JPS593372A (en) | 1982-06-30 | 1982-06-30 | Stub tuner |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11324482A JPS593372A (en) | 1982-06-30 | 1982-06-30 | Stub tuner |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS593372A JPS593372A (en) | 1984-01-10 |
| JPH0380361B2 true JPH0380361B2 (en) | 1991-12-24 |
Family
ID=14607217
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11324482A Granted JPS593372A (en) | 1982-06-30 | 1982-06-30 | Stub tuner |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS593372A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006064543A (en) * | 2004-08-26 | 2006-03-09 | Kyocera Corp | Tuner for load-pull or source-pull measurement |
-
1982
- 1982-06-30 JP JP11324482A patent/JPS593372A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS593372A (en) | 1984-01-10 |
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