JPH0378351U - - Google Patents

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Publication number
JPH0378351U
JPH0378351U JP13943289U JP13943289U JPH0378351U JP H0378351 U JPH0378351 U JP H0378351U JP 13943289 U JP13943289 U JP 13943289U JP 13943289 U JP13943289 U JP 13943289U JP H0378351 U JPH0378351 U JP H0378351U
Authority
JP
Japan
Prior art keywords
image data
circuit
latch circuit
response
addition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13943289U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP13943289U priority Critical patent/JPH0378351U/ja
Publication of JPH0378351U publication Critical patent/JPH0378351U/ja
Pending legal-status Critical Current

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  • Image Processing (AREA)
  • Editing Of Facsimile Originals (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案に係る画像データ処理装置のブ
ロツク構成図、第2図は同装置の動作を示すタイ
ムチヤートである。 1…画像データ処理装置、2…VRAM、3…
ラツチ回路、4…加算・平均化回路、5…画像デ
ータ選択回路、b…画素クロツク、c…入力画像
データ、d…ラツチされた画像データ、e…平均
化された画像データ、f…出力画像データ。
FIG. 1 is a block diagram of an image data processing apparatus according to the present invention, and FIG. 2 is a time chart showing the operation of the apparatus. 1... Image data processing device, 2... VRAM, 3...
Latch circuit, 4... Addition/averaging circuit, 5... Image data selection circuit, b... Pixel clock, c... Input image data, d... Latched image data, e... Averaged image data, f... Output image data.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 画素クロツクに対応して順次読み出される多値
レベルの画像データを一時記憶するラツチ回路と
、ラツチ回路に記憶された画像データと次の画像
データとを加算して平均化する加算・平均化回路
と、画素クロツクに対応して前記ラツチ回路に記
憶された画像データと前記加算・平均化回路で平
均化された画像データとを切替えて出力する画像
データ選択回路とを備えたことを特徴とする画像
データ処理装置。
A latch circuit that temporarily stores multilevel image data that is sequentially read out in response to a pixel clock, and an addition/averaging circuit that adds and averages the image data stored in the latch circuit and the next image data. , an image data selection circuit that switches and outputs the image data stored in the latch circuit and the image data averaged by the addition/averaging circuit in response to a pixel clock. Data processing equipment.
JP13943289U 1989-11-30 1989-11-30 Pending JPH0378351U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13943289U JPH0378351U (en) 1989-11-30 1989-11-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13943289U JPH0378351U (en) 1989-11-30 1989-11-30

Publications (1)

Publication Number Publication Date
JPH0378351U true JPH0378351U (en) 1991-08-08

Family

ID=31686479

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13943289U Pending JPH0378351U (en) 1989-11-30 1989-11-30

Country Status (1)

Country Link
JP (1) JPH0378351U (en)

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