JPH0376030B2 - - Google Patents
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- Publication number
- JPH0376030B2 JPH0376030B2 JP56144393A JP14439381A JPH0376030B2 JP H0376030 B2 JPH0376030 B2 JP H0376030B2 JP 56144393 A JP56144393 A JP 56144393A JP 14439381 A JP14439381 A JP 14439381A JP H0376030 B2 JPH0376030 B2 JP H0376030B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- electrode wiring
- contact
- thickness
- intermediate layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- 239000004065 semiconductor Substances 0.000 claims description 23
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 15
- 238000010438 heat treatment Methods 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 13
- 150000004767 nitrides Chemical class 0.000 claims description 12
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 229910052804 chromium Inorganic materials 0.000 claims description 3
- 229910052735 hafnium Inorganic materials 0.000 claims description 3
- 229910052758 niobium Inorganic materials 0.000 claims description 3
- 229910052715 tantalum Inorganic materials 0.000 claims description 3
- 229910052720 vanadium Inorganic materials 0.000 claims description 3
- 229910052726 zirconium Inorganic materials 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 75
- 229910000838 Al alloy Inorganic materials 0.000 description 16
- 230000004888 barrier function Effects 0.000 description 11
- 239000000463 material Substances 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 238000006243 chemical reaction Methods 0.000 description 8
- 238000000034 method Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000001556 precipitation Methods 0.000 description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000000843 powder Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000005546 reactive sputtering Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000013077 target material Substances 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000010828 elution Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
本発明は半導体装置に係り、特に半導体基板に
対しオーミツク接触あるいはシヨツトキ接触のい
ずれかが形成可能な電極を具備する半導体装置に
おける電極の改良に関する。
LSI、超LSI等の半導体装置の電極配線材料に
はAlもしくはAl合金が多く用いられている。
Alは電気抵抗が小さく、且つ半導体例えばシ
リコン（Si）とシヨツトキ接触もオーミツク接触
も可能であり、また、その接触抵抗を小さくなし
得る等の長所を有するが、その反面Siと反応し易
く、電極配線形成後のアニール工程等の加熱処理
工程において、SiがAl中に溶け出しその界面に
凹凸を生ずるとともに冷却されるとAl中へSiが
容易に析出し、その結果例えばシヨツトキ・バリ
ア・ダイオードの特性を劣化させるという問題が
ある。
このような問題点を防止するため、第１図に示
すように、Si基板１表面と二酸化シリコン
（SiO2）或いは燐シリケートガラス（PSG）等よ
りなる絶縁膜２に開口されたコンタクト窓３部に
おいてコンタクトする電極配線４を、第１のAl
層５、高融点金属層たとえばTiW層６、第２の
Al層７からなる３層構造がかねてより用いられ
ている。この従来の構造はTiWがAlともSiとも
反応しにくいことを利用したものであつて、上述
の如くTiW層６を第１及び第２のAl層５，７の
間に中間層として介在せしめることにより、Siと
反応するAlの量を第１のAl層５のみに限定し、
もつてSiの溶出とそのAl中への析出を一定量以
下に制限し得るようにしたものである。
半導体装置の電極配線を、かかる構造として、
第２のAl層７へのSiの過剰な拡散を防止するこ
とにより、前記電極配線を形成した後において
も、凡そ450〔℃〕以下の温度であれば、半導体装
置の電気的特性を劣化させることなく加熱処理を
施すことが可能となつた。
しかし昨今では、素子の微細化、高集積化につ
れて、配線層および絶縁層等がますます多層化さ
れる趨勢にある。上記配線層や絶縁層の形成時に
は加熱処理工程が付随する。そのため多層化され
るに伴つて素子に加えられる加熱処理回数が増加
し、素子の耐熱性として、少なくとも500〔℃〕の
温度にさらされても異常のないことが要請される
に至つた。
前述の従来の電極配線構造は、凡そ450〔℃〕以
下の温度であれば、半導体装置の特性を劣化させ
ることなく加熱処理を施すことが可能であるとさ
れていたが、かかる温度でも昨今のように繰り返
し加熱処理を加えた場合、或いは、500〔℃〕とい
う高温にさらした場合には、中間層がAlやSiと
反応してその障壁性を失い、前記第２（上層）の
Al層もしくはAl合金層７へのSiの過剰な拡散を
生じ、半導体装置の電気的特性が劣化してしまう
という問題点があつた。そして、ICやLSIがシヨ
ツトキ接触する電極を有するシヨツトキバリアダ
イオード等を具備するものである場合、この500
〔℃〕以上の熱処理の影響はより深刻なものとな
る。また上記TiW層６を形成するには、通常ス
パツタリング法が用いられるが、TiWは合金で
なく混合物のためTiとＷのスパツタレートが一
定でなく、またTiWの焼結体ターゲツトから微
粉末が発生飛散し、基板表面に付着する等の問題
点もあつた。
そこで本発明は上記問題点を解消して、熱処理
によるSiの析出を防止し、シヨツトキバリアダイ
オード等の電気的特性を劣化させることのない電
極配線を提供することをその目的とする。
この目的は本発明において、半導体基板に対し
オーミツク接触あるいはシヨツトキ接触のいずれ
かが形成可能な電極を具備する半導体装置におい
て、前記半導体基板上に形成された電極が、略
100〓乃至2000〓の厚さを有し前記半導体基板に
接する第１のAl層と、Ti、Ta、Ｗ、Hf、Mo、
Zr、Nb、Ｖ、Crの中から選ばれた一つの金属の
窒化物層からなり略200〓乃至2000〓の厚さを有
する中間層と、第２のAl層とを順次積層してな
る積層構造を有し、少なくとも450℃の熱処理に
耐えるように構成されてなる構成としたことによ
り達成される。
従来構造においてはTiやTiW等の高融点金属
あるいはその混合物を中間層として用いたのは、
SiおよびAlに対する固溶度が比較的小さいこと
を利用したものであつて、このことは逆に言うと
僅かではあるが反応することを意味する。450
〔℃〕以下の温度では、さらす時間が短ければ中
間層がSiやAlと反応する量はごく少ないため、
障壁として作用する。しかし加熱処理を繰り返し
たり、温度が500〔℃〕以上に高くなつた場合に
は、反応が進行し、障壁性を失うこととなる。
本発明は中間層として本質的にSiやAlと反応
しない高融点金属の窒化物を用いることにより安
定な障壁を形成したものである。
第２図は本発明の一実施例を示す要部断面図で
あつて、第１のAl層もしくはAl合金層、特にSi
を含むAl合金層５と、第２のAl層もしくはAl合
金層７の中間層１６として、従来のTiWに代え
てTi、Ta、Ｗ、Hf、Mo、Zr、Nb、Ｖ、Crの中
から選ばれた一つの金属の窒化物層１６を用いた
ことが従来と異なる。
これらの金属の窒化物はSiと合金を作らず、ま
た電極配線材料のAlとも全く反応しないので、
中間層１６をこれらの材料を用いて形成すること
により、500〔℃〕という高温下でもSiの析出量を
一定量以下に抑えることができる。
しかも、これらの金属の窒化物は、前述の加熱
処理を繰り返してもなんらAlおよびSiとの反応
が進行しないため、従来のTiWを使用した半導
体装置のような電気的特性が劣化することもなく
安定である。
さらに上記金属の窒化物層を形成するのはきわ
めて容易で、且つTiW層を形成する場合のよう
に微粉末が発生飛散して基板表面に付着すること
がない。上記金属の窒化物層は、使用する金属単
体よりなるターゲツトを用いてリアクテイブスパ
ツタ法により容易に形成し得る。上述の如くター
ゲツトは窒化物を用いることなく、所望の金属単
体により作成されたものを用い、反応槽中の雰囲
気をアルゴン（Ar）と窒素（N2）の混合雰囲気
とすればよい。
第１表は一例としてTiよりなるターゲツトを
用い、反応槽中におけるArに対するN2の分圧比
を種々選択して形成したTiNよりなる中間層１
６の、Siの析出を抑制する障壁性の良否を示す表
で、表中の温度は電極配線４を形成した後の加熱
処理温度、○印は障壁性の良好であることを、×
印は障壁性が十分でなかつたことを示す。
なお同表の試料の電極配線４の各層は、第１の
Al層５を約1000〔〓〕、TiN層１６を約1000〔〓〕、
第２のAl層７を約6500〔〓〕の厚さとした。
The present invention relates to semiconductor devices, and more particularly to improvements in electrodes in semiconductor devices that include electrodes that can form either ohmic contact or shot contact with a semiconductor substrate. Al or Al alloys are often used as electrode wiring materials for semiconductor devices such as LSIs and super LSIs. Al has the advantage of having low electrical resistance and being able to make both spot and ohmic contact with semiconductors such as silicon (Si), and the contact resistance can be made small. However, on the other hand, it easily reacts with Si and is In the heat treatment process such as the annealing process after wiring formation, Si dissolves into the Al, creating irregularities at the interface, and when cooled, Si easily precipitates into the Al, resulting in, for example, the formation of shot barrier diodes. There is a problem that the characteristics deteriorate. In order to prevent such problems, as shown in FIG. 1, contact windows 3 are opened in the surface of the Si substrate 1 and the insulating film 2 made of silicon dioxide (SiO 2 ), phosphorous silicate glass (PSG), etc. The electrode wiring 4 in contact with the first Al
layer 5, a refractory metal layer such as a TiW layer 6, a second
A three-layer structure consisting of an Al layer 7 has been used for some time. This conventional structure takes advantage of the fact that TiW hardly reacts with either Al or Si, and as mentioned above, the TiW layer 6 is interposed as an intermediate layer between the first and second Al layers 5 and 7. Therefore, the amount of Al that reacts with Si is limited to only the first Al layer 5,
This makes it possible to limit the elution of Si and its precipitation into Al to below a certain amount. The electrode wiring of a semiconductor device has such a structure,
By preventing excessive diffusion of Si into the second Al layer 7, even after the electrode wiring is formed, if the temperature is about 450 [°C] or less, the electrical characteristics of the semiconductor device will deteriorate. It became possible to perform heat treatment without any heat treatment. However, in recent years, as devices have become smaller and more highly integrated, there has been a trend toward increasing the number of interconnect layers, insulating layers, and the like. A heat treatment process is involved when forming the above-mentioned wiring layer and insulating layer. Therefore, as the number of layers increases, the number of heat treatments applied to the device increases, and the heat resistance of the device is now required to be no abnormality even when exposed to temperatures of at least 500 [° C.]. It was believed that the conventional electrode wiring structure described above could be subjected to heat treatment at temperatures below approximately 450 [°C] without deteriorating the characteristics of the semiconductor device. When repeatedly subjected to heat treatment as described above, or when exposed to a high temperature of 500 [°C], the intermediate layer reacts with Al and Si and loses its barrier properties, causing the second (upper layer) to
There was a problem in that excessive diffusion of Si into the Al layer or Al alloy layer 7 occurred, resulting in deterioration of the electrical characteristics of the semiconductor device. If the IC or LSI is equipped with a shot barrier diode, etc. that has an electrode that comes into contact with the shot, this 500
The effects of heat treatment above [°C] become more serious. In addition, sputtering is usually used to form the TiW layer 6, but since TiW is not an alloy but a mixture, the sputtering rate of Ti and W is not constant, and fine powder is generated and scattered from the TiW sintered target. However, there were also problems such as adhesion to the substrate surface. SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide an electrode wiring that prevents the precipitation of Si due to heat treatment and does not deteriorate the electrical characteristics of a shot barrier diode or the like. This object is achieved in the present invention in a semiconductor device including an electrode capable of forming either ohmic contact or shot contact with a semiconductor substrate, in which the electrode formed on the semiconductor substrate is approximately
a first Al layer having a thickness of 100〓 to 2000〓 and in contact with the semiconductor substrate; Ti, Ta, W, Hf, Mo,
A laminated layer consisting of an intermediate layer made of a nitride layer of one metal selected from Zr, Nb, V, and Cr and having a thickness of approximately 200 to 2000 mm, and a second Al layer. This is achieved by having a structure that has a structure that can withstand heat treatment of at least 450°C. In conventional structures, high-melting point metals such as Ti and TiW or their mixtures were used as the intermediate layer.
This takes advantage of the relatively low solid solubility of Si and Al, which means that they react, albeit slightly. 450
At temperatures below [℃], if the exposure time is short, the amount of reaction of the intermediate layer with Si and Al is very small.
Acts as a barrier. However, if the heat treatment is repeated or the temperature rises above 500 [°C], the reaction will proceed and the barrier properties will be lost. In the present invention, a stable barrier is formed by using a high melting point metal nitride that essentially does not react with Si or Al as an intermediate layer. FIG. 2 is a sectional view of a main part showing an embodiment of the present invention, in which the first Al layer or Al alloy layer, especially Si
As the Al alloy layer 5 including the Al alloy layer 5 and the second Al layer or the intermediate layer 16 of the Al alloy layer 7, a material selected from among Ti, Ta, W, Hf, Mo, Zr, Nb, V, and Cr is used instead of the conventional TiW. The difference from the conventional method is that a nitride layer 16 of one selected metal is used. These metal nitrides do not form alloys with Si, nor do they react at all with Al, the electrode wiring material.
By forming the intermediate layer 16 using these materials, the amount of Si precipitated can be suppressed to a certain amount or less even at a high temperature of 500 [° C.]. Furthermore, these metal nitrides do not undergo any reaction with Al and Si even after the heat treatment described above is repeated, so there is no deterioration in the electrical properties of semiconductor devices that use conventional TiW. It is stable. Furthermore, it is extremely easy to form the metal nitride layer, and unlike the case of forming a TiW layer, fine powder is not generated and scattered and attached to the substrate surface. The above metal nitride layer can be easily formed by reactive sputtering using a target made of a single metal. As mentioned above, the target may be made of a desired simple metal without using nitride, and the atmosphere in the reaction tank may be a mixed atmosphere of argon (Ar) and nitrogen (N 2 ). Table 1 shows, as an example, a target made of Ti and an intermediate layer 1 made of TiN formed by selecting various partial pressure ratios of N2 to Ar in the reaction tank.
6 is a table showing the quality of the barrier property to suppress the precipitation of Si.
The mark indicates that the barrier properties were not sufficient. Note that each layer of the electrode wiring 4 of the sample in the same table is
Al layer 5 about 1000 [〓], TiN layer 16 about 1000 [〓],
The thickness of the second Al layer 7 was approximately 6500 [〓].
【表】
上記第１表に見られるごとく、電極配線４を形
成した後に素子がさらされる温度が500〔℃〕以下
であれば、上述の反応槽雰囲気中におけるArに
対するN2分圧比を１／10以上とすればよく、ま
た上記温度が550〔℃〕以下であれば上記分圧比は
４／10以上とすればよい。但し表には記載してい
ないが、第１のAl層５の厚さが100〔〓〕より大
幅に薄くなつた場合には、上記分圧比をN2を100
％に近ずけると、中間層１６の剥離が生じ易くな
る。
このことから、第１のAl層５の厚さは実用上
100〔〓〕以上とすることが望ましい。
更に前記特許請求の範囲に記載した金属の窒化
物を直接Siとオーミツク接触せしめることは殆ん
ど不可能である。従つて電極配線４をSiとオーミ
ツク接触させるためには、Siと直接接触する部分
を、Siと良好な接触を形成する材料とする必要が
ある。第１のAl層もしくはAl合金層５はこの目
的のために設けたものであつて、コンタクト窓３
内全域にわたつて一様な接触を形成せしめるため
にも、第１のAl層もしくはAl合金層５は或る程
度の厚さを必要とする。種々検討の結果、この接
触性から見ても第１のAl層もしくはAl合金層５
の厚さは、100〔〓〕以上とすることが実用的であ
る。
このように本実施例の作成に用いた製造方法で
は、ターゲツトの材料を、形成すべき中間層１６
の材料（所定金属の窒化物）とする必要がなく、
ターゲツトの材料は金属単体とし、反応槽内雰囲
気に含まれるArとN2の比を選択してリアクテイ
ブスパツタリングを行なうことにより、所定の厚
さの第１のAl層もしくはAl合金層５上に所望金
属の窒化物よりなる中間層１６を形成し得ると共
に、該中間層１６に所望の性質を具備せしめるこ
とが可能である。しかも従来法のTiWやターゲ
ツトのように微粉末を発生することもない。
本実施例の電極配線４の構造は、上述の如く第
１のAl層もしくはAl合金層５の厚さを100〔〓〕
以上とし、且つ製造工程に若干留意することによ
り、Siの析出が制御されしかも良好な接触が得ら
れる。第３図及び第４図は本実施例の接触抵抗
が、Alよりなる電極配線と比較して遜色のない
ことを示す図で、第３図は比較に用いた試料の要
部断面図、第４図は第３図の電極配線４，４′間
の抵抗値を示す曲線図である。
試料の構造は第３図に見られる如く、Ｐ型のSi
基板１表面に短冊状のｎ型領域２０を多数形成し
（図では１個のみ示す）、該ｎ型領域２０両端部上
のSiO2膜２を選択的に除去してコンタクト窓３，
３′を設け、該コンタクト窓３，３′においてｎ型
領域２０とそれぞれ接触する電極配線４，４′を
形成したものである。電極配線４，４′の構造、
寸法及び形成方法は前記第２図のものと同じとし
た。これと比較するための試料は、図示はしてい
ないが、電極配線を通常の蒸着法によりAlのみ
で形成したことを除いて第３図の試料と全く同じ
である。
第４図の曲線Ａは、第３図の電極配線４，４′
間の抵抗値を、中間層を形成する際の反応槽内圧
力に対するN2の分圧比に対応させて示し、白丸
の点Ｂは比較試料のAlよりなる電極配線間抵抗
値を示す。なお各測定値はそれぞれ凡そ400個の
サンプルの実測値の平均値である。
図より明らかな如く、本実施例の電極配線の構
造は、Alのみよりなる電極配線と比較し、抵抗
値は若干高いが、その差は実用上何ら差しつかえ
ない程度である。また電極配線４，４′間の抵抗
値は、上述の中間層の形成工程におけるN2の分
圧比を凡そ９〔％〕以上とすればきわめて安定で
ある。この点からも本実施例の電極配線が製作容
易であることが理解されよう。
なお第１のAl層もしくはAl合金層５の厚さは、
下限については前述したが、上限は2000〔〓〕程
度とすること望ましいようである。それはシヨツ
トキ・バリア・ダイオードの電極配線を本発明に
より形成した場合には、厚さを2000〔〓〕以上と
すると、順方向電圧の立上り電圧VFがLSI製造工
程の熱サイクルにより不安定となるものが発生す
ることによる。
また熱処理の過程で第１層のAlもしくはAl合
金層に溶出するSiの量は、この第１層の厚さに依
存するのでこの点からは、良好な電気的特性の確
保される限りにおいて薄い方が好ましい。こうし
たことを考えあわせると実用的には、中間層１６
の厚さは200〜2000〔〓〕程度でなるべく薄く、第
２のAlもしくはAl合金層７は凡そ5000〔〓〕以上
とするのが望ましいようである。
以上述べた如く本実施例は中間層をTiNによ
り形成したことにより、500〔℃〕という高温にお
いても十分な障壁性を有し、そのため素子の電気
的特性も安定となる。
かかる効果は、TiNが安定な物質であつて、
高温においてもSi及びAlと反応しないことによ
る。
以上説明したごとく、本発明により半導体材料
の析出が抑制可能で且つ製作容易な電極配線を具
備する半導体装置が提供された。
なお本発明に係る電極配線上に、層間絶縁層を
介して上層配線を形成して多層配線を形成し得る
こと、また上層配線の構造及び材料等は通常用い
られるいかなるものであつてもよいこと等は特に
説明を要しないであろう。[Table] As shown in Table 1 above, if the temperature to which the element is exposed after forming the electrode wiring 4 is 500 [°C] or less, the partial pressure ratio of N2 to Ar in the reaction tank atmosphere is set to 1/ The partial pressure ratio may be 10 or more, and if the temperature is 550 [° C.] or less, the partial pressure ratio may be 4/10 or more. However, although it is not stated in the table, if the thickness of the first Al layer 5 becomes significantly thinner than 100 [〓], the above partial pressure ratio is changed to N 2 to 100
%, the intermediate layer 16 is likely to peel off. From this, the thickness of the first Al layer 5 is practically
It is desirable to set it to 100 [〓] or more. Furthermore, it is almost impossible to directly bring the metal nitride described in the claims into ohmic contact with Si. Therefore, in order to bring the electrode wiring 4 into ohmic contact with Si, the portion that directly contacts Si must be made of a material that forms good contact with Si. The first Al layer or Al alloy layer 5 is provided for this purpose, and the contact window 3
The first Al layer or Al alloy layer 5 needs to have a certain thickness in order to form a uniform contact over the entire area. As a result of various studies, we found that the first Al layer or Al alloy layer 5
It is practical to set the thickness to 100 [〓] or more. In this way, in the manufacturing method used to create this example, the target material is applied to the intermediate layer 16 to be formed.
material (nitride of a specified metal),
The target material is a single metal, and reactive sputtering is performed by selecting the ratio of Ar and N 2 contained in the atmosphere in the reaction tank to form the first Al layer or Al alloy layer 5 with a predetermined thickness. An intermediate layer 16 made of a nitride of a desired metal can be formed thereon, and the intermediate layer 16 can be provided with desired properties. Moreover, it does not generate fine powder unlike conventional methods such as TiW and targets. The structure of the electrode wiring 4 of this embodiment is such that the thickness of the first Al layer or Al alloy layer 5 is 100 [〓] as described above.
By doing the above and paying some attention to the manufacturing process, precipitation of Si can be controlled and good contact can be obtained. Figures 3 and 4 are diagrams showing that the contact resistance of this example is comparable to that of electrode wiring made of Al. Figure 3 is a sectional view of the main part of the sample used for comparison, FIG. 4 is a curve diagram showing the resistance value between the electrode wirings 4 and 4' of FIG. 3. The structure of the sample is P-type Si, as shown in Figure 3.
A large number of strip-shaped n-type regions 20 are formed on the surface of the substrate 1 (only one is shown in the figure), and the SiO 2 film 2 on both ends of the n-type regions 20 is selectively removed to form contact windows 3,
3' are provided, and electrode wirings 4, 4' are formed in contact windows 3, 3' to contact the n-type region 20, respectively. Structure of electrode wiring 4, 4',
The dimensions and forming method were the same as those shown in FIG. 2 above. Although not shown, the sample for comparison is exactly the same as the sample shown in FIG. 3, except that the electrode wiring was formed only of Al by the usual vapor deposition method. Curve A in FIG. 4 corresponds to the electrode wiring 4, 4' in FIG.
The resistance value between the two electrodes is shown in correspondence with the partial pressure ratio of N 2 to the internal pressure of the reaction tank when forming the intermediate layer, and the white circle point B shows the resistance value between the electrode wiring made of Al of the comparison sample. Note that each measured value is the average value of the actual measured values of approximately 400 samples. As is clear from the figure, the structure of the electrode wiring of this example has a slightly higher resistance value than the electrode wiring made only of Al, but the difference is of a level that does not cause any practical problems. Further, the resistance value between the electrode wirings 4 and 4' is extremely stable if the partial pressure ratio of N 2 in the above-mentioned intermediate layer formation step is approximately 9% or more. From this point as well, it will be understood that the electrode wiring of this example is easy to manufacture. The thickness of the first Al layer or Al alloy layer 5 is as follows:
The lower limit was mentioned above, but it seems desirable to set the upper limit to about 2000 [〓]. When the electrode wiring of the Schottky barrier diode is formed according to the present invention, if the thickness is 2000 mm or more, the rising voltage V F of the forward voltage becomes unstable due to the thermal cycle of the LSI manufacturing process. By something occurring. In addition, the amount of Si eluted into the first Al or Al alloy layer during the heat treatment process depends on the thickness of this first layer, so from this point of view, it is important to keep it thin as long as good electrical properties are ensured. is preferable. Considering these things, in practical terms, the middle class 16
It seems desirable that the thickness of the second Al or Al alloy layer 7 be as thin as possible, about 200 to 2000 [〓], and about 5000 [〓] or more. As described above, this embodiment has sufficient barrier properties even at a high temperature of 500 [° C.] because the intermediate layer is formed of TiN, and therefore the electrical characteristics of the device are also stable. This effect is due to the fact that TiN is a stable material and
This is because it does not react with Si and Al even at high temperatures. As described above, the present invention provides a semiconductor device having an electrode wiring that can suppress the precipitation of a semiconductor material and is easy to manufacture. Note that a multilayer wiring can be formed by forming an upper layer wiring on the electrode wiring according to the present invention via an interlayer insulating layer, and that the structure and material of the upper layer wiring may be any commonly used one. etc. do not require any particular explanation.
第１図は従来の電極配線を説明するための要部
断面図、第２図は本発明の一実施例を示す要部断
面図、第３図は本発明に係る電極配線と従来のも
のとの比較試験を行なうための試料を示す要部断
面図、第４図は上記比較試験結果を示す曲線図で
ある。
図において、１は半導体基板、２は絶縁膜、４
は電極配線、５は第１のAlもしくはAl合金より
なる層、７は第２のAlもしくはAl合金よりなる
層、１６は中間層を示す。
FIG. 1 is a cross-sectional view of a main part to explain a conventional electrode wiring, FIG. 2 is a cross-sectional view of a main part showing an embodiment of the present invention, and FIG. FIG. 4 is a sectional view of a main part showing a sample for conducting a comparative test, and FIG. 4 is a curve diagram showing the results of the above comparative test. In the figure, 1 is a semiconductor substrate, 2 is an insulating film, and 4 is a semiconductor substrate.
5 indicates an electrode wiring, 5 a first layer made of Al or an Al alloy, 7 a second layer made of Al or an Al alloy, and 16 an intermediate layer.
Claims (1)
シヨツトキ接触のいずれかが形成可能な電極を具
備する半導体装置において、 前記半導体基板１上に形成された電極４が、略
100〓乃至2000〓の厚さを有し前記半導体基板に
接する第１のAl層５と、Ti、Ta、Ｗ、Hf、Mo、
Zr、Nb、Ｖ、Crの中から選ばれた一つの金属の
窒化物層からなり略200〓乃至2000〓の厚さを有
する中間層１６と、第２のAl層７とを順次積層
してなる積層構造を有し、少なくとも450℃の熱
処理に耐えるように構成されてなることを特徴と
する半導体装置。[Scope of Claims] 1. In a semiconductor device including an electrode capable of forming either ohmic contact or shot contact with the semiconductor substrate 1, the electrode 4 formed on the semiconductor substrate 1 is approximately
A first Al layer 5 having a thickness of 100〓 to 2000〓 and in contact with the semiconductor substrate, Ti, Ta, W, Hf, Mo,
An intermediate layer 16 made of a nitride layer of one metal selected from Zr, Nb, V, and Cr and having a thickness of approximately 200 to 2000 mm and a second Al layer 7 are laminated in sequence. What is claimed is: 1. A semiconductor device having a laminated structure and configured to withstand heat treatment of at least 450°C.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14439381A JPS5844767A (en) | 1981-09-11 | 1981-09-11 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14439381A JPS5844767A (en) | 1981-09-11 | 1981-09-11 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5844767A JPS5844767A (en) | 1983-03-15 |
| JPH0376030B2 true JPH0376030B2 (en) | 1991-12-04 |
Family
ID=15361100
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14439381A Granted JPS5844767A (en) | 1981-09-11 | 1981-09-11 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5844767A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021261521A1 (en) * | 2020-06-26 | 2021-12-30 | 株式会社デンソー | Semiconductor device and manufacturing method therefor |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2018121050A (en) * | 2017-01-24 | 2018-08-02 | トヨタ自動車株式会社 | Semiconductor device and method for manufacturing the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5444866A (en) * | 1977-09-16 | 1979-04-09 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device |
-
1981
- 1981-09-11 JP JP14439381A patent/JPS5844767A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5444866A (en) * | 1977-09-16 | 1979-04-09 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021261521A1 (en) * | 2020-06-26 | 2021-12-30 | 株式会社デンソー | Semiconductor device and manufacturing method therefor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5844767A (en) | 1983-03-15 |
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