JPH0362582A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0362582A JPH0362582A JP19541789A JP19541789A JPH0362582A JP H0362582 A JPH0362582 A JP H0362582A JP 19541789 A JP19541789 A JP 19541789A JP 19541789 A JP19541789 A JP 19541789A JP H0362582 A JPH0362582 A JP H0362582A
- Authority
- JP
- Japan
- Prior art keywords
- mask
- layer
- semiconductor
- etching
- eaves
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 47
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000005530 etching Methods 0.000 claims abstract description 15
- 238000000927 vapour-phase epitaxy Methods 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 4
- 238000000034 method Methods 0.000 abstract description 39
- 238000001039 wet etching Methods 0.000 abstract description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 5
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052681 coesite Inorganic materials 0.000 abstract description 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 3
- 229910052682 stishovite Inorganic materials 0.000 abstract description 3
- 229910052905 tridymite Inorganic materials 0.000 abstract description 3
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 2
- 239000003989 dielectric material Substances 0.000 abstract description 2
- 238000000059 patterning Methods 0.000 abstract description 2
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 102100025477 GTP-binding protein Rit1 Human genes 0.000 abstract 1
- 101000574654 Homo sapiens GTP-binding protein Rit1 Proteins 0.000 abstract 1
- 239000007788 liquid Substances 0.000 abstract 1
- 238000004943 liquid phase epitaxy Methods 0.000 abstract 1
- 238000010884 ion-beam technique Methods 0.000 description 5
- 238000005253 cladding Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
- Semiconductor Lasers (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
半導体装置の製造方法に係り、特にエツチングした半導
体をＭＯＶＰＥ （有機金属気相成長法〉を用いて他の
半導体で埋め込む工程を有する光半導体装置の製造方法
に関し、
ＲＩＢＢ法でエツチングした半導体上に誘電体膜（マス
ク）の「ひさし」を形成してＭＯＶＰＥ法で埋め込み成
長を可能にすることを目的とし、半導体基板上に形成し
た半導体層上にストライブ状誘電体膜を形成し、該誘電
体膜をマスクにして反応性イオンビーム（ＲＩＢＢ）法
により前記半導体層をメサエッチングし、その後ケミカ
ルウェットエツチング法により該誘電体膜をマスクとし
て該マスク下の半導体層をエツチングし、有機金属気相
成長法により前記半導体基板及び半導体層上に他の半導
体層を形成する工程を含むことを構成とする。[Detailed Description of the Invention] [Summary] A method for manufacturing a semiconductor device, particularly a method for manufacturing an optical semiconductor device, which includes a step of burying an etched semiconductor with another semiconductor using MOVPE (metal-organic vapor phase epitaxy). Regarding this, the purpose of forming an "eaves" of a dielectric film (mask) on the semiconductor etched by the RIBB method and enabling buried growth using the MOVPE method is to strip the semiconductor layer formed on the semiconductor substrate. The semiconductor layer is mesa-etched by a reactive ion beam (RIBB) method using the dielectric film as a mask, and then the area under the mask is etched using the dielectric film as a mask by a chemical wet etching method. The method includes a step of etching the semiconductor layer and forming another semiconductor layer on the semiconductor substrate and the semiconductor layer by metal organic vapor phase epitaxy.
本発明は半導体装置の製造方法に係り、特にエツチング
した半導体をＭＯＶＰＥ （有機金属気相成長法）を用
いて他の半導体で埋め込む工程を有する光半導体装置の
製造方法に関する。The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing an optical semiconductor device that includes a step of burying an etched semiconductor with another semiconductor using MOVPE (metal organic vapor phase epitaxy).
従来、例えば、レーザー等の光半導体装置の製造におけ
る半導体の埋め込み工程は基板上に形成された半導体積
層をＳｉｎ、等の誘電体膜をマスクにしてメサ形にウェ
ットエツチングし、その後上記誘電体膜を再びマスクと
してＭＯＶＰＥ法により半導体を選択成長させていた。Conventionally, in the semiconductor embedding process in the manufacture of optical semiconductor devices such as lasers, a semiconductor stack formed on a substrate is wet-etched into a mesa shape using a dielectric film such as Sin as a mask, and then the dielectric film is etched into a mesa shape. The semiconductor was selectively grown using the MOVPE method again using the mask as a mask.
しかしながらこのメサ状のウェットエツチング工程にお
いて半導体の材料や組成によりマスク５下の最上の半導
体層：コンタクト層４が第２図に示すような安定したひ
さし形状にならなかった。However, in this mesa-shaped wet etching process, the uppermost semiconductor layer under the mask 5, the contact layer 4, did not have a stable eaves shape as shown in FIG. 2, depending on the material and composition of the semiconductor.
図中１は基板、２は活性層、３はコンタクト層である。In the figure, 1 is a substrate, 2 is an active layer, and 3 is a contact layer.
ひさしが形成されないと、ＭＯＶＰＥ法により半導体層
を選択成長させた場合、第３図に示す様にマスクの側部
に異常成長による突起１０が形成されてしまい、安定し
た形状の埋込みが出来なかった。If the eaves were not formed, when the semiconductor layer was selectively grown using the MOVPE method, as shown in FIG. 3, protrusions 10 due to abnormal growth would be formed on the sides of the mask, making it impossible to embed in a stable shape. .
また近年新しいエツチング方法として半導体の材料や組
成に関わらず再現性良くエツチングできるＲＩＢＢ （
反応性イオンビームエツチング）法が実用化された。In addition, in recent years, a new etching method, RIBB (
The reactive ion beam etching (reactive ion beam etching) method was put into practical use.
第４図にＲＩＢＢ法でメサエッチングした半導体の断面
模式図を示す。FIG. 4 shows a schematic cross-sectional view of a semiconductor mesa-etched by the RIBB method.
本工程の半導体のエツチングに応用して歩留りを向上さ
せることが要求されるがＲＩＢＢ法では第３図に示すよ
うにマスクである誘電体膜５も同時にエツチングされて
しまいＭＯＶＰＢ選択成長に必要な誘電体膜の「ひさし
」が得られない。It is required to improve the yield by applying this process to the semiconductor etching process, but in the RIBB method, as shown in FIG. The "eaves" of the body membrane cannot be obtained.
本発明はＲＩＢＢ法でエツチングした半導体上に誘電体
膜〈マスク）の「ひさし」を形成してＭＯＶＰＥ法で埋
め込み成長を可能にすることを目的とする。The object of the present invention is to form an "eaves" of a dielectric film (mask) on a semiconductor etched by the RIBB method to enable buried growth by the MOVPE method.
上記課題は本発明によれば半導体基板上に形成した半導
体層上にストライプ状誘電体膜を形成し、該誘電体膜を
マスクにして反応性イオンビーム（ＲＩＳＢ）法により
前記半導体層をメサエッチングし、その後ケミカルウェ
ットエツチング法により該誘電体膜をマスクとして該マ
スク下の半導体層をエツチングし、有機金属気相成長法
により前記半導体基板及び半導体層上に他の半導体層を
形成する工程を含むことを特徴とする半導体装置の製造
方法によって解決される。According to the present invention, the above problem can be solved by forming a striped dielectric film on a semiconductor layer formed on a semiconductor substrate, and mesa etching the semiconductor layer by a reactive ion beam (RISB) method using the dielectric film as a mask. and then etching the semiconductor layer under the mask using the dielectric film as a mask by a chemical wet etching method, and forming another semiconductor layer on the semiconductor substrate and the semiconductor layer by a metal organic vapor phase epitaxy method. The problem is solved by a method of manufacturing a semiconductor device characterized by the following.
本発明によればＲＩＢＢ法により半導体層をメサエッチ
ングした後、更に、ウェットエツチングにより誘電体膜
マスク直下の該半導体層を選択的にエツチングすること
により誘電体膜の「ひさし」の効果ＲＩＥ、イオンミリ
ングが得られるのでＭＯＶＰＢ法により他事導体層を基
板上に埋め込むことが可能となる。According to the present invention, after the semiconductor layer is mesa-etched by the RIBB method, the semiconductor layer directly under the dielectric film mask is selectively etched by wet etching, thereby creating an "eaves" effect of the dielectric film by RIE, ion etching, and so on. Since milling can be achieved, it becomes possible to embed other conductive layers on the substrate by the MOVPB method.
本発明では初めエツチングはＲＩＢＢ法により行なって
いるが他のドライエツチング等でも可能である。また本
発明に用いる半導体基板としてＩｎＰ。In the present invention, etching is initially performed by the RIBB method, but other dry etching methods may also be used. Moreover, InP is used as the semiconductor substrate used in the present invention.
ＧａＡｓ等が用いられ、また誘電体膜としては、ＳｌＯ
□。GaAs etc. are used, and the dielectric film is SlO
□.
ＳｉＮ等が用いられる。SiN or the like is used.
以下本発明の実施例を図面に基づいて説明する。 Embodiments of the present invention will be described below based on the drawings.
第１八図ないし第１Ｄ図は本発明の一実施例を説明する
ための工程断面図である。FIGS. 18 to 1D are process sectional views for explaining one embodiment of the present invention.
第１Ａ図においてｎ−１ｎｐ基板１上に、厚さ０．２−
１λ＝１．３ｐＭのＩｎＧａＡｓＰ活性層２、厚さ１．
５□□□のｐ−ＩｎＰクラッド層３、厚さ０．５−のλ
＝１．：３−のｐ−１ｎＧａＡｓＰコンタクト層４を液
相エピタキシャル法で順次成長させる。コンタクト層が
薄いと、実質的にひさしが形成されていないものと同等
になってしまう。従って、ひさしの形状を確立するため
、コンタクト層の厚みは、０．４μ以上、好ましくは、
０．５以上であることが必要である。その上に厚さ０．
２７−の５ｉ０２層をＣＶＤ法により成長した後約３−
の幅にパターニングし５ｉ０２マスク５を形成する。In FIG. 1A, on an n-1np substrate 1, a thickness of 0.2-
InGaAsP active layer 2 with 1λ=1.3 pM, thickness 1.
p-InP cladding layer 3 of 5□□□, λ of 0.5-thickness
=1. :3- p-1nGaAsP contact layer 4 is sequentially grown by liquid phase epitaxial method. If the contact layer is thin, it will be equivalent to a structure in which no eaves are substantially formed. Therefore, in order to establish the shape of the eaves, the thickness of the contact layer should be 0.4μ or more, preferably
It is necessary that it is 0.5 or more. On top of that, the thickness is 0.
After growing the 5i02 layer of 27- by CVD method, about 3-
A 5i02 mask 5 is formed by patterning to a width of .
次に第１Ｂ図に示すようにＳｉＯ□マスク５をマスクと
してＲＩＢＢ （反応性イオンビームエツチング〉法を
用いて塩素ガスでｐ−ＩｎＧａＡｓＰコンタクト層４、
ｐ−ＩｎＰクラッド層３、そしてＩｎＧａＡｓＰ活性層
２を順次エツチングする。Next, as shown in FIG. 1B, the p-InGaAsP contact layer 4 is etched with chlorine gas using the RIBB (reactive ion beam etching) method using the SiO□ mask 5 as a mask.
The p-InP cladding layer 3 and the InGaAsP active layer 2 are sequentially etched.
次に硫酸系のエツチング液を用いたウエットエッチング
により選択的にＩｎＧａＡｓＰのみの側壁を除去し片側
で約０．５角突出した５ｌＯ３誘電体膜の「ひさし」を
形成する（第１Ｃ図）。Next, by wet etching using a sulfuric acid-based etching solution, only the side walls of InGaAsP are selectively removed to form an "eaves" of the 5lO3 dielectric film that protrudes by about 0.5 angle on one side (FIG. 1C).
次にＭＯＶＰＥ法を用いてＦｅをドープした半絶縁性１
ｎＰを埋め込み成長させ電極を形成して長波長レーザ埋
め込み層を得たＣ名／Ｉ）Ｉ！ｌ）。Next, semi-insulating 1 doped with Fe using the MOVPE method
C name/I) I! NP was buried and grown to form an electrode to obtain a long wavelength laser buried layer. l).
基板材料としてはＩｎＰ系以外ＧａＡｓ、Ｓｉ等を用い
ることができ、またｐ型基板をも用いることができる。As the substrate material, other than InP-based materials such as GaAs and Si can be used, and a p-type substrate can also be used.
以上説明した様に本発明によればＲＩＢＢ法及びウェッ
トエツチングによるエツチングとＭＯＶＰＩＥ法による
基板上の埋め込み成長を併用することにより良好な「ひ
さし」状の誘電体を再現性よく形成した性能の良い半導
体装置を歩留りよく又再現性よく製造することができる
。As explained above, according to the present invention, a high-performance semiconductor can be obtained by forming a good "eaves"-shaped dielectric material with good reproducibility by using a combination of etching using the RIBB method and wet etching and buried growth on the substrate using the MOVPIE method. The device can be manufactured with good yield and reproducibility.
第１八図ないし第１Ｄ図は本発明の一実施例を説明する
ための工程断面図及び斜視図（第１Ｄ図）であり、
第２図要〜第中図は従来の技術を説明するための断面図
である。
１・・・基板（ｎ−ＩｎＰ）、 ２・・・活性層（Ｉ
ｎＧａＡｓＰ）、３・・・クラッド層（ｐ−ＩｎＰ）、
４ ・：］ンタクト層（ｐ−ＩｎＧａＡｓＰ）、５・・
・マスク（Ｓ１０２）、 ６・・・埋め込み層。Figures 18 to 1D are process sectional views and perspective views (Figure 1D) for explaining one embodiment of the present invention, and Figures 2 to 1D are for explaining the conventional technology. FIG. 1... Substrate (n-InP), 2... Active layer (I
nGaAsP), 3... cladding layer (p-InP), 4 .:] contact layer (p-InGaAsP), 5...
- Mask (S102), 6... Buried layer.
Claims (1)
誘電体膜を形成し、該誘電体膜をマスクにして前記半導
体層を異方性エッチングし、その後等方性エッチングに
より該誘電体膜をマスクとして該マスク下の半導体層を
サイドエッチングしてひさしを形成し、次いで有機金属
気相成長法により前記半導体基板及び半導体層上に他の
半導体層を形成する工程を含むことを特徴とする半導体
装置の製造方法。1. A striped dielectric film is formed on a semiconductor layer formed on a semiconductor substrate, the semiconductor layer is anisotropically etched using the dielectric film as a mask, and then the dielectric film is etched by isotropic etching. A semiconductor characterized by comprising a step of side etching a semiconductor layer under the mask as a mask to form an eaves, and then forming another semiconductor layer on the semiconductor substrate and the semiconductor layer by metal organic vapor phase epitaxy. Method of manufacturing the device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19541789A JPH0362582A (en) | 1989-07-29 | 1989-07-29 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19541789A JPH0362582A (en) | 1989-07-29 | 1989-07-29 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0362582A true JPH0362582A (en) | 1991-03-18 |
Family
ID=16340741
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19541789A Pending JPH0362582A (en) | 1989-07-29 | 1989-07-29 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0362582A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6393661A (en) * | 1986-10-07 | 1988-04-23 | 安全索道株式会社 | Cableway system |
| JP2004111918A (en) * | 2002-07-24 | 2004-04-08 | Furukawa Electric Co Ltd:The | Optical component mounter and optical module using same |
-
1989
- 1989-07-29 JP JP19541789A patent/JPH0362582A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6393661A (en) * | 1986-10-07 | 1988-04-23 | 安全索道株式会社 | Cableway system |
| JPH0544380B2 (en) * | 1986-10-07 | 1993-07-06 | Anzen Sakudo Kk | |
| JP2004111918A (en) * | 2002-07-24 | 2004-04-08 | Furukawa Electric Co Ltd:The | Optical component mounter and optical module using same |
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