JPH0358614A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0358614A JPH0358614A JP1195528A JP19552889A JPH0358614A JP H0358614 A JPH0358614 A JP H0358614A JP 1195528 A JP1195528 A JP 1195528A JP 19552889 A JP19552889 A JP 19552889A JP H0358614 A JPH0358614 A JP H0358614A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- power supply
- voltage detection
- terminal out
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 238000001514 detection method Methods 0.000 claims abstract description 21
- 230000010354 integration Effects 0.000 claims abstract description 5
- 239000003990 capacitor Substances 0.000 claims description 8
- 230000000694 effects Effects 0.000 abstract description 3
- 230000000295 complement effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Logic Circuits (AREA)
- Electronic Switches (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業」二の利用分野〕
本発明は半導体装置に係り、特に容量と抵抗とから構成
される積分回路が電源間に接続されている半導体装置に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application in Industry] The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which an integrating circuit composed of a capacitor and a resistor is connected between power supplies.
従来、この種の半導体装置は、電源間に接続された容量
と抵抗とから構成される積分回路の出力を、相補型MO
SFETで構威したインバータに接続し、電源が投入さ
れてから前記積分回路の容量への充電電圧が前記インバ
ータの論理スレッショルド電圧レベルに到達するまでの
時間Hレベル(高電位レベル)のパルスを、前記相補型
MOSFETで構成したインバータの出力より発生させ
ている。Conventionally, this type of semiconductor device uses a complementary MO
Connected to an inverter composed of SFETs, and a pulse of H level (high potential level) for a period of time from when the power is turned on until the charging voltage to the capacitor of the integrator circuit reaches the logic threshold voltage level of the inverter, It is generated from the output of an inverter made up of the complementary MOSFETs.
前述した従来の半導体装置は、積分回路から出力される
パルスで、フリップ・フロップ回路など電源投入直後に
回路状態をLレベル(低電位レベル)またはHレベル(
高電位レベル)にイニシャライズする為のイニシャライ
ス信号として、使用している。しかし、電源電圧が、重
負荷もしくは外部ノイズなどにより電源電圧のレベルが
変動した場合、この変動が電源投入直後の動作とみなさ
れ、積分回路より誤った信号が出力され、フリップフロ
ップ回路などがイニシャライズされてしまう欠点がある
。The conventional semiconductor device described above uses a pulse output from an integrating circuit to change the circuit state of a flip-flop circuit, etc. to L level (low potential level) or H level (low potential level) immediately after power is turned on.
It is used as an initialization signal to initialize to a high potential level. However, if the level of the power supply voltage fluctuates due to a heavy load or external noise, this fluctuation is considered to be an operation immediately after the power is turned on, and an incorrect signal is output from the integrator circuit, causing the flip-flop circuit etc. to initialize. There is a drawback that it can be done.
本発明の目的は、前記欠点を解決すべく、電源電圧が変
動してパルス発生回路から不必要なパルスが発生した場
合でも、フリップ・フロップ回路などに影響のないよう
に、電源電圧の変動によって発生するパルスを制御する
ようにした半導体装置を提供することにある。SUMMARY OF THE INVENTION In order to solve the above-mentioned drawbacks, an object of the present invention is to prevent fluctuations in power supply voltage from affecting flip-flop circuits, etc. even when unnecessary pulses are generated from the pulse generation circuit due to fluctuations in power supply voltage. An object of the present invention is to provide a semiconductor device in which generated pulses are controlled.
本発明の半導体装置の構成は、容量と抵抗とから構成さ
れる積分回路と、電源電圧がある電圧以上であるかどう
かを検出する電源電圧検出回路と、前記積分回路の出力
を前記電源電圧検出回路の出力によって制御する制御回
路とを備えていることを特徴とする。The semiconductor device of the present invention has a configuration including an integrating circuit composed of a capacitor and a resistor, a power supply voltage detection circuit that detects whether a power supply voltage is higher than a certain voltage, and an output of the integrating circuit that detects the power supply voltage. The present invention is characterized by comprising a control circuit that performs control based on the output of the circuit.
次に本発明を図面を参照しながら説明する。第1図は本
発明の一実施例の半導体装置を示す回路図である。Next, the present invention will be explained with reference to the drawings. FIG. 1 is a circuit diagram showing a semiconductor device according to an embodiment of the present invention.
第1図において、本実施例では、電池電源1のプラス側
を電源電圧検出回路2のa入力端子と、抵抗4の一端と
に接続する。電池電源1のマイナス側は、電源電圧検出
回路2のb入力端子と容量3の一端とに接続する。抵抗
4の他端と容量3の他端とを接続する。容量3と抵抗4
とが直列に接続された回路を積分回路5とし、この積分
回路5は抵抗4の一端と容量3の一端とを入力端子とし
、抵抗4の他端と容量3の他端とが接続されている接続
点を、積分回路5の出力端子outとする。In FIG. 1, in this embodiment, the positive side of a battery power supply 1 is connected to the a input terminal of a power supply voltage detection circuit 2 and one end of a resistor 4. The negative side of the battery power supply 1 is connected to the b input terminal of the power supply voltage detection circuit 2 and one end of the capacitor 3. The other end of the resistor 4 and the other end of the capacitor 3 are connected. capacitance 3 and resistance 4
are connected in series as an integrating circuit 5, and this integrating circuit 5 has one end of the resistor 4 and one end of the capacitor 3 as input terminals, and the other end of the resistor 4 and the other end of the capacitor 3 are connected. The connection point located there is defined as the output terminal OUT of the integrating circuit 5.
電源圧検出回路2の出力端子outは、制御回路6の入
力端子Cに接続し、積分回路5の出力端子outを制御
回路6の入力端子dに接続する。制御回路6の出力端子
outを、半導体装置の出力とする。The output terminal out of the power supply voltage detection circuit 2 is connected to the input terminal C of the control circuit 6, and the output terminal out of the integrating circuit 5 is connected to the input terminal d of the control circuit 6. The output terminal OUT of the control circuit 6 is assumed to be the output of the semiconductor device.
次に、本実施例の動作について説明する。まず、電源投
入時は積分回路5の出力端子outより、パルス信号が
出力される。電源投入直後は、電源電圧が電源電圧検出
回路2の検出電圧以下であるから、電源電圧検出回路2
の出力端子outには、例えばLレベル(低電位レベル
)が出力される。Next, the operation of this embodiment will be explained. First, when the power is turned on, a pulse signal is output from the output terminal OUT of the integrating circuit 5. Immediately after the power is turned on, the power supply voltage is lower than the detection voltage of the power supply voltage detection circuit 2, so the power supply voltage detection circuit 2
For example, an L level (low potential level) is output to the output terminal OUT.
電源電圧検出回路2の出力端子outから、Lレベル(
低電位レベル)が制御回路6に入力されると、制御回路
6の出力端子outには、入力端子dの信号即ち積分回
路5の出力パルス信号が出力される。From the output terminal out of the power supply voltage detection circuit 2, the L level (
When the low potential level) is input to the control circuit 6, the signal at the input terminal d, that is, the output pulse signal of the integrating circuit 5, is output to the output terminal OUT of the control circuit 6.
次に、電源投入中に、重負荷や外部ノイズによって電源
変動があった場合、積分回路5の出力端子outより電
源投入時と同様にパルス信号が出力される。しかし、電
源変動の範囲が電源電圧検出回路2の検出電圧以上であ
ると、電源電圧検出回路2のoutには、Hレベル(高
電位レベル)が出力される。この信号が、制御回路60
入力端子Cに入力されると、制御回路6は入力端子dの
信号を出力端子outに出力を禁止するので、制御回路
6の出力端子outにはパルス信号が出力されない。Next, if there is a power fluctuation due to a heavy load or external noise while the power is turned on, a pulse signal is output from the output terminal OUT of the integrating circuit 5 in the same way as when the power is turned on. However, if the range of power supply fluctuation is equal to or higher than the detection voltage of the power supply voltage detection circuit 2, an H level (high potential level) is output to the output of the power supply voltage detection circuit 2. This signal is transmitted to the control circuit 60
When the pulse signal is input to the input terminal C, the control circuit 6 prohibits outputting the signal of the input terminal d to the output terminal out, so that no pulse signal is output to the output terminal out of the control circuit 6.
以上説明したように、本発明は、容量と抵抗とから構威
される積分回路が電源間に接続され、電源電圧検出回路
の出力によって、積分回路の出力を制御することにより
、重負荷及び外部ノイズによる電池電源の電圧の変動の
レベルを検出し、制御信号を前記電源電圧検出回路より
出力させ、電二使一
源変動によって前記積分回路より発生する信号を無効に
させ、特にフリップ・フロップ回路など他の回路への影
響をなくすことができ、電源に対して重負荷の集積回路
に内臓でき、安定した回路動作を保証するという効果が
ある。As explained above, in the present invention, an integrating circuit composed of a capacitance and a resistor is connected between power supplies, and the output of the integrating circuit is controlled by the output of the power supply voltage detection circuit. Detects the level of fluctuation in the voltage of the battery power supply due to noise, outputs a control signal from the power supply voltage detection circuit, invalidates the signal generated by the integration circuit due to fluctuations in the power supply, and is particularly effective in flip-flop circuits. This has the effect of eliminating the influence on other circuits, such as this, and allowing it to be built into an integrated circuit with a heavy load on the power supply, ensuring stable circuit operation.
第1図は本発明の一実施例の半導体装置を示す回路図で
ある。
■・・・・・・電池電源、2・・・・・・電源電圧検出
回路、3・・・・・・抵抗、4・・・・・・容量、5・
・・山積分回路、6・・・・・・制御回路。FIG. 1 is a circuit diagram showing a semiconductor device according to an embodiment of the present invention. ■...Battery power supply, 2...Power supply voltage detection circuit, 3...Resistance, 4...Capacity, 5.
...Mountain integral circuit, 6...Control circuit.
Claims (1)
る電圧以上であるかどうかを検出する電源電圧検出回路
と、前記積分回路の出力を前記電源電圧検出回路の出力
によって制御する制御回路とを備えたことを特徴とする
有する半導体装置。an integrating circuit composed of a capacitor and a resistor; a power supply voltage detection circuit that detects whether a power supply voltage is higher than a certain voltage; and a control circuit that controls the output of the integration circuit by the output of the power supply voltage detection circuit. A semiconductor device comprising:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1195528A JPH0358614A (en) | 1989-07-27 | 1989-07-27 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1195528A JPH0358614A (en) | 1989-07-27 | 1989-07-27 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0358614A true JPH0358614A (en) | 1991-03-13 |
Family
ID=16342591
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1195528A Pending JPH0358614A (en) | 1989-07-27 | 1989-07-27 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0358614A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0667651U (en) * | 1993-03-04 | 1994-09-22 | 株式会社かな和工業 | Roof-roof joint structure |
US6388302B1 (en) * | 1999-06-22 | 2002-05-14 | Stmicroelectronics S.R.L. | Ground compatible inhibit circuit |
-
1989
- 1989-07-27 JP JP1195528A patent/JPH0358614A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0667651U (en) * | 1993-03-04 | 1994-09-22 | 株式会社かな和工業 | Roof-roof joint structure |
US6388302B1 (en) * | 1999-06-22 | 2002-05-14 | Stmicroelectronics S.R.L. | Ground compatible inhibit circuit |
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