JPH0358465A - Resin sealed type semiconductor device - Google Patents

Resin sealed type semiconductor device

Info

Publication number
JPH0358465A
JPH0358465A JP1194935A JP19493589A JPH0358465A JP H0358465 A JPH0358465 A JP H0358465A JP 1194935 A JP1194935 A JP 1194935A JP 19493589 A JP19493589 A JP 19493589A JP H0358465 A JPH0358465 A JP H0358465A
Authority
JP
Japan
Prior art keywords
power source
semiconductor device
base ribbon
metal plates
metal plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1194935A
Other languages
Japanese (ja)
Inventor
Hajime Nakamura
肇 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1194935A priority Critical patent/JPH0358465A/en
Publication of JPH0358465A publication Critical patent/JPH0358465A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Abstract

PURPOSE:To eliminate noises applied to a power source without an additional capacitor of small capacitance by a method wherein a base ribbon is formed of two metal plates which sandwich an electrical insulator between them, and the metal plates are electrically connected to positive and a negative power source terminal respectively. CONSTITUTION:Metal plates 3a and 3b are bonded together overlapping each other and interposing an insulating resin layer 6 between them to form a base ribbon, where the metal plates 3a and 3b are insulated from each other. The metal plate 3b of the base ribbon is connected to a positive power source terminal of an external terminal, and the other metal plate 3a is connected to a negative power source terminal with a bonding wire 5. A semiconductor chip 1 is mounted on the base ribbon 3a and connected to the external terminal with bonding wires 4, which is sealed up with a molding resin 2. By this setup, noises applied to a power source can be removed without an additional capacitor of small capacitance.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は樹脂封止型半導体装置に関し、特に半導体チッ
プを搭載するベースリボンの構造に関する． 〔従来の技術〕 従来の樹脂封止型半導体装置は、第２図に示すように、
半導体チップ１を搭載するベースリボン３が１枚の金属
板からなっていた。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a resin-sealed semiconductor device, and particularly to the structure of a base ribbon on which a semiconductor chip is mounted. [Prior Art] A conventional resin-sealed semiconductor device, as shown in FIG.
A base ribbon 3 on which a semiconductor chip 1 is mounted is made of one metal plate.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の樹脂封止型半導体装置は、電源間（プラ
ス電源とマイナス電源間）にコンデンサを内蔵していな
いため、電源に雑音が加わった場合に、誤動作し易い。The above-described conventional resin-sealed semiconductor device does not have a built-in capacitor between the power supplies (between the positive power source and the negative power source), so it is likely to malfunction when noise is added to the power source.

特に近年ＩＣの高速化に伴い、電源の微弱な雑音にも敏
感に反応し易くなっている。In particular, as ICs have become faster in recent years, they have become more sensitive to even weak noise from the power supply.

従って、通常大容量コンデンサ（数μＦ〜数百μＦ〉と
小容量コンデンサ（数十ｐＦ〜数千ｐＦ）を並列にＩＣ
電源間に付加し電源雑音を吸収するようにしている． しかし、コンデンサの取付位置が半導体装置に近くない
と、雑音除去が十分でなく、プリント板上の部品搭載面
積に余裕がない時は、コンデンサを半導体装置の近くに
取付けられず、雑音除去が不十分となってしまうという
欠点がある。Therefore, usually a large capacitor (several μF to several hundred μF) and a small capacitor (several tens of pF to several thousand pF) are connected in parallel to the IC.
It is added between the power supplies to absorb power supply noise. However, if the capacitor is not installed close to the semiconductor device, noise removal will not be sufficient, and if there is not enough area for mounting components on the printed circuit board, the capacitor cannot be installed near the semiconductor device, and noise removal will be insufficient. The disadvantage is that it becomes sufficient.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は、金属製のベースリボン上に半導体チップを搭
載してなる樹脂封止型半導体装置において、前記ベース
リボンが間に電気的絶縁物を挟んで重ね合わされた２枚
の金属板からなり、それぞれの金属板は前記半導体チッ
プのプラス電源端子及びマイナス電源端子に電気的に接
続されているというものである。The present invention provides a resin-sealed semiconductor device in which a semiconductor chip is mounted on a metal base ribbon, in which the base ribbon is composed of two metal plates stacked on top of each other with an electrical insulator in between. Each metal plate is electrically connected to a positive power terminal and a negative power terminal of the semiconductor chip.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は本発明の一実施例の縦断面図である。FIG. 1 is a longitudinal sectional view of an embodiment of the present invention.

ベースリボンは２板の金属板３ａと３ｂが絶縁性の樹脂
層６を間に挟んで重ね合わせて接着され、相互に電気的
に絶縁されている。絶縁性の樹脂層５としては例えば耐
熱性の高いポリイミド樹脂などが適当である。The base ribbon is made up of two metal plates 3a and 3b that are bonded together with an insulating resin layer 6 in between, and are electrically insulated from each other. As the insulating resin layer 5, for example, polyimide resin with high heat resistance is suitable.

なおベースボンの金属板の１枚３ｂは外部端子のブラス
（又はマイナス）電源端子に接続されており、他の金属
板３ａはボンディングワイヤ５等によりマイナス（又は
プラス）電源端子に接続する．半導体チップ１はベース
リボン上にマウントされ、ボンディングワイヤ４により
外部端子に接続した後にモールド樹脂２により封止され
、樹脂封止型半導体装置が楕戒される． 〔発明の効果〕 以上説明したように本発明は、ベースリボンを２板の金
属板を重ね合わせ相互に絶縁することでコンデンサを形
成することになり、各金属板がプラス電源端子及びマイ
ナス電源端子にそれぞれ接続されているため、半導体装
置の電源に乗った雑音が外に小容量コンデンサを付加し
なくても除去できる効果がある．また従来付加していた
小容量コンデンサが不要となるためプリント板上での実
装面積を小さくできる効果もある。Note that one metal plate 3b of the base bond is connected to a brass (or negative) power terminal of an external terminal, and the other metal plate 3a is connected to a negative (or positive) power terminal by a bonding wire 5 or the like. The semiconductor chip 1 is mounted on a base ribbon, connected to external terminals by bonding wires 4, and then sealed with a molding resin 2 to form a resin-sealed semiconductor device. [Effects of the Invention] As explained above, in the present invention, a capacitor is formed by stacking two metal plates on a base ribbon and insulating them from each other, and each metal plate has a positive power terminal and a negative power terminal. Since these are connected to each other, noise carried by the semiconductor device's power supply can be removed without adding an external small-capacity capacitor. Furthermore, since the small capacitance capacitor that was conventionally added is no longer necessary, the mounting area on the printed circuit board can be reduced.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例の縦断面図、第２図は従来例
の縦断面図である．FIG. 1 is a longitudinal sectional view of one embodiment of the present invention, and FIG. 2 is a longitudinal sectional view of a conventional example.

Claims (1)

【特許請求の範囲】[Claims] 金属製のベースリボン上に半導体チップを搭載してなる
樹脂封止型半導体装置において、前記ベースリボンが間
に電気的絶縁物を挟んで重ね合わされた２枚の金属板か
らなり、それぞれの金属板は前記半導体チップのプラス
電源端子及びマイナス電源端子に電気的に接続されてい
る事を特徴とする樹脂封止型半導体装置。In a resin-sealed semiconductor device in which a semiconductor chip is mounted on a metal base ribbon, the base ribbon is composed of two metal plates stacked on top of each other with an electrical insulator in between, and each metal plate has a A resin-sealed semiconductor device characterized in that the device is electrically connected to a positive power terminal and a negative power terminal of the semiconductor chip.
JP1194935A 1989-07-26 1989-07-26 Resin sealed type semiconductor device Pending JPH0358465A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1194935A JPH0358465A (en) 1989-07-26 1989-07-26 Resin sealed type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1194935A JPH0358465A (en) 1989-07-26 1989-07-26 Resin sealed type semiconductor device

Publications (1)

Publication Number Publication Date
JPH0358465A true JPH0358465A (en) 1991-03-13

Family

ID=16332789

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1194935A Pending JPH0358465A (en) 1989-07-26 1989-07-26 Resin sealed type semiconductor device

Country Status (1)

Country Link
JP (1) JPH0358465A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030090821A (en) * 2002-05-22 2003-12-01 (주)포베이비 Health hygienic liner for inserting vagina
WO2017159081A1 (en) * 2016-03-15 2017-09-21 住友電気工業株式会社 Semiconductor module
JP2020014377A (en) * 2019-09-04 2020-01-23 住友電気工業株式会社 Semiconductor module

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030090821A (en) * 2002-05-22 2003-12-01 (주)포베이비 Health hygienic liner for inserting vagina
WO2017159081A1 (en) * 2016-03-15 2017-09-21 住友電気工業株式会社 Semiconductor module
JP2017168582A (en) * 2016-03-15 2017-09-21 住友電気工業株式会社 Semiconductor module
JP2020014377A (en) * 2019-09-04 2020-01-23 住友電気工業株式会社 Semiconductor module

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