JPH0357226A - Insulated-gate transistor - Google Patents
Insulated-gate transistorInfo
- Publication number
- JPH0357226A JPH0357226A JP1193534A JP19353489A JPH0357226A JP H0357226 A JPH0357226 A JP H0357226A JP 1193534 A JP1193534 A JP 1193534A JP 19353489 A JP19353489 A JP 19353489A JP H0357226 A JPH0357226 A JP H0357226A
- Authority
- JP
- Japan
- Prior art keywords
- region
- emitter
- electrode
- semiconductor
- igbt
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 48
- 230000003071 parasitic effect Effects 0.000 abstract description 22
- 230000004913 activation Effects 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 230000001629 suppression Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 43
- 230000000694 effects Effects 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000006378 damage Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 241001333909 Soter Species 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は絶縁ゲート型トランジスタに関し、特に通電
能力の向上に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an insulated gate transistor, and particularly relates to an improvement in current carrying capacity.
絶縁ゲート型トランジスタの１つである、絶縁ゲート型
バイボーラトランジスタ（ＩｎｓｕｌａＬｅｄ Ｇａｔ
ｅ Ｂｉｐｏｌａｒ Ｔｒａｎｓｉｓｔｏｒ ；以下Ｉ
ＧＢＴという）は一般に多数のＩＧＥＴ素子（以下ｒＧ
ＢＴセルという）が並列接続された構造を有している。The insulated gate bibolar transistor (InsulaLed Gat) is one of the insulated gate transistors.
e Bipolar Transistor; hereinafter referred to as I
Generally, a large number of IGET elements (hereinafter referred to as rG
It has a structure in which BT cells (referred to as BT cells) are connected in parallel.
第３図は従来のＩＧＢＴを示す断面図である。FIG. 3 is a sectional view showing a conventional IGBT.
同図において、１はＰ＋コレクタ層であり、その一方主
面上にはＮ＋バッファ層２が形戊されている。Ｎ ハッ
ファ層２はＰ コレクタ層１からのホールの注入を抑制
する働きがある。In the figure, 1 is a P+ collector layer, and an N+ buffer layer 2 is formed on one main surface thereof. The N huffer layer 2 has the function of suppressing the injection of holes from the P collector layer 1.
このＮ＋バッファ層２上にＮ−ボディ層３が形成されて
おり、Ｎ ボディ層３の表面の一部領域上には、Ｐ型の
不純物を所定のパターンに従って選択的に拡散すること
によりＰベース領域４が形成されており、さらに、この
Ｐベース領域４の表面の一部領域には、高濃度のＮ型の
不純物を選択的に拡散することによりＮ＋エミッタ領域
５が形成されている。Ｎ ボディ層３の表面とＮ エミ
ッタ領域５の表面とて挟まれたＰベース領域４の表面が
チャネル領域６となり、このチャネル領域６上にゲート
絶縁膜７が形成されている。このゲー１・絶縁膜７上に
ゲート電極８が形成され、また、Ｐベース領域４の中央
部表面及びＮ＋エミッタ領域５の一部表面とに電気的接
触をして、ラッチアップ防止のためにエミッタ短路構造
をとるＮ＋エミッタ電極９か形成されている。なお、ゲ
ート電険８およびエミッタ電極９は、層間絶縁膜１０に
より絶縁分離された多層構造となっている。このように
、ゲート電極８とエミッタ電極９を多層構造にして、全
ＩＧＢＴセルに対してそれぞれの電極８．９が共通に電
気的につながった構造になっている。また、Ｐ＋コレク
タ層１の裏面にはコレクタ電極１１か全ＩＧＢＴセルに
対し一体に形成されている。このようなＮチャネル型Ｉ
ＧＢＴは基本的にはパワーＭＯＳＦＥＴのドレイン側に
Ｐ型領域を設けた構造となっている。言いかえれば第３
図のＩＧＢＴにおいて、Ｐ＋コレクタ層１とＮ＋バッフ
ァ層２がＮ＋ドレイン層に置き代ったものがパワーＭＯ
ＳＦＥＴとなる。An N- body layer 3 is formed on this N+ buffer layer 2, and a P-type impurity is selectively diffused on a part of the surface of the N-body layer 3 according to a predetermined pattern. A region 4 is formed, and an N+ emitter region 5 is further formed in a part of the surface of the P base region 4 by selectively diffusing highly concentrated N type impurities. The surface of the P base region 4 sandwiched between the surface of the N 2 body layer 3 and the surface of the N 2 emitter region 5 becomes a channel region 6 , and a gate insulating film 7 is formed on this channel region 6 . A gate electrode 8 is formed on this gate 1 insulating film 7, and is electrically contacted with the central surface of the P base region 4 and a part of the surface of the N+ emitter region 5 to prevent latch-up. An N+ emitter electrode 9 having an emitter short circuit structure is also formed. Note that the gate electrode 8 and the emitter electrode 9 have a multilayer structure insulated and separated by an interlayer insulating film 10. In this way, the gate electrode 8 and the emitter electrode 9 have a multilayer structure, and each electrode 8.9 is commonly electrically connected to all IGBT cells. Further, on the back surface of the P+ collector layer 1, a collector electrode 11 is integrally formed for all IGBT cells. Such N-channel type I
GBT basically has a structure in which a P-type region is provided on the drain side of a power MOSFET. In other words, the third
In the IGBT shown in the figure, the power MO is the one in which the P+ collector layer 1 and the N+ buffer layer 2 are replaced by the N+ drain layer.
It becomes SFET.
このような構成において、エミッタ電極９とコレクタ電
極１１との間に所定のコレクタ電圧Ｖ。１こ（コレクタ
側が正）を印加する。そして、ゲート電極８とエミッタ
電極９との間に所定のゲート電圧ｖ６Ｅ（ゲート側がＩ
′Ｅ）を印加すると、チャネル領域６がＮ型に反転する
ことにより、チャネルか形成される。In such a configuration, a predetermined collector voltage V is applied between the emitter electrode 9 and the collector electrode 11. Apply 1 (positive on the collector side). A predetermined gate voltage v6E is applied between the gate electrode 8 and the emitter electrode 9 (the gate side is I
When 'E) is applied, the channel region 6 is inverted to N type, thereby forming a channel.
このＮ型に反転したチャネル領域６を通して、Ｎ＋エミ
ッタ領域５からＮ ボディ層３にかけて電子が注入され
る。この電子の注入に伴い、１・ランジスタの増幅作用
によりＰ＋コレクタ層１からＮ−ボディ層３への多量な
ホールの注入が起こる。Electrons are injected from the N+ emitter region 5 to the N2 body layer 3 through this channel region 6 which has been inverted to N type. Along with this injection of electrons, a large amount of holes are injected from the P+ collector layer 1 to the N- body layer 3 due to the amplification effect of the 1 transistor.
このようにＩ ＧＢＴはバイボーラ的動作をするため、
伝導度変調の効果からＮ−ボディ層３の抵抗が大幅に低
下する。Ｎ ボディ層３の抵抗値はＩＧＢＴあるいはパ
ワーＭＯＳＦＥＴのオン抵抗を決定する主要因であるた
め、Ｉ ＧＢＴは従来のパワーＭＯＳＦＥＴに比べて低
いオン電圧、大きい電流容量を実現できる利点がある。In this way, since the IGBT operates in a bibolar manner,
The resistance of the N-body layer 3 is significantly reduced due to the effect of conductivity modulation. Since the resistance value of the N body layer 3 is the main factor determining the on-resistance of the IGBT or power MOSFET, the IGBT has the advantage of being able to realize a lower on-voltage and a larger current capacity than conventional power MOSFETs.
しかしながら、第３図により明らかなように、ＩＧＢＴ
にはＮ＋エミッタ領域５，Ｐベース賄域４， Ｎ ボ
ディ層３およびＰ＋コレクタ層１よりＩ［３成される寄
生サイリスクが存花する。However, as is clear from Figure 3, IGBT
There exists a parasitic silicon risk formed by I[3 from the N+ emitter region 5, the P base covering region 4, the N body layer 3, and the P+ collector layer 1.
ＩＧＢＴを流れる主電流である、コレクタ電流■ｃが増
大するに伴い、Ｎ ボディ層３からＰベース領域４に流
れるホール電流も増大する。そしで、コレクタ電流■
がラッチアップ電流Ｉ１、をＣ
越えると、Ｎ＋エミッタ領域５直下のＰベース領域４を
流れるホール電流がＰベース領域４の抵抗分のために生
じる電圧降下により、Ｎ＋エミッタ領域５，Ｐベース領
域４， Ｎ ボディ層３から成るＮＰＮ寄生トランジ
スタがオンし、前述した寄ｌＬサイリスタがオンする。As the collector current (c), which is the main current flowing through the IGBT, increases, the hole current flowing from the N body layer 3 to the P base region 4 also increases. Then, the collector current■
When C exceeds the latch-up current I1, the Hall current flowing through the P base region 4 directly below the N+ emitter region 5 causes a voltage drop caused by the resistance of the P base region 4, causing the N+ emitter region 5 and the P base region 4 to , N The NPN parasitic transistor consisting of the body layer 3 is turned on, and the aforementioned parasitic 1L thyristor is turned on.
こうしてＩ ＧＢＴはラッチアップ状態となる。一度、
寄生サイリスクがオンすると、ゲート電極８に与えるゲ
ート電圧Ｖ では、最早コレクタ電流Ｉ。を制御できな
くＧＥ
なるため、素子破壊につながる。In this way, the IGBT enters a latch-up state. one time,
When the parasitic silicon risk is turned on, the gate voltage V applied to the gate electrode 8 no longer causes the collector current I. GE becomes uncontrollable, leading to element destruction.
第４図に種々のゲート電圧Ｖ６Ｅ（矢印に示すように上
方ほど大）の印加状態下におけるＩＧＢＴの出力特性を
示す。同図に示すように、一定のゲート電圧Ｖ。，のち
とでは、チャネル領域６を流れる電流量に制限があるた
め、ＭＯＳＦＥＴと同｛７ｌに自己電流制限がかかり、
コレクタ電流■。は所定値で飽和してしまい、それ以上
は上昇しない。FIG. 4 shows the output characteristics of the IGBT under application of various gate voltages V6E (larger as shown by the arrow). As shown in the figure, a constant gate voltage V. , later, since there is a limit to the amount of current flowing through the channel region 6, a self-current limit is applied to the same as the MOSFET,
Collector current■. is saturated at a predetermined value and does not rise any further.
したがって、Ｎ＋バッファ層２を厚くする、Ｎ＋エミッ
タ領域５を減らす等の方法を用いて［ＧＢＴを設＝１す
ることにより、通常用いるゲート電圧ＶＧＥではコレク
タ電流ＩＣの飽和電流Ｉ ｃ （ｓａｔ）が、ラッチア
ンプ電流ＩＬを越えないようにして、寄生サイリスタが
オンしないようにしていた。Therefore, by thickening the N+ buffer layer 2, reducing the N+ emitter region 5, etc., by setting GBT to 1, the saturation current I c (sat) of the collector current IC can be reduced at the normally used gate voltage VGE. , the latch amplifier current IL was not exceeded to prevent the parasitic thyristor from turning on.
このように、従来のＩＧＢＴは、寄生サイリス夕かオン
することによるラッチアップ現象を回避するために、そ
の通電能力か制限されてしまうという問題点があった。As described above, the conventional IGBT has a problem in that its current carrying capacity is limited in order to avoid the latch-up phenomenon caused by the parasitic thyristor turning on.
また、ＮチャネルバワーＭＯＳＦＥＴにおいても、Ｎ１
エミッタ領域５，Ｐベース領域４， Ｎボディ層３に
相当する領域より形成されるＮＰＮ寄生トランジスタが
存在し、オン／オフ切換時に逆方向電流がＮ＋エミッタ
領域５に相当する領域直下のＰベース領域４に相当する
領域に流れ寄生トランジスタがオンすることによる素子
破壊等の弊害を回避するため、通電能力か制限されてし
まうという問題点かあった。Also, in N-channel power MOSFET, N1
There is an NPN parasitic transistor formed from a region corresponding to the emitter region 5, P base region 4, and N body layer 3, and when switching on/off, a reverse current flows to the P base region immediately below the region corresponding to the N+ emitter region 5. In order to avoid problems such as element destruction due to the parasitic transistor turning on in the region corresponding to No. 4, there was a problem in that the current carrying capacity was limited.
この発明は上記のような問題点を解決するためになされ
たもので、通電能力を向上させた絶縁ゲー１・型トラン
ジスタを得ることを目的とする。The present invention was made to solve the above-mentioned problems, and an object of the present invention is to obtain an insulated gate type 1 type transistor with improved current carrying capacity.
この発明にかかる絶縁ゲート型トランジスタは、第１お
よび第２の主面を有する第１あるいは第２の導電型の第
１の半導体層と、前記第１の半導体層の前記第１の主面
上に形成された第２の導電型の第２の半導体層と、前記
第２の半導体層の表面に選択的に形成された第１の導電
型の第１の半導体領域と、前記第１の半導体領域の表面
に還択的に形成された第２の導電型の第２の半導体領域
と、前記第２の半導体層と前記第２の半導体領域とて挾
まれた前記第１の半導体領域の表面上に形成された絶縁
膜と、前記絶縁膜上に形成された制御電極と、前記第１
および第２の半導体領域上にまたがって形成された第１
の主電極と、前記第１の半導体層の前記第２の主面上に
形戊された第２の主電極とを備え、前記第１の主電極は
、前記第１の半導体領域の表面から前記第２の半導体領
域の底面の少なくとも一部に延びて形成されている。The insulated gate transistor according to the present invention includes a first semiconductor layer of a first or second conductivity type having a first and a second main surface, and a first semiconductor layer on the first main surface of the first semiconductor layer. a second semiconductor layer of a second conductivity type formed on a surface of the second semiconductor layer; a first semiconductor region of a first conductivity type selectively formed on a surface of the second semiconductor layer; a second semiconductor region of a second conductivity type selectively formed on a surface of the region; and a surface of the first semiconductor region sandwiched between the second semiconductor layer and the second semiconductor region; an insulating film formed thereon, a control electrode formed on the insulating film, and the first
and a first semiconductor region formed over the second semiconductor region.
and a second main electrode formed on the second main surface of the first semiconductor layer, the first main electrode extending from the surface of the first semiconductor region. The second semiconductor region is formed so as to extend over at least a portion of the bottom surface of the second semiconductor region.
この発明における第１の主電極は、第１の半導体領域の
表面から第゛２の半導体領域の底面の少なくとも一部に
延びて形成されているため、第１の半導体領域中を流れ
るキャリアの少なくとも一部は、第２の半導体領域直下
の第１の半導体厨域を流れることなく直接に第１の主電
極に達する。The first main electrode in this invention is formed to extend from the surface of the first semiconductor region to at least a part of the bottom surface of the second semiconductor region, so that at least one of the carriers flowing in the first semiconductor region is A portion directly reaches the first main electrode without flowing through the first semiconductor region directly under the second semiconductor region.
第１図はこの発明の一実施例であるＮチャネル型ｒ Ｇ
ＢＴを示す断面図である。同図に示すように、エミッタ
電極９′が第３図で示した従来の形成領域に加え、さら
に、Ｐベース領域４の上層部にも埋めれ込まれて形戊さ
れている。すなわち、Ｎ＋エミッタ領域５間のＰベース
領域４から、Ｎ１エミッタ領域５の底面全面にかけて形
成されている。なお、他のｔＭ １５．ＳＥは従来と同
様であるため説明は省略する。FIG. 1 shows an N-channel type r G which is an embodiment of the present invention.
It is a sectional view showing BT. As shown in the figure, an emitter electrode 9' is formed not only in the conventional formation region shown in FIG. 3 but also embedded in the upper layer of the P base region 4. That is, it is formed from the P base region 4 between the N+ emitter regions 5 to the entire bottom surface of the N1 emitter region 5. In addition, other tM 15. Since the SE is the same as the conventional one, the explanation will be omitted.
このようなｔＭ ｂ５．において、コレクタ電極１１と
エミッタ電極９′ との間に所定のコレクタ電圧ＶＣＵ
Ｅを、ゲート電極８とエミッタ電極９′ との間に、所
定のゲートｙｉ圧Ｖ。，を従来同様に印加すると、ＩＧ
ＢＴかオンし伝導度変調効果により、Ｎ ボディ層３の
抵抗値か低下する。エミッタ電極９′はＮ＋エミッタ領
域５〜チャネル領域６〜Ｎ ボディ層３間の電子電流■
が流れる経路中ｅ
には形戊されていないため、Ｉ ＧＢＴの動作に何ら悪
影響を与えない。Such tM b5. , a predetermined collector voltage VCU is applied between the collector electrode 11 and the emitter electrode 9'.
E and a predetermined gate yi pressure V between the gate electrode 8 and the emitter electrode 9'. , is applied in the same way as before, IG
BT is turned on and the resistance value of the N body layer 3 decreases due to the conductivity modulation effect. The emitter electrode 9' is an electron current between the N+ emitter region 5, the channel region 6, and the N body layer 3.
Since it is not shaped in the path through which the IGBT flows, it does not have any adverse effect on the operation of the IGBT.
ここで、コレクタ電流ＩＣが第４図で示したラッチアッ
プ電流Ｉｔ，より大きく流れ、Ｎ ボディ層３からＰベ
ース領域４へ流れるホール電流が臨界値を越えて増大し
た場合を考える。この場合、エミッタ電極９′がＮ＋エ
ミッタ領域５の底部にも形成されているため、Ｐベース
領域４に流れ込んだホール電流は従来のようにＮ＋エミ
ッタ領域５直下のＰベース領域４を流れることなく直接
にエミッタ電極９′に到達してしまい、このエミッタ電
極９′から外部に流れる。Here, consider a case where the collector current IC flows larger than the latch-up current It shown in FIG. 4, and the hole current flowing from the N body layer 3 to the P base region 4 increases beyond a critical value. In this case, since the emitter electrode 9' is also formed at the bottom of the N+ emitter region 5, the hole current flowing into the P base region 4 does not flow through the P base region 4 directly under the N+ emitter region 5 as in the conventional case. It directly reaches the emitter electrode 9' and flows to the outside from this emitter electrode 9'.
その結果、Ｐベース領域４に流れるホール電流は、Ｎ＋
エミッタ領域５，Ｐベース領域４， Ｎボディ層３か
ら戒るＮＰＮ寄生トランジスタのへ一ス電流とはなりえ
ないため、大量のホール電流がＰベース領域４に流れ込
んでも、前述したＮＰＮ寄生トランジスタがオンするこ
とはなくなり、寄生サイリスクによるラッチアップ現象
は極めて起こりにくくなる。As a result, the hole current flowing through the P base region 4 is N+
Since the emitter region 5, P base region 4, and N body layer 3 cannot serve as a path current for the NPN parasitic transistor, even if a large amount of hole current flows into the P base region 4, the aforementioned NPN parasitic transistor It will no longer turn on, and the latch-up phenomenon due to parasitic silicon risk will be extremely unlikely to occur.
したがって、この実施例によるＩＧＢＴではラッチアッ
プ電流ＩＬが従来と比べて格段に高くなり、従来のよう
に、通常のゲート電圧Ｖ。０を印加した時にＩＧＢＴを
流れるコレクタ電流■。の飽和値を、従来の比較的低い
ラッチアップ電流！ ＋，以下にするようにＩＧＢＴを
設計しなければならないという制限がなくなるため、従
来に比べ通電できるコレクタ電流ｆｆｉｌ。を大幅に増
大することができる。さらに、従来から行われていた種
々のラッチアップ防止対策を行う必要もなくなる。Therefore, in the IGBT according to this embodiment, the latch-up current IL is much higher than that of the conventional one, and the normal gate voltage V is lower than that of the conventional one. Collector current ■ that flows through the IGBT when 0 is applied. Saturation value of conventional relatively low latch-up current! Since there is no longer a restriction that the IGBT must be designed to have a value of +, or less, the collector current ffil that can be passed is lower than that of the conventional method. can be significantly increased. Furthermore, there is no need to take various latch-up prevention measures that have been conventionally taken.
また、エミッタ電極９′がＮ＋エミッタ領域５の底部全
面に形成されているため、エミッタ電極９′とＮ＋エミ
ッタ領域５との電気的接触而積効率が向上する。したが
って、Ｎ＋エミッタ領域５の水平方向の形成幅を、多少
短くしても、従来と同レベルのエミッタ電極９′とＮ＋
エミッタ領域５との電気的接触面積を保つことができる
。Furthermore, since the emitter electrode 9' is formed on the entire bottom of the N+ emitter region 5, the electrical contact volume efficiency between the emitter electrode 9' and the N+ emitter region 5 is improved. Therefore, even if the width of the N+ emitter region 5 in the horizontal direction is somewhat reduced, the emitter electrode 9' and the N+
The electrical contact area with the emitter region 5 can be maintained.
第２図は、この発明の他の実施例であるＮチャネルバワ
ーＭＯＳＦＥＴを示す断面図である。同図に示すように
、第１図で示したＩ ＧＢＴのＮ＋バッファ層２及びＰ
＋コレクタ層１が、Ｎ＋ドレイン層１２に置き代った構
造となっており、他の構造は第１図のＩＧＢＴと全く同
一である。ただし、ＩＧＢＴとＭＯＳＦＥＴの性質の違
いにより、Ｎ＋エミソタ領域５はＮ＋ソース領域１５と
してエミッタ電極９′はソース電極１９′ として、コ
レクタ電極１１はドレイン電極２１として説明する。FIG. 2 is a sectional view showing an N-channel power MOSFET according to another embodiment of the invention. As shown in the figure, the N+ buffer layer 2 and P of the IGBT shown in FIG.
The structure is such that the + collector layer 1 replaces the N+ drain layer 12, and the other structures are exactly the same as the IGBT shown in FIG. However, due to the difference in properties between an IGBT and a MOSFET, the N+ emitter region 5 will be explained as an N+ source region 15, the emitter electrode 9' will be explained as a source electrode 19', and the collector electrode 11 will be explained as a drain electrode 21.
第２図に示すように構成すると、オン／オフ切換時に逆
方向電流がＮ＋ソース領域１５直下のＰベース領域４を
流れることなく直接にソース電極１９′に流れ込んでし
まうため、Ｎ＋ソース項域１５，Ｐベース領域４，Ｎ−
ボディ層３から成るＮＰＮ寄生トランジスタがオンする
可能性はなくなり、従来のように、寄生トランジスタが
オンすることを抑制するための設計上の制限がなくなる
ため、第１図のｒＧＢＴ同様、パワーＭＯＳＦＥＴの通
電できるソース電流量を大幅に１曽加することができる
。With the configuration shown in FIG. 2, during on/off switching, the reverse current flows directly into the source electrode 19' without flowing through the P base region 4 directly below the N+ source region 15. , P base region 4, N-
There is no longer a possibility that the NPN parasitic transistor consisting of the body layer 3 will turn on, and there is no longer a design restriction to suppress the parasitic transistor from turning on, as in the past. The amount of source current that can be supplied can be significantly increased by 1.
なお、第１図，第２図で示した実施例では、Ｎ エミッ
タ領域５ （Ｎ＋ソース領域１５）の底面全面に、エミ
ッタ電極９′ （ソース電極１９′）を形成した例を示
したが、少なくともＮ＋エミツタ領域５ （Ｎ＋ソース
領域１５）の底面の一部に、エミッタ電極９′ （ソー
ス電極１９′）を形戊すれば、寄生トランジスタの活性
化を抑制する機能を果たす効果がある。In the embodiment shown in FIGS. 1 and 2, an example was shown in which the emitter electrode 9' (source electrode 19') was formed on the entire bottom surface of the N emitter region 5 (N+ source region 15). Forming an emitter electrode 9' (source electrode 19') on at least a part of the bottom surface of the N+ emitter region 5 (N+ source region 15) has the effect of suppressing activation of the parasitic transistor.
しかしながら、より完全な寄生トランジスタの活性化の
抑制を果たし、通電能力を大幅に向上させるためには、
第１図（第２図）で示したように、Ｎ＋エミッタ領域５
（Ｎ＋ソース領域１５）の底面全面にエミッタ電極９
′ （ソース電極１９′）を形１戊する方が望ましい。However, in order to more completely suppress the activation of parasitic transistors and significantly improve the current carrying capacity,
As shown in FIG. 1 (FIG. 2), the N+ emitter region 5
The emitter electrode 9 is located on the entire bottom surface of the (N+ source region 15).
It is preferable to form the source electrode 19' (source electrode 19') into a single shape.
また、上記実施例では、ＮチャネルのＩＧＢＴ及びパワ
ーＭＯＳＦＥＴについて説明したが、ＰチャネルのＩ
ＧＢＴ及びパワーＭＯＳＦＥＴについてもこの発明を適
用できることは勿論である。Furthermore, in the above embodiment, an N-channel IGBT and a power MOSFET have been described, but a P-channel IGBT and a power MOSFET have been described.
Of course, the present invention can also be applied to GBTs and power MOSFETs.
以上説明したように、この発明によれば、第１の主電極
は、第１の半導体領域の表面から第２の１ｉ導体領域の
底面の少なくとも一部に延びて形成されているため、第
１の半導体領域中を流れるキャリアの少なくとも一部は
、第２の半導体領域に達することなく第１の主電極に流
れる。As explained above, according to the present invention, the first main electrode is formed extending from the surface of the first semiconductor region to at least a part of the bottom surface of the second 1i conductor region. At least a portion of the carriers flowing through the semiconductor region flow to the first main electrode without reaching the second semiconductor region.
したがって、第２の半導体領域に大量のキャリアが流れ
る場合においても、第２の半導体領域をベース領域とし
、第１の半導体領域をエミッタ領域とし、第２の半導体
層をコレクタ領域とした寄坐トランジスタのベース電流
を大幅に削減できるため、寄生トランジスタの活性化の
抑制効果が向上する。Therefore, even when a large amount of carriers flow into the second semiconductor region, the parasitic transistor with the second semiconductor region as the base region, the first semiconductor region as the emitter region, and the second semiconductor layer as the collector region Since the base current of the transistor can be significantly reduced, the effect of suppressing the activation of parasitic transistors is improved.
その桔果、寄生トランジスタの活性化を回避するための
主電流の制限が大幅に緩和されるため、通電能力が向上
した絶縁ゲート型トランジスタを得ることができる効果
がある。As a result, the restriction on the main current for avoiding activation of parasitic transistors is significantly relaxed, so that it is possible to obtain an insulated gate transistor with improved current carrying capacity.
第１図はこの発明の一実施例であるＩ ＧＢＴを示す断
而図、第２図はこの発明の他の実施例であるパワーＭＯ
ＳＦＥＴを示す断面図、第３図は従来のＩＧＢＴを示す
断面図、第４図はＩ ＧＢＴの出力特性図である。
図において、１はＰ＋コレクタ層、３はＮ ボディ層、
４はＰヘース領域、５はＮ＋エミ・ソタ領域、６はチャ
ネル領域、７はゲート絶縁膜、８はゲート電極、９′は
エミツタ電極、１１はコレクタ電極、１２はＮ＋ドレイ
ン領域、１５はＮ＋ソース領域、１９′ はソース電極
、２ｌはドレイン電極である。
なお、各図中同一符号は同一または相当部分を示す。Fig. 1 is a diagram showing an IGBT which is an embodiment of the present invention, and Fig. 2 is a diagram showing a power MO which is another embodiment of the invention.
FIG. 3 is a cross-sectional view of the SFET, FIG. 3 is a cross-sectional view of a conventional IGBT, and FIG. 4 is an output characteristic diagram of the IGBT. In the figure, 1 is a P+ collector layer, 3 is an N body layer,
4 is a P heath region, 5 is an N+ emitter/soter region, 6 is a channel region, 7 is a gate insulating film, 8 is a gate electrode, 9' is an emitter electrode, 11 is a collector electrode, 12 is an N+ drain region, 15 is an N+ In the source region, 19' is a source electrode, and 2l is a drain electrode. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
の導電型の第１の半導体層と、 前記第１の半導体層の前記第１の主面上に形成された第
２の導電型の第２の半導体層と、 前記第２の半導体層の表面に選択的に形成された第１の
導電型の第１の半導体領域と、 前記第１の半導体領域の表面に選択的に形成された第２
の導電型の第２の半導体領域と、 前記第２の半導体層と前記第２の半導体領域とで挟まれ
た前記第１の半導体領域の表面上に形成された絶縁膜と
、 前記絶縁膜上に形成された制御電極と、 前記第１および第２の半導体領域上にまたがって形成さ
れた第１の主電極と、 前記第１の半導体層の前記第２の主面上に形成された第
２の主電極とを備え、 前記第１の主電極は、前記第１の半導体領域の表面から
前記第２の半導体領域の底面の少なくとも一部に延びて
形成されていることを特徴とする絶縁ゲート型トランジ
スタ。(1) A first or second surface having a first and second main surface.
a first semiconductor layer of a conductivity type; a second semiconductor layer of a second conductivity type formed on the first main surface of the first semiconductor layer; and a surface of the second semiconductor layer. a first semiconductor region of a first conductivity type selectively formed on a surface of the first semiconductor region; and a second semiconductor region selectively formed on a surface of the first semiconductor region.
a second semiconductor region of a conductivity type; an insulating film formed on the surface of the first semiconductor region sandwiched between the second semiconductor layer and the second semiconductor region; and on the insulating film. a control electrode formed on the second main surface of the first semiconductor layer; a first main electrode formed on the first and second semiconductor regions; and a first main electrode formed on the second main surface of the first semiconductor layer. 2 main electrodes, wherein the first main electrode is formed to extend from the surface of the first semiconductor region to at least a part of the bottom surface of the second semiconductor region. Gate type transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1193534A JPH0357226A (en) | 1989-07-25 | 1989-07-25 | Insulated-gate transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1193534A JPH0357226A (en) | 1989-07-25 | 1989-07-25 | Insulated-gate transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0357226A true JPH0357226A (en) | 1991-03-12 |
Family
ID=16309678
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1193534A Pending JPH0357226A (en) | 1989-07-25 | 1989-07-25 | Insulated-gate transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0357226A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101834202A (en) * | 2010-04-13 | 2010-09-15 | 东南大学 | N-type lateral insulated gate bipolar device capable of reducing hot carrier effect |
-
1989
- 1989-07-25 JP JP1193534A patent/JPH0357226A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101834202A (en) * | 2010-04-13 | 2010-09-15 | 东南大学 | N-type lateral insulated gate bipolar device capable of reducing hot carrier effect |
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