JPH035677B2 - - Google Patents
Info
- Publication number
- JPH035677B2 JPH035677B2 JP10420682A JP10420682A JPH035677B2 JP H035677 B2 JPH035677 B2 JP H035677B2 JP 10420682 A JP10420682 A JP 10420682A JP 10420682 A JP10420682 A JP 10420682A JP H035677 B2 JPH035677 B2 JP H035677B2
- Authority
- JP
- Japan
- Prior art keywords
- composite
- board
- substrate
- capacitor
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003990 capacitor Substances 0.000 claims description 35
- 239000002131 composite material Substances 0.000 claims description 35
- 239000000758 substrate Substances 0.000 claims description 35
- 229910000679 solder Inorganic materials 0.000 claims description 11
- 239000004020 conductor Substances 0.000 claims description 8
- 238000005245 sintering Methods 0.000 claims description 2
- 238000010030 laminating Methods 0.000 claims 1
- 238000000034 method Methods 0.000 description 17
- 239000000463 material Substances 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 5
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 239000000919 ceramic Substances 0.000 description 4
- 238000004382 potting Methods 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 238000007598 dipping method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 239000011165 3D composite Substances 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910010413 TiO 2 Inorganic materials 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000001186 cumulative effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910000510 noble metal Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- -1 resistors Substances 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
- Combinations Of Printed Boards (AREA)
Description
【発明の詳細な説明】
本発明は高密度の複合回路装置に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to high density composite circuit devices.
近年、半導体集積回路（IC）化率の大幅向上
によつて電子回路の小形高密度化が著しく促進さ
れたが、線形回路においては高精度の抵抗や、大
容量コンデンサなどの周辺回路は依然として個別
回路部品が利用されるケースが多い。即ち、半導
体IC化困難な抵抗、コンデンサなどの回路部品
をも効率良く複合化した低コストで小形高密度、
かつ標準ブロツク化可能な複合回路装置の出現が
強く望まれている。 In recent years, the large increase in the rate of semiconductor integrated circuits (ICs) has significantly promoted the miniaturization and high density of electronic circuits, but in linear circuits, peripheral circuits such as high-precision resistors and large-capacity capacitors are still required to be individually packaged. In many cases, circuit components are used. In other words, it is a low-cost, compact, high-density product that efficiently combines circuit components such as resistors and capacitors that are difficult to convert into semiconductor ICs.
There is also a strong desire for the emergence of a composite circuit device that can be made into a standard block.
従来、小形高密度化を要求される電子回路にお
いては、チツプ抵抗、チツプコンデンサといつた
小形化回路部品を用いて、同じく小形化パツケー
ジされた能動素子とともにプリント基板に実装す
るチツプマウント法が一般化している。しかし、
これらチツプ部品の小形化にも限度があり、シス
テム全体の小形化のネツクとなつてるし、又部品
点数が多く管理面でも組立作業性でも難がある
し、接続箇所が多くて信頼性に乏しい欠点もあ
る。 Conventionally, in electronic circuits that require compactness and high density, the chip mounting method is commonly used, in which miniaturized circuit components such as chip resistors and chip capacitors are mounted on a printed circuit board along with active elements packaged in the same miniaturized package. It has become but,
There is a limit to the miniaturization of these chip parts, and this becomes the bottleneck for miniaturizing the entire system.Also, the large number of parts makes it difficult to manage and assemble, and there are many connections, making it unreliable. There are also drawbacks.
さらにいわゆる厚膜集積回路の様に、アルミナ
基板上に導体、抵抗体、半導体チツプ、コンデン
サチツプ、外部リードなどを連続的に付加してい
き最後に外装を施すような複合回路装置もある。
半導体チツプの直付け法を採用すればかなりの高
集積度は期待できるが、各構成要素を連続的に付
加していくプロセスであるために累積歩留が悪く
なるし、量産性の面でも難があり、民生用電子機
器に使用するには高価すぎる欠点があつた。さら
にマイクロモジユール方式の様に標準化されたウ
エハを構成要素部品として複数枚を積層し各端子
電極間を複数本のワイヤを用いて相互配線した
後、外装を施した三次元構成の複合回路装置も提
案されたが、複雑な組立工程を必要とするし、接
続箇所も多いなどコストメリツトが生じないこと
から現在では全く使用例は見られない。 Furthermore, there are also composite circuit devices, such as so-called thick film integrated circuits, in which conductors, resistors, semiconductor chips, capacitor chips, external leads, etc. are successively added to an alumina substrate, and an exterior is applied at the end.
If the direct attachment method of semiconductor chips is adopted, a considerably high degree of integration can be expected, but since it is a process in which each component is added successively, the cumulative yield will be poor, and it will also be difficult in terms of mass production. However, it had the disadvantage that it was too expensive to be used in consumer electronic equipment. Furthermore, as in the case of the micromodule method, a three-dimensional composite circuit device is created in which multiple standardized wafers are stacked together as component parts, each terminal electrode is interconnected using multiple wires, and then an exterior is applied. was also proposed, but it requires a complicated assembly process and has many connection points, so there is no cost advantage, so it is currently not used at all.
本発明はかかる状況に鑑みてなされたもので、
IC化困難な抵抗やコンデンサをもICなどととも
に巧みに一体化した複合回路装置を提供すること
を目的としている。 The present invention was made in view of this situation,
The aim is to provide a composite circuit device that skillfully integrates resistors and capacitors that are difficult to integrate with ICs.
以下、本発明の一実施例を図面を用いて説明す
る。第１図は本発明の構造を示す図で第１図Ａ、
第１図Ｂはそれぞれ本発明に用いるキヤリア基板
及び複合コンデンサ基板の平面図、第１図Ｃは両
基板が合体した複合回路装置の断面図を表わして
いる。本発明の複合回路装置は、基本的には半導
体チツプを主要素子として構成したキヤリア基板
と、複数個のコンデンサを主要素子として構成し
た複合コンデンサ基板とを独立した要素基板とし
て製作し、最後にこれらを一体化して標準化され
たブロツク構造とすることを特徴としている。 An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing the structure of the present invention.
FIG. 1B is a plan view of a carrier substrate and a composite capacitor substrate used in the present invention, and FIG. 1C is a sectional view of a composite circuit device in which both substrates are combined. The composite circuit device of the present invention basically consists of a carrier board configured with a semiconductor chip as the main element, and a composite capacitor board configured with a plurality of capacitors as the main elements, as independent element boards, and finally these It is characterized by integrating the blocks into a standardized block structure.
キヤリア基板１には、標準的な厚膜プロセスが
適用できるアルミナなどのセラミツク基板を用い
た。形状は多数個同時処理や収容効率を配慮して
正方形としたが矩形状でも構わない。キヤリア基
板１の両面及び縁端面には、まず導体層２がスク
リーン印刷と焼成によつて付加される。この導体
には、目的に応じてガラスフリツトを含んだAu
やAgPdなどの貴金属系の材料が素材として用い
られる。キヤリア基板１の四縁端面にも両面導体
間の電気的接続のため、及びプリント基板への実
装上の引出端子電極として端面電極層２′が設け
られている。端子電極数は本実施例では各辺に５
端子ずつ設け、合計20端子としている。キヤリア
基板１の片面には、抵抗体層３が同じくスクリー
ン印刷および焼成されて構成される。この抵抗体
にはRuO2などの素材が用いられる。必要に応じ
て抵抗体層３及び導体層２の上には保護ガラス層
が被覆されることもあるし、又抵抗体層３はレー
ザなどによつて所定の値にトリミングされる場合
もある。キヤリア基板の他の片面にはICチツプ
４が、ダイボンデイングやワイヤボンデイング技
術によつて付加される。さらにICチツプを機械
的、環境的に保護する目的でポツテイング樹脂５
を被覆すれば、キヤリア基板１はIC及びトリミ
ングを要する高精度の抵抗を高密度に一体化した
モジユールとして完成する。外観はICの標準化
パツケージの一方式として提案されているリード
レスのチツプキヤリと呼ばれるものと類似してい
るが、高精度の印刷抵抗を内蔵してる点に特徴が
ある。キヤリア基板１は外形寸法や引出端子電極
数、電極ピツチなどを標準化していけば、異なつ
た回路モジユールが共通の自動化設備によつて大
量生産しうるようになる。単独のモジユールとし
ても、リードレスでプリント基板への直付け実装
も可能である。 As the carrier substrate 1, a ceramic substrate made of alumina or the like to which a standard thick film process can be applied was used. The shape is square in consideration of simultaneous processing of multiple pieces and storage efficiency, but it may also be rectangular. A conductor layer 2 is first applied to both sides and edge surfaces of the carrier substrate 1 by screen printing and baking. This conductor can be made of Au containing glass frit depending on the purpose.
Noble metal materials such as and AgPd are used as materials. End surface electrode layers 2' are also provided on the four edge surfaces of the carrier board 1 for electrical connection between the double-sided conductors and as lead terminal electrodes for mounting on a printed circuit board. In this example, the number of terminal electrodes is 5 on each side.
One terminal is provided for each terminal, making a total of 20 terminals. On one side of the carrier substrate 1, a resistor layer 3 is similarly screen printed and fired. This resistor is made of a material such as RuO 2 . If necessary, the resistor layer 3 and the conductor layer 2 may be covered with a protective glass layer, and the resistor layer 3 may be trimmed to a predetermined value using a laser or the like. An IC chip 4 is added to the other side of the carrier board by die bonding or wire bonding technology. In addition, potting resin 5 is used to mechanically and environmentally protect the IC chip.
Once coated, the carrier substrate 1 is completed as a module in which an IC and a high-precision resistor that requires trimming are integrated in a high density. The external appearance is similar to a leadless chip carrier that has been proposed as a standardized package method for ICs, but it is unique in that it has a built-in high-precision printed resistor. If the carrier board 1 is standardized in terms of external dimensions, number of lead-out terminal electrodes, electrode pitch, etc., different circuit modules can be mass-produced using common automated equipment. It can be used as a stand-alone module or can be mounted directly onto a printed circuit board without leads.
一方、複合コンデンサ基板６は、いわゆる積層
セラミツク技術を用いて製作される。材料として
は、要求されるコンデンサ特性に応じてTiO2、
BaTiO3系の高誘電率材料が用いられる。積層セ
ラミツク技術には印刷法、シート工法と呼ばれる
公知の技術が一般化しているが、いずれも誘電体
層７、内部電極層８が交互に積層され1300℃〜
1400℃程度で一体化焼結することによつて製作さ
れる。内部電極層８は複数個のコンデンサを構成
する目的で、パターンニングされた版を用いて印
刷法で交互に対向電極を形成する必要がある。内
部電極層８からの引出端子電極９は複合コンデン
サ基板６の縁端面に構成される。端子電極数は内
蔵されるコンデンサ数によつて変化するが、本実
施例では６個のコンデンサ内蔵のもので９端子の
ものを示している。バイパスコンデンサの様に、
接地端子が内部電極層によつて共通的に接続出き
るものが多い為、一般に端子電極数はコンデンサ
数の２倍よりも少なくしうる。これは、個別のチ
ツプコンデンサを使用するのに比し、必要端子数
が減少し接続部の信頼性が増す効果を発揮すると
ともに、複数個のコンデンサが複合一体化され一
ブロツク化されるので管理面でも有利となる。引
出端子電極９の材料としては、半田付け実装を可
能ならしめるためAgPd系が一般に好適である。
複合コンデンサ基板６も標準化された外形寸法と
端子配列にすることにより、自動化設備の共通化
が図られ大量生産が可能となる。 On the other hand, the composite capacitor substrate 6 is manufactured using so-called laminated ceramic technology. Depending on the required capacitor characteristics, materials include TiO 2 ,
A high dielectric constant material based on BaTiO 3 is used. Well-known technologies called printing method and sheet method have become common in laminated ceramic technology, but in both of them, dielectric layers 7 and internal electrode layers 8 are alternately laminated at temperatures of 1300℃~
Manufactured by integral sintering at approximately 1400℃. In order to form a plurality of capacitors in the internal electrode layer 8, it is necessary to form opposing electrodes alternately by a printing method using a patterned plate. A lead terminal electrode 9 from the internal electrode layer 8 is formed on the edge surface of the composite capacitor substrate 6. The number of terminal electrodes varies depending on the number of built-in capacitors, but in this embodiment, a device with six capacitors and nine terminals is shown. Like a bypass capacitor,
Generally, the number of terminal electrodes can be less than twice the number of capacitors because the ground terminals can often be connected in common by internal electrode layers. Compared to using individual chip capacitors, this has the effect of reducing the number of required terminals and increasing the reliability of the connection, and can also be managed because multiple capacitors are integrated into one block. It is also advantageous in terms of As the material for the lead terminal electrode 9, AgPd-based material is generally suitable because it enables soldering mounting.
By making the composite capacitor board 6 also have standardized external dimensions and terminal arrangement, automation equipment can be standardized and mass production becomes possible.
以上の様に、キヤリア基板１と複合コンデンサ
基板６はそれぞれ独立して製作され、かつ特性チ
エツクされた高密度のリードレスの標準化モジユ
ールであることが分る。次に、両基板を一体化し
た本発明の複合回路装置について第１図Ｃを基に
説明する。キヤリア基板１の端面電極層２′と複
合コンデンサ基板６の引出端子電極９とは同一ピ
ツチ配列上に設けた方が標準化には好都合である
ことから、両基板の外形寸法は全く同一か、又は
若干複合コンデンサ基板を小さめにする程度が好
ましい。両基板の端子電極を対向配置させつつ半
田槽で一括浸漬すれば、端子電極相互間が半田層
１０によつて電気的機械的に接続される。予め両
基板間を接着剤で貼り合せた後、半田浸漬する方
がより接続の確実性を増すことが出来る。両基板
寸法に若干の差がある方が半田層１０の半田量が
多くなり、一端子当りの接続強度が強くなる効果
があるため、特に複合コンデンサ基板６の端子数
が少ない場合には好都合である。全く同一寸法の
場合は標準化面では有利となり、端子数が比較的
多い場合には適用しうる。 As described above, it can be seen that the carrier substrate 1 and the composite capacitor substrate 6 are high-density leadless standardized modules that are manufactured independently and whose characteristics have been checked. Next, a composite circuit device of the present invention in which both boards are integrated will be explained based on FIG. 1C. Since it is convenient for standardization to provide the end electrode layer 2' of the carrier substrate 1 and the lead-out terminal electrode 9 of the composite capacitor substrate 6 on the same pitch arrangement, the external dimensions of both substrates should be exactly the same or It is preferable to make the composite capacitor board slightly smaller. By immersing the terminal electrodes of both substrates in a solder bath while facing each other, the terminal electrodes are electrically and mechanically connected to each other by the solder layer 10. The reliability of the connection can be further increased by bonding the two substrates together with an adhesive in advance and then dipping them in solder. If there is a slight difference in the dimensions of both boards, the amount of solder in the solder layer 10 will be larger, and the connection strength per terminal will be stronger. This is particularly advantageous when the number of terminals on the composite capacitor board 6 is small. be. Having exactly the same dimensions is advantageous in terms of standardization, and can be applied when the number of terminals is relatively large.
以上の様に極めて簡単な組立工程によつて両基
板が一体化され、IC、抵抗、コンデンサなどの
構成要素が三次元的に高密度に集積化された複合
回路装置が実現しうる。両基板はそれぞれ特性チ
エツクされており、組立後の特性歩留も非常に良
い。外部リードの必要性も全く無く、又ICチツ
プはポツテイング樹脂５で個別に保護されてお
り、特別の外装を施す必要もない。 As described above, the two substrates are integrated through an extremely simple assembly process, and a composite circuit device in which components such as ICs, resistors, and capacitors are three-dimensionally integrated with high density can be realized. Both substrates have been checked for their respective characteristics, and the characteristic yield after assembly is also very good. There is no need for any external leads, and the IC chips are individually protected by the potting resin 5, so there is no need for special packaging.
引続き、第２図に基づきプリント基板などへの
実装方法について述べる。キヤリア基板１及び複
合コンデンサ基板６は第１図と等価であるが本実
施例では同一外形寸法のものを用いた。両基板間
は予め接着剤１１によつて機械的に貼り合せてお
く。別途準備さるべきプリント基板１２の表面に
はエツチングされた銅箔層１３が構成される。プ
リント基板１２にはポツテイング樹脂５の逃げ穴
１４を穿孔しておく。機械的に一体化した複合回
路装置をプリント基板１２の上の所定の位置に載
置し、同様に接着剤で機械的に固定する。他の実
装すべき回路部品もすべてプリント基板１２の上
に載置した後、一括して半田浸漬すれば、キヤリ
ア基板１、複合コンデンサ基板６、プリント基板
１２の各々の端子電極相互間が半田層１０によつ
て短絡され電気的に接続される。唯一度の半田浸
漬工程によつてすべての電気的相互接続が完了す
る。各基板は個別に特性チエツクされているので
組立後特性歩留は極めて良い。 Next, the mounting method on a printed circuit board etc. will be described based on FIG. The carrier substrate 1 and the composite capacitor substrate 6 are equivalent to those shown in FIG. 1, but in this embodiment, those having the same external dimensions are used. The two substrates are mechanically bonded together in advance using an adhesive 11. An etched copper foil layer 13 is formed on the surface of a printed circuit board 12 which must be prepared separately. An escape hole 14 for the potting resin 5 is bored in the printed circuit board 12. The mechanically integrated composite circuit device is placed in a predetermined position on the printed circuit board 12 and similarly fixed mechanically with adhesive. If all other circuit components to be mounted are placed on the printed circuit board 12 and then dipped in solder all at once, the terminal electrodes of the carrier board 1, the composite capacitor board 6, and the printed circuit board 12 will have a solder layer between them. 10 and are electrically connected. A single solder dip process completes all electrical interconnections. Since each board is individually checked for characteristics, the characteristic yield after assembly is extremely high.
以上本発明の実施例を図面を用いて説明した
が、関連して実施しうる他の例についても述べ
る。前の実施例ではキヤリア基板１にはIC及び
抵抗を構成したが、ICの中に抵抗がすべて内蔵
される場合には別途抵抗を構成する必要がない。
この場合、キヤリア基板１にはICのみが実装さ
れた状態となり、標準化されたいわゆるICチツ
プキヤリアとして機能する。 Although the embodiments of the present invention have been described above with reference to the drawings, other examples that can be implemented in conjunction will also be described. In the previous embodiment, an IC and a resistor were configured on the carrier board 1, but if all the resistors are built into the IC, there is no need to configure a separate resistor.
In this case, only the IC is mounted on the carrier board 1, and it functions as a standardized so-called IC chip carrier.
さらに又、前述の実施例では複合コンデンサ基
板６の表面上には別の構成素子を一切設けないこ
ととしたが、印刷抵抗を付加構成したRC複合基
板とすることも可能である。高誘電率の積層誘電
体基板上に浮遊容量を軽減する目的で、低誘電率
のガラス層を下塗りした上に印刷抵抗を構成する
技術も進歩しており、RC複合基板を用いても良
い。即ち、抵抗体は必要でない場合もあるし、又
必要な場合はキヤリア基板及び複合コンデンサ基
板のいずれにも構成する事が技術的には可能であ
り、いずれを選択するかは、配置設計、回路性
能、端子電極数の増減、コストダウンなどの観点
から決定すれば良いことになる。さらに最近は、
複合コンデンサ基板にインダクタンスをも一体化
焼結する試みもなされているが、安価に入手しう
る技術開発が実現すればLC複合基板として使用
することが可能になることは容易に類推しうる。 Furthermore, in the above-described embodiment, no other component was provided on the surface of the composite capacitor board 6, but it is also possible to use an RC composite board with additional printed resistors. For the purpose of reducing stray capacitance on a laminated dielectric substrate with a high dielectric constant, the technology of configuring a printed resistor on a low dielectric constant glass layer undercoated has also advanced, and an RC composite substrate may also be used. In other words, the resistor may not be necessary in some cases, and if it is necessary, it is technically possible to configure it on either the carrier board or the composite capacitor board, and which one to choose depends on the layout design and circuit design. The decision can be made from the viewpoints of performance, increase/decrease in the number of terminal electrodes, cost reduction, etc. More recently,
Attempts have also been made to integrate and sinter inductance into a composite capacitor substrate, but it is easy to infer that if a technology that can be obtained at low cost is developed, it will be possible to use it as an LC composite substrate.
以上、いくつかの実施例によつて本発明を説明
してきたが、本発明によつて次の様な効果が得ら
れる。すなわち、構成要素のキヤリア基板と複合
コンデンサ基板が標準化されるので設備の自動化
への対処が容易になる。両基板は高密度に複合化
されたモジユールであり、従来例に比し部品管理
面でも著しく楽になる。両基板は独立して製造さ
れかつ特性チエツクされるので、組立後の特性歩
留は極めて良い。外部リードや外装の必要がな
く、しかも電気的接続が唯一回の半田浸漬工程に
よつて完了しうるなど組立工程が著しく簡素化で
きる。一般に積層誘電体基板は機械的強度が弱
く、大面積になるほどクラツクや割れが発生し易
く、特に信頼性面で問題が生じ易いが、本発明で
はキヤリア基板材がアルミナの様な高強度のセラ
ミツク構造材として機能するのでその心配も消散
する。同様に構成素子を三次元的に集積化する方
式であり、高密度実装法を安価に提供することが
できるとともに、回路ブロツクを標準化していく
のに好適である。 The present invention has been explained above using several examples, and the following effects can be obtained by the present invention. That is, since the component carrier board and composite capacitor board are standardized, it becomes easier to deal with equipment automation. Both boards are high-density composite modules, making parts management significantly easier than in conventional systems. Since both substrates are manufactured and checked independently, the characteristic yield after assembly is extremely good. There is no need for external leads or sheathing, and the electrical connection can be completed with only one solder dipping process, which greatly simplifies the assembly process. In general, laminated dielectric substrates have weak mechanical strength, and the larger the area, the more likely they are to crack and crack, and are particularly prone to problems in terms of reliability. However, in the present invention, the carrier substrate material is made of high-strength ceramic such as alumina. Since it functions as a structural material, that worry will disappear. Similarly, this is a method of three-dimensionally integrating component elements, which can provide a high-density mounting method at low cost, and is suitable for standardizing circuit blocks.
本発明の複合回路装置は上述したように多くの
特長を有しており、ラジオ、テープレコーダ、ポ
ータブルビデオなど超小形化を要求される民生用
電子機器回路の標準ブロツク化において、合理化
を経済的に実現する手段として特に有効である。 The composite circuit device of the present invention has many features as described above, and can be used economically and rationally to standardize circuits of consumer electronic devices such as radios, tape recorders, and portable video devices that require ultra-miniaturization. This is particularly effective as a means of achieving this.
第１図Ａ，Ｂ，Ｃは本発明の一実施例における
キヤリア基板、複合コンデンサ基板の各平面図お
よび両基板を合体した状態を示す断面図、第２図
は本発明の複合回路装置のプリント基板への実装
状態の一例を示す断面図である。
１……キヤリア基板、２，２′……導体層、３
……抵抗体層、４……ICチツプ、５……ポツテ
イング樹脂、６……コンデンサ基板、１……誘電
体層、８……内部電極層、９……引出端子電極、
１０……半田層、１１……接着剤。
FIGS. 1A, B, and C are plan views of a carrier board and a composite capacitor board in one embodiment of the present invention, and a sectional view showing a state in which both boards are combined, and FIG. 2 is a printed circuit board of a composite circuit device of the present invention. FIG. 3 is a cross-sectional view showing an example of a mounting state on a board. 1... Carrier board, 2, 2'... Conductor layer, 3
... Resistor layer, 4 ... IC chip, 5 ... Potting resin, 6 ... Capacitor substrate, 1 ... Dielectric layer, 8 ... Internal electrode layer, 9 ... Output terminal electrode,
10...Solder layer, 11...Adhesive.
Claims (1)
配設し、かつ前記絶縁基板の縁端面部に、前記絶
縁基板上の導体層と電気的に接続された引出端子
電極を設けたキヤリア基板と、内部電極層と誘電
体層とを交互に積層して焼結した複数個のコンデ
ンサ機能を有する積層誘電体基板の縁端面部に引
出端子電極を設けた複合コンデンサ基板とを、相
互間の引出端子電極を対向して配置すると共に、
半田層によつて前記各引出端子電極間を電気的に
相互に接続したことを特徴とする複合回路装置。 ２ 複合コンデンサ基板の主面上に抵抗体を配設
したことを特徴とする特許請求の範囲第１項記載
の複合回路装置。[Scope of Claims] 1. A conductor layer and a circuit component are arranged on both main surfaces of an insulating substrate, and a lead-out terminal is electrically connected to the conductor layer on the insulating substrate at an edge surface of the insulating substrate. A composite capacitor board comprising a carrier board provided with electrodes, a laminated dielectric board having multiple capacitor functions, which is made by laminating and sintering internal electrode layers and dielectric layers alternately, and a lead terminal electrode provided on the edge surface. and by arranging the lead terminal electrodes facing each other, and
A composite circuit device characterized in that the respective lead terminal electrodes are electrically connected to each other by a solder layer. 2. The composite circuit device according to claim 1, characterized in that a resistor is disposed on the main surface of the composite capacitor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10420682A JPS58220492A (en) | 1982-06-16 | 1982-06-16 | Composite circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10420682A JPS58220492A (en) | 1982-06-16 | 1982-06-16 | Composite circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58220492A JPS58220492A (en) | 1983-12-22 |
| JPH035677B2 true JPH035677B2 (en) | 1991-01-28 |
Family
ID=14374494
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10420682A Granted JPS58220492A (en) | 1982-06-16 | 1982-06-16 | Composite circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58220492A (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3613302B2 (en) * | 1995-07-26 | 2005-01-26 | セイコーエプソン株式会社 | Inkjet recording head |
| JP4150552B2 (en) * | 2002-08-28 | 2008-09-17 | 富士通株式会社 | Composite capacitor |
| JP6554833B2 (en) * | 2015-03-12 | 2019-08-07 | 株式会社村田製作所 | Composite electronic components and resistive elements |
| JP6743602B2 (en) * | 2016-09-09 | 2020-08-19 | 株式会社村田製作所 | Composite electronic components and resistance elements |
| JP6747202B2 (en) * | 2016-09-09 | 2020-08-26 | 株式会社村田製作所 | Composite electronic components |
| JP2018041931A (en) * | 2016-09-09 | 2018-03-15 | 株式会社村田製作所 | Composite electronic component |
| US10910163B2 (en) * | 2018-06-29 | 2021-02-02 | Samsung Electro-Mechanics Co., Ltd. | Multilayer electronic component and board having the same mounted thereon |
-
1982
- 1982-06-16 JP JP10420682A patent/JPS58220492A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58220492A (en) | 1983-12-22 |
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