JPH0353651B2 - - Google Patents

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Publication number
JPH0353651B2
JPH0353651B2 JP60066932A JP6693285A JPH0353651B2 JP H0353651 B2 JPH0353651 B2 JP H0353651B2 JP 60066932 A JP60066932 A JP 60066932A JP 6693285 A JP6693285 A JP 6693285A JP H0353651 B2 JPH0353651 B2 JP H0353651B2
Authority
JP
Japan
Prior art keywords
data
bit data
circuit
addition
supplied
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60066932A
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Japanese (ja)
Other versions
JPS61226835A (en
Inventor
Hiroshi Mobara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP60066932A priority Critical patent/JPS61226835A/en
Publication of JPS61226835A publication Critical patent/JPS61226835A/en
Publication of JPH0353651B2 publication Critical patent/JPH0353651B2/ja
Granted legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Electrophonic Musical Instruments (AREA)

Abstract

PURPOSE:To improve error accuracy by supplying the inverting data of the highest order bit data of multiplying result when adding is executed by an adding subtracting circuit and supplying the highest order bit data as the lowest order bit data when subtracting is executed. CONSTITUTION:The first and second binary data are multiplied in which the complement of 2 is expressed by a multiplying circuit 11, and the lower order bit of the number of a constant bit is cut off and the multiplying result is obtained. The multiplying result is made into the higher order bit data, and with the third binary data, in which the inverting data of the highest bit data of the multiplying result are respective data of the lower order bit than it, as one side input data, and with the fourth binary data expressed by the complement of 2 as other input data, they are respectively supplied to an adding subtracting circuit 12, and based upon the control signal, the third and fourth binary data are added and subtracted. When the adding is executed, the inverting data of the highest order bit data are supplied, and when the subtracting is executed, the highest order bit data are supplied as the lowest bit data.

Description

【発明の詳細な説明】[Detailed description of the invention]

〔発明の技術分野〕 この発明は、デイジタルフイルタや音声合成、
メロデイー合成等に代表されるデイジタル信号処
理分野で用いられ、特に乗算結果の誤差を改善す
る乗算丸め機能を有し、同時に乗算結果の増幅機
能を有するデイジタル信号処理回路に関する。 〔発明の技術的背景〕 従来、デイジタル信号処理で利用される乗算結
果の丸め処理としては、下位数ビツトの切捨て処
理や、切捨てる下位数ビツトの四捨五入処理が行
われている。また、切上げ処理は安定性を考慮し
て通常では行われないが、近年の音声合成に用い
る格子型フイルタでのメロデイー合成ではこの切
上げ処理が重要な役割を果たしている。この切上
げ処理を使用した技術としては、例えば、日本音
響学会音声研究会資料S82−04（昭和57年４月26
日発行）の第25頁ないし第32頁に記載されてに
る、日比野他著の「PARCOR音声合成LSIにお
ける楽音発生の検討」が知られている。 切捨て処理、四捨五入処理は本質的に真値を減
衰させる機能を備えているため、例えば格子型フ
イルタのインパルス応答を用いて所望の周波数の
減衰正弦波を生成し、メロデイーの音階信号に利
用する場合、減衰の時定数が大きすぎて音階とし
て実用上使用することができない。そこで、上記
文献に記載されている技術では、乗算結果の切上
げを行ない、一種の増幅を行なうことを提案して
いる。 〔背景技術の問題点〕 しかしながら、上記文献の技術による切上げ方
法では以下のような問題点がある。すなわち、い
ま、Ｍビツトの乗算結果Ｚが得られ、その下位Ｎ
ビツトの切上げ処理が行われた後のＭビツトのデ
ータをZ′とする。ただし、Ｚ，Z′はともに２の補
数で表現されているとする。上記文献の方法によ
れば、Ｚが正または零ならば下位Ｎビツトをすべ
て“１”レベルにし、Ｚが負の場合には下位Ｎビ
ツトをすべて“０”レベルにする。いま｜Ｚ｜≦
１として、ＺとZ′との関係を示したのが第３図で
ある。第３図において、破線は切上げ処理を行な
わないときのＺとZ′との関係を示し、切上げ処理
後のデータZ′は実線で示すように階段状に変化す
る。従つて、ＺとZ′との間の誤差ｅをｅ＝Z′−Ｚ
と定義したときに次の各式が成立する。ただしΔ
は2-(M-N-1)と定義する。 −Δ＜ｅ≦０：Ｚ＜０のとき …１ ０≦ｅ≦（１−2-N）Δ：０≦Ｚ≦（１−2-N）Δ
のとき …２ ０≦ｅ＜Δ：（１−2-N）Δ＜Ｚのとき …３ 第３図で示される切り上げ関係を持つ回路に、
直流バイアス成分が０の信号が入力されたとき、
切り上げ後の信号の直流バイアス成分を調べる。
下記の第１表は、切り上げ後の信号のレベルと、
そのレベルになる確率を示している。ただし、Δ
は2-(M-N-1)とする。また、Ｑ＝2-Nとする。各レ
ベル値と、その値になる確率の積和により、切り
上げ後の平均レベル、すなわち直流バイアス成分
をみると、−Δ／2N+1となり、マイナス側に直流
バイアス成分が発生している。 [Technical field of the invention] This invention relates to digital filters, speech synthesis,
The present invention is used in the digital signal processing field represented by melody synthesis and the like, and particularly relates to a digital signal processing circuit having a multiplication rounding function for improving errors in multiplication results, and at the same time a multiplication result amplification function. [Technical Background of the Invention] Conventionally, rounding of multiplication results used in digital signal processing involves truncating the lower several bits or rounding off the lower several bits. Although rounding up is not normally performed in consideration of stability, it plays an important role in melody synthesis using lattice filters used in recent speech synthesis. As a technique using this rounding up process, for example, the Acoustical Society of Japan Speech Study Group Material S82-04 (April 26, 1982)
``Study of musical sound generation in PARCOR speech synthesis LSI'' written by Hibino et al., published on pages 25 to 32 of ``Published by J.D.'', is known. Truncation processing and rounding processing essentially have the function of attenuating the true value, so for example, when using the impulse response of a lattice filter to generate a damped sine wave of a desired frequency and using it as a melody scale signal. , the decay time constant is too large to be used practically as a musical scale. Therefore, the technique described in the above-mentioned document proposes rounding up the multiplication result to perform a type of amplification. [Problems with Background Art] However, the rounding-up method according to the technique of the above-mentioned document has the following problems. That is, now we have obtained the M-bit multiplication result Z, and its lower N
Let the M-bit data after rounding up the bits be Z'. However, it is assumed that Z and Z' are both expressed as two's complement numbers. According to the method in the above document, if Z is positive or zero, all the lower N bits are set to the "1" level, and when Z is negative, all the lower N bits are set to the "0" level. Now｜Z｜≦
1, FIG. 3 shows the relationship between Z and Z'. In FIG. 3, the broken line shows the relationship between Z and Z' when rounding up is not performed, and the data Z' after rounding up changes in a stepwise manner as shown by the solid line. Therefore, the error e between Z and Z' is expressed as e=Z'-Z
When defined, the following formulas hold true. However, Δ
is defined as 2 -(MN-1) . -Δ<e≦0: When Z<0…1 0≦e≦(1-2 -N ) Δ:0≦Z≦(1-2 -N ) Δ
When...2 0≦e<Δ: (1-2 -N ) When Δ<Z...3 In the circuit with the rounding-up relationship shown in Figure 3,
When a signal with a DC bias component of 0 is input,
Examine the DC bias component of the signal after rounding up.
Table 1 below shows the signal level after rounding up,
It shows the probability of reaching that level. However, Δ
is 2 -(MN-1) . Also, let Q = 2 -N . Looking at the average level after rounding up, that is, the DC bias component, from the product sum of each level value and the probability of reaching that value, it becomes -Δ/2 N+1 , and the DC bias component is generated on the negative side.

【表】【table】

〔発明の目的〕[Purpose of the invention]

この発明は上記のような事情を考慮してなされ
たものでありその目的は、演算結果の誤差精度が
改善でき、かつ増幅機能を有し、いいかえれば負
の直流バイアスを減少させることができ、かつハ
ードウエア量も従来に比較してほとんど増加しな
いデイジタル信号処理回路を提供することにあ
る。 〔発明の概要〕 上記目的を達成するためこの発明のデイジタル
信号処理回路にあつては、乗算回路によつて２の
補数表現された第１および第２の２進データを乗
算し、一定ビツト数の下位ビツトを切捨てて乗算
結果を得て、上記乗算結果を上位ビツトデータと
しかつ上記乗算結果の最上位ビツトデータの反転
データをそれよりも下位ビツトの各データとする
第３の２進データを一方の入力データとして、２
の補数表現された第４の２進データを他方の入力
データとしてそれぞれ加減算回路に供給し、この
加減算回路で制御信号に基づいて上記第３および
第４の２進データの加減算を行ない。この加減算
におけるキヤリー入力として上記加減算回路で加
算が行われる際には上記乗算結果の最上位ビツト
データの反転データを供給し、減算が行われる際
には最下位ビツトデータとして上記乗算結果の最
上位ビツトデータを供給するようにしている。 〔発明の実施例〕 次にこの発明の実施例の説明の前にこの発明の
原理について説明する。いま、４ビツトのデータ
Ｘ＝（X4，X3，X2，X1）とＹ＝（Y4，Y3，Y2，
Y1）とを乗算し、その結果の上位の４ビツトで
あるＱ＝（Q4，Q3，Q2，Q1）を乗算結果として
取出し、その４ビツトデータの下位２ビツトを切
上げる場合を考える。ただし、上記４ビツトのデ
ータＸとＹとは２の補数表現されており、各ビツ
トデータの添字の大きい方がMSBであり、小さ
い方がLSBであるとする。 ここで、Ｑ＝（Q4，Q3，Q2，Q1）の下位２ビ
ツトQ2とQ1を切上げるのだから、Ｑが正と負の
場合とで切上げ後のデータQ′はそれぞれ次のよ
うになる。 Q′＝（０，Q3＋１，０，０）：Ｑ≧０（Q4＝０）
…４ Q′＝（１，Q3，０，０） ：Ｑ＜０（Q4＝１）
…５ 次に切上げ処理後の値Q′と、データＺの加算
もしくは減算を行なう。すなわち、Ｚ＋Q′また
はＺ−Q′を行なう。上記の乗算および加減算を
実行するためには、切上げ時に上記４式で示すよ
うに、１回の加算およびその後の加減算で１回の
加減算を行なう必要があるが、この発明の回路で
はこれらの演算を第１図に示すような実施例回路
で実行するようにしている。 すなわち、第１図はこの発明に係るデイジタル
信号処理回路の一実施例の構成を示す回路図であ
る。図において１１はそれぞれ４ビツトのデータ
入力端子A4ないしA1およびB4ないしB1を有し、
これら入力端子に供給される２の補数表現された
一対のデータの乗算を行なう乗算回路であり、一
対のデータとして上記データＸ＝（X4，X3，X2，
X1）およびＹ＝（Y4，Y3，Y2，Y1）が供給され
る。上記乗算回路１１の乗算結果Ｑ＝（Q4，Q3，
Q2，Q1）のうち上位２ビツトのデータQ4および
Q3が加減算回路１２に供給される。この加減算
回路１２はそれぞれ４ビツトのデータ入力端子
E4ないしE1およびF4ないしF1を有し、加／減算
制御信号に応じてこれら入力端子に供給される２
の補数表現された一対のデータの間で加算もしく
は減算を乗算を行なうものであり、一方のデータ
入力端子E4ないしE1にはデータとして上記デー
タＺ＝（Z4，Z3，Z2，Z1）が供給され、他方のデ
ータ入力端子F4ないしF1のうち上位の２ビツト
F4，F3には上記データQ4およびQ3がそれぞれ供
給され、下位の２ビツトF2，F1には上記データ
Ｑを最上位ビツトのデータQ4がインバータ１３
を介して供給される。すなわち、データ入力端子
F2，F1にはデータQ4の反転データが並列に供給
される。また、上記加減算回路１２には最下位ビ
ツトのデータ入力端子としてキヤリーデータ入力
端子Ｃが設けられており、この加減算回路１２で
減算が行われる際にこの入力端子Ｃには上記イン
バータ１３の出力データがインバータ１４および
スイツチ１５を介して供給されるようになつてお
り、また、この加減算回路１２で加算が行われる
際にこの入力端子Ｃには上記インバータ１３の出
力データがスイツチ１６を介して供給されるよう
になつている。 上記加減算回路１２は以下のような演算動作を
行なう。まず、加算回路として動作するときに
は、（E4，E3，E2，E1）＋（F4，F3，F2，F1）＋
（０，０，０，Ｃ）＝（S4，S3，S2，S1）なる演算
を行なう。減算回路として動作するときには、
（E4，E3，E2，E1）＋（4，3，2，1）＋（０，
０，０，Ｃ）＝（S4，S3，S2，S1）なる演算を行な
う。 次にこのような構成の回路で、先に原理の説明
のところで述べたような演算が実行されることを
以下に説明する。まず、上記４および５式をそれ
ぞれ次のように変形する。 Q′＝（０，Q3，１，１）＋１ ＝（Q4，Q3，4，4）＋4：Ｑ≧０（Q4＝
０） …６ Q′＝（１，Q3，０，０）＋０ ＝（Q4，Q3，4，4）＋4：Ｑ＜０（Q4＝
１） …７ 従つて、Qa＝（Q4，Q3，4，4）とすると、 Q′＝Qa＋4 …８ となる。この８式により加減算回路１２で行われ
る前記Ｚ＋Q′またはＺ−Q′の演算はそれぞれ次
の式で表わされるような演算となる。 Ｚ＋Q′＝Ｚ＋Qa＋4（加算のとき） …９ Ｚ−Q′＝Ｚ−（Qa＋4） ＝Ｚ＋−4＋１ ＝Ｚ＋＋Q4（減算のとき） …10 上記９式および10式の演算はとりもなおさず第
１図回路における加減算回路１２における演算動
作である。 上記実施例回路における元のデータＺの変化に
対する切上げ後のデータZ′との関係は第２図に示
すようになる。すなわち、Ｚが正もしくは零なら
ば下位Ｎビツトをすべて“０”レベルにして、さ
らに下位からＮ＋１ビツト目に１を加算する。Ｚ
が負ならば下位Ｎビツトをすべて“０”レベルに
する。 第２図で示される切り上げ関係を持つ回路に、
直流バイアス成分が０の信号が入力されたとき、
切り上げ後の信号の直流バイアス成分がどうなる
かをまとめて示したものが下記の第２表である。
第２表において、各レベル値と、その値になる確
率の積和により、切り上げ後の平均レベル、すな
わち直流バイアス成分は０になる。従来の方式で
はこれがマイナス側の直流バイアス成分−Δ／
2N+1であつたものが０となり、明らかに改善され
ている。 This invention was made in consideration of the above-mentioned circumstances, and its purpose is to improve the error accuracy of calculation results, and to have an amplification function, in other words, to reduce negative DC bias. Another object of the present invention is to provide a digital signal processing circuit in which the amount of hardware is hardly increased compared to the conventional one. [Summary of the Invention] In order to achieve the above object, the digital signal processing circuit of the present invention multiplies first and second binary data expressed in two's complement by a multiplier circuit to obtain a fixed number of bits. The lower bits of are truncated to obtain the multiplication result, and third binary data is generated in which the multiplication result is used as the upper bit data and the inverted data of the most significant bit data of the multiplication result is used as each data of the lower bits. As one input data, 2
The fourth binary data represented by the complement of is supplied as the other input data to the adder/subtracter circuit, and the adder/subtracter adds and subtracts the third and fourth binary data based on the control signal. When addition is performed in the addition/subtraction circuit, the inverted data of the most significant bit data of the multiplication result is supplied as a carry input in this addition/subtraction, and when subtraction is performed, the most significant bit data of the multiplication result is supplied as the least significant bit data. It is designed to supply bit data. [Embodiments of the Invention] Next, before explaining embodiments of the invention, the principle of the invention will be explained. Now, 4-bit data X = (X 4 , X 3 , X 2 , X 1 ) and Y = (Y 4 , Y 3 , Y 2 ,
Y 1 ), the upper 4 bits of the result, Q = (Q 4 , Q 3 , Q 2 , Q 1 ), are extracted as the multiplication result, and the lower 2 bits of the 4-bit data are rounded up. think. However, the above 4-bit data X and Y are expressed in two's complement numbers, and the larger subscript of each bit data is the MSB, and the smaller subscript is the LSB. Here, since the lower two bits Q 2 and Q 1 of Q = (Q 4 , Q 3 , Q 2 , Q 1 ) are rounded up, the data Q' after rounding up is as follows depending on whether Q is positive or negative. become that way. Q′=(0,Q 3 +1,0,0): Q≧0(Q 4 =0)
...4 Q′=(1,Q 3 ,0,0) :Q<0(Q 4 =1)
...5 Next, add or subtract the value Q' after rounding up and the data Z. That is, Z+Q' or Z-Q' is performed. In order to execute the above multiplication and addition/subtraction, it is necessary to perform one addition and one addition/subtraction at the time of rounding up and subsequent addition/subtraction, as shown in the above four formulas, but the circuit of the present invention can perform these operations. is executed by an embodiment circuit as shown in FIG. That is, FIG. 1 is a circuit diagram showing the configuration of one embodiment of a digital signal processing circuit according to the present invention. In the figure, 11 has 4-bit data input terminals A 4 to A 1 and B 4 to B 1 , respectively.
This is a multiplier circuit that multiplies a pair of two's complement data supplied to these input terminals, and the above data X=(X 4 , X 3 , X 2 ,
X 1 ) and Y=(Y 4 , Y 3 , Y 2 , Y 1 ) are supplied. The multiplication result of the multiplication circuit 11 is Q=(Q 4 , Q 3 ,
Q 2 , Q 1 ), the upper 2 bits of data Q 4 and
Q 3 is supplied to the addition/subtraction circuit 12 . Each of the adder/subtracter circuits 12 has a 4-bit data input terminal.
E 4 to E 1 and F 4 to F 1 and supplied to these input terminals in response to the addition/subtraction control signal.
Addition, subtraction , or multiplication is performed between a pair of data expressed as complements of Z 1 ) is supplied, and the upper two bits of the other data input terminal F 4 to F 1
The above data Q 4 and Q 3 are supplied to F 4 and F 3 , respectively, and the above data Q and the most significant bit data Q 4 are supplied to the lower two bits F 2 and F 1 .
Supplied via. That is, the data input terminal
Inverted data of data Q 4 is supplied to F 2 and F 1 in parallel. Further, the addition/subtraction circuit 12 is provided with a carry data input terminal C as a data input terminal for the least significant bit. Data is supplied via an inverter 14 and a switch 15, and when addition is performed in this addition/subtraction circuit 12, output data from the inverter 13 is supplied to this input terminal C via a switch 16. supply is becoming available. The addition/subtraction circuit 12 performs the following arithmetic operations. First, when operating as an adder circuit, (E 4 , E 3 , E 2 , E 1 ) + (F 4 , F 3 , F 2 , F 1 ) +
The calculation (0, 0, 0, C) = (S 4 , S 3 , S 2 , S 1 ) is performed. When operating as a subtraction circuit,
(E 4 , E 3 , E 2 , E 1 ) + ( 4 , 3 , 2 , 1 ) + (0,
The following calculation is performed: 0, 0, C)=(S 4 , S 3 , S 2 , S 1 ). Next, it will be explained below that the circuit having such a configuration executes the calculations as described in the explanation of the principle. First, the above equations 4 and 5 are transformed as follows. Q′ = (0, Q 3 , 1, 1) + 1 = (Q 4 , Q 3 , 4 , 4 ) + 4 :Q≧0(Q 4 =
0) ...6 Q' = (1, Q 3 , 0, 0) + 0 = (Q 4 , Q 3 , 4 , 4 ) + 4 : Q < 0 (Q 4 =
1) ...7 Therefore, if Qa=(Q 4 , Q 3 , 4 , 4 ), then Q'=Qa+ 4 ...8. Based on these 8 equations, the calculations of Z+Q' or Z-Q' performed by the addition/subtraction circuit 12 are as shown in the following equations. Z+Q'=Z+Qa+ 4 (for addition)...9 Z-Q'=Z-(Qa+ 4 ) =Z+- 4 +1 =Z++Q 4 (for subtraction)...10 The operations in equations 9 and 10 above are not changed. First, there is a calculation operation in the addition/subtraction circuit 12 in the circuit of FIG. The relationship between the rounded-up data Z' and the change in the original data Z in the circuit of the above embodiment is as shown in FIG. That is, if Z is positive or zero, all the lower N bits are set to the "0" level, and 1 is added to the N+1th bit from the lowest. Z
If is negative, all lower N bits are set to "0" level. In the circuit with the rounding up relationship shown in Figure 2,
When a signal with a DC bias component of 0 is input,
Table 2 below summarizes what happens to the DC bias component of the signal after rounding up.
In Table 2, the average level after rounding up, that is, the DC bias component, becomes 0 based on the product sum of each level value and the probability of reaching that value. In the conventional method, this is the negative DC bias component -Δ/
2 What was N+1 has become 0, which is clearly an improvement.

【表】【table】

Claims (1)

【特許請求の範囲】 １ ２の補数表現された第１および第２の２進デ
ータを乗算し、一定ビツト数の下位ビツトを切捨
てて乗算結果を得る乗算回路と、上記乗算結果を
上位ビツトデータとしかつ上記乗算結果の最上位
ビツトデータの反転データをそれよりも下位ビツ
トの各データとする第３の２進データが一方の入
力データとして、２の補数表現された第４の２進
データが他方の入力データとしてそれぞれ供給さ
れ、制御信号に基づいて上記第３および第４の２
進データの加減算を行なう加減算回路と、上記加
減算回路で加算が行われる際には最下位ビツトデ
ータとして上記乗算結果の最上位ビツトデータの
反転データを供給し、減算が行われる際には最下
位ビツトデータとして上記乗算結果の最上位ビツ
トデータを供給する手段とを具備したことを特徴
とするデイジタル信号処理回路。 ２ 前記加減算回路の最下位ビツトデータがキヤ
リー入力データにされている特許請求の範囲第１
項に記載のデイジタル信号処理回路。[Scope of Claims] 1. A multiplication circuit that obtains a multiplication result by multiplying first and second binary data expressed in two's complement and truncating a certain number of lower bits, and converting the multiplication result into upper bit data. In addition, the third binary data in which the inverted data of the most significant bit data of the above multiplication result is used as each data of the lower bits is one input data, and the fourth binary data expressed in two's complement is are respectively supplied as the other input data, and the third and fourth two
An addition/subtraction circuit that performs addition/subtraction of base data, and when addition is performed in the addition/subtraction circuit, the inverted data of the most significant bit data of the multiplication result is supplied as the least significant bit data, and when subtraction is performed, the least significant bit data is supplied as the least significant bit data. A digital signal processing circuit comprising means for supplying the most significant bit data of the multiplication result as bit data. 2. Claim 1, wherein the least significant bit data of the addition/subtraction circuit is used as carry input data.
The digital signal processing circuit described in .
JP60066932A 1985-03-30 1985-03-30 Digital signal processing circuit Granted JPS61226835A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60066932A JPS61226835A (en) 1985-03-30 1985-03-30 Digital signal processing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60066932A JPS61226835A (en) 1985-03-30 1985-03-30 Digital signal processing circuit

Publications (2)

Publication Number Publication Date
JPS61226835A JPS61226835A (en) 1986-10-08
JPH0353651B2 true JPH0353651B2 (en) 1991-08-15

Family

ID=13330259

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60066932A Granted JPS61226835A (en) 1985-03-30 1985-03-30 Digital signal processing circuit

Country Status (1)

Country Link
JP (1) JPS61226835A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01108806A (en) * 1987-10-21 1989-04-26 Nec Corp Digital filter

Also Published As

Publication number Publication date
JPS61226835A (en) 1986-10-08

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