JPH0353302A - Pulse output device for digital controller - Google Patents
Pulse output device for digital controllerInfo
- Publication number
- JPH0353302A JPH0353302A JP18915589A JP18915589A JPH0353302A JP H0353302 A JPH0353302 A JP H0353302A JP 18915589 A JP18915589 A JP 18915589A JP 18915589 A JP18915589 A JP 18915589A JP H0353302 A JPH0353302 A JP H0353302A
- Authority
- JP
- Japan
- Prior art keywords
- output
- control
- pulse
- width
- pulse width
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007423 decrease Effects 0.000 abstract description 7
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000001035 drying Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Control By Computers (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
（産業上の利用分野）
本発明はディジタルコントローラのパルス出力装置に関
する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a pulse output device for a digital controller.
（従来の技術）
従来のディジタルコントローラにおけるパルス出力装置
は，制御周期毎の制御出力値（ΔＭＶ）に変換係数を乗
してパルス幅に変換している。(Prior Art) A pulse output device in a conventional digital controller converts the control output value (ΔMV) for each control period into a pulse width by multiplying it by a conversion coefficient.
即ち、
Ｐ＝α・ΔＭＶ＋Ｐ’ ・・（υ式において
、Ｐは出力パルス幅，αは変換係数，Ｐ′はパックラッ
シュ補償値であり、変換係数αはα＝Ａ／ｘにて決定さ
れる。但し，Ａはフルストローク動かすのに必要な時間
、Ｘはコントローラ出力分解能［ Ｓ ］ Ｘ １００
％である。That is, P=α・ΔMV+P' (In the υ formula, P is the output pulse width, α is the conversion coefficient, P' is the packlash compensation value, and the conversion coefficient α is determined by α=A/x. .However, A is the time required to move the full stroke, and X is the controller output resolution [S] x 100
%.
（発明が解決しようとする課題）
従来のアナログコントローラでは制御が連続して行われ
ることにより、パルス出力要否の決定も連続で実行され
ていた。しかしながら，ディジタルコント口ーラではＣ
ＰＵの処理に時間がかかるため、パルス出力の決定はあ
る周期（制御周期）毎に（１）式より実行される。この
ため、制御出力値が小さく、パルス幅が制御周期よりも
短い場合が連続した時，パルス出力は制御周期毎にＯＮ
／ＯＦＦを操り返し、燥作端に悪影響を与える。(Problems to be Solved by the Invention) In conventional analog controllers, control is performed continuously, so that determination of whether or not pulse output is necessary is also performed continuously. However, in digital controllers, C
Since PU processing takes time, the pulse output is determined every certain cycle (control cycle) using equation (1). Therefore, when the control output value is small and the pulse width is shorter than the control cycle, the pulse output is turned ON every control cycle.
/OFF is reversed and has a negative effect on the drying end.
本発明の目的はパルス幅出力において，燥作量が過少な
場合においても操作端に連続出力を行う手段を堤供する
ことにある。An object of the present invention is to provide a means for continuously outputting pulse width output to the operating end even when the amount of drying is too small.
（課題を解決するための手段）
本発明は制御出力を予？ｌＩｌｌ演算を使用して補正す
ることを特徴としたディジタルコントローラのパルス出
力装置である。(Means for Solving the Problems) The present invention provides a method for predicting control outputs. This is a pulse output device for a digital controller characterized by correction using IIll calculation.
（作 用）
本発明に於では制御出力に対して予８１！Ｉ機能を付加
し、パルス幅出力を補正する。(Function) In the present invention, the control output is predetermined by 81! Add I function to correct pulse width output.
（実施例）
次に本発明の一実施例を説明する。第■図はディジタル
コントローラの制御演算を行なう制御演算機能１と、制
御演算機能１からの制御出力ΔＭＶによってコントロー
ラ制御出力の将来方向の予８１１演算を行なう予２１１
！Ｉ演算機能５と、予ｌ１１’ｌ演算機能５の予ｉ１１
！１演算結果によって制御演算機能上の制御出力△ＭＶ
を補正する補正演算機能３と，補正演算機能３からの補
正演算値をパルス幅に変換して出力するパルス幅出力機
能４とを具備してなるディジタルコントローラのパルス
出力装置を示している。尚、ｅは儲差である。(Example) Next, an example of the present invention will be described. Figure 3 shows a control calculation function 1 that performs control calculations for the digital controller, and a prediction 211 that performs a prediction 811 calculation of the future direction of the controller control output based on the control output ΔMV from the control calculation function 1.
! I arithmetic function 5 and preliminarily i11'l arithmetic function 5's preliminarily i11
! 1 Control output △MV on the control calculation function based on the calculation result
This figure shows a pulse output device for a digital controller, which is equipped with a correction calculation function 3 for correcting the correction calculation function 3, and a pulse width output function 4 for converting the correction calculation value from the correction calculation function 3 into a pulse width and outputting the pulse width. Note that e is the profit margin.
即ち、制御演算機能１から出力された制御出力ΔＭＶの
方向性を予測演算機能５にて予測する。補正演算機能３
ではパルス出力幅が制御周期より短い場合，予測演算結
果をもとにパルス出力幅を決定する。That is, the directionality of the control output ΔMV output from the control calculation function 1 is predicted by the prediction calculation function 5. Correction calculation function 3
If the pulse output width is shorter than the control period, the pulse output width is determined based on the predicted calculation results.
予測演算結果においては制御出力ΔＭＶの方向性を、増
大一増一減一減小等に区分し，制御出力ΔＭＶの方向性
が増大、減小の場合に各々パルス幅を調整する。制御出
力ΔＭＶが増大する場合，パルス出力幅を制御周期に設
定し、一方、制御出力ΔＭＶが減小する場合、パルス出
力を停止する。In the prediction calculation result, the directionality of the control output ΔMV is divided into increases, increases, decreases, decreases, etc., and the pulse width is adjusted respectively when the directionality of the control output ΔMV is increasing or decreasing. When the control output ΔMV increases, the pulse output width is set to the control period, and on the other hand, when the control output ΔMV decreases, the pulse output is stopped.
第２図の１１はパルス出力幅判定回路、ｌ２はパルス出
力幅回路． １３はΔＭＶ増大回路． １４は△ＭＶ減
少回路、ｌ５はパルス出力停止回路、第３図の２１はΔ
Ｍ■微分値計算回路，２２は偏差判定回路，２３は△Ｍ
Ｖ微分値判定回路である。11 in FIG. 2 is a pulse output width determination circuit, and l2 is a pulse output width circuit. 13 is a ΔMV increase circuit. 14 is a ΔMV reduction circuit, l5 is a pulse output stop circuit, and 21 in Fig. 3 is a ΔMV reduction circuit.
M■ Differential value calculation circuit, 22 is a deviation judgment circuit, 23 is △M
This is a V differential value determination circuit.
本発明により、不必要なパルス幅出力を抑え、連続した
パルス幅出力を操作端へ送信することが可能となる。According to the present invention, unnecessary pulse width output can be suppressed and continuous pulse width output can be transmitted to the operating end.
第ｌ図は本発明の一実施例を示すバルス出カ装置の構成
図、第２図は補正演算部の詳細ブロック説明図、第３図
は予ｄ１リ演算部の詳細ブロック説明図である。FIG. 1 is a block diagram of a pulse output device showing an embodiment of the present invention, FIG. 2 is a detailed block diagram of a correction calculation unit, and FIG. 3 is a detailed block diagram of a pre-d1 calculation unit.
Claims (1)
能と、この制御演算機能からの出力によってコントロー
ラ制御出力の将来方向の予測演算を行なう予測演算機能
と、この予測演算機能の予測演算結果によって前記制御
演算機能の制御出力を補正する補正演算機能と、この補
正演算機能からの補正演算値をパルス幅に変換して出力
するパルス幅出力機能とを具備してなるディジタルコン
トローラのパルス出力装置。A control calculation function that performs control calculations for the digital controller; a predictive calculation function that performs predictive calculations on the future direction of the controller control output based on the output from this control calculation function; A pulse output device for a digital controller comprising a correction calculation function for correcting a control output and a pulse width output function for converting a correction calculation value from the correction calculation function into a pulse width and outputting the pulse width.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18915589A JPH0353302A (en) | 1989-07-21 | 1989-07-21 | Pulse output device for digital controller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18915589A JPH0353302A (en) | 1989-07-21 | 1989-07-21 | Pulse output device for digital controller |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0353302A true JPH0353302A (en) | 1991-03-07 |
Family
ID=16236362
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18915589A Pending JPH0353302A (en) | 1989-07-21 | 1989-07-21 | Pulse output device for digital controller |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0353302A (en) |
-
1989
- 1989-07-21 JP JP18915589A patent/JPH0353302A/en active Pending
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