JPH0350726A - Structure of interlayer wiring connection part and its forming method - Google Patents

Structure of interlayer wiring connection part and its forming method

Info

Publication number
JPH0350726A
JPH0350726A JP18450389A JP18450389A JPH0350726A JP H0350726 A JPH0350726 A JP H0350726A JP 18450389 A JP18450389 A JP 18450389A JP 18450389 A JP18450389 A JP 18450389A JP H0350726 A JPH0350726 A JP H0350726A
Authority
JP
Japan
Prior art keywords
metal
wiring
insulating film
forming
interlayer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18450389A
Other languages
Japanese (ja)
Inventor
Hideyuki Nakano
秀之 中野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP18450389A priority Critical patent/JPH0350726A/en
Publication of JPH0350726A publication Critical patent/JPH0350726A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent the disconnection caused by step-difference, improve device characteristics, and increase manufacturing yield, by buring metal material forming a flat surface with an interlayer insulating film, in an insulating film of an interlayer wiring connection part. CONSTITUTION:After a tantalum(Ta) film is formed on a glass substrate 1, a lower wiring 2 is formed by patterning. A chromium film is formed, a contact forming part on the lower wiring 2 is masked with contact metal 6, the tantalum of the lower wiring 2 is anodized, and a tantalum pentaoxide(TaOX) insulating film 3 is grown. After a film of upper electrode material is formed, an upper wiring 5 is formed by patterning, and connected with the lower wiring 2 via the contact metal 6, thereby forming a connection part where metal is buried in an insulating film, so as to be connected with the lower wiring 2 via contact metal 6.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、絶縁性基板上における層間配線接続部の構造
およびその形成方法に関し、ざらに詳しくはアクティブ
マトリックス形液晶デイスプレィ等に用いられる層間配
線接続部の構造およびその形成方法に関するものである
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of an interlayer wiring connection portion on an insulating substrate and a method for forming the same, and more specifically, to an interlayer wiring used in an active matrix liquid crystal display, etc. The present invention relates to a structure of a connecting portion and a method of forming the same.

[従来の技術] 第3図(a)〜(C)は、絶縁膜を介した配線のコンタ
クトをとる場合における従来の層間配線接続部の形成方
法を工程順に示した接続部の断面図である。
[Prior Art] FIGS. 3(a) to 3(C) are cross-sectional views of a connecting portion showing a conventional method for forming an interlayer wiring connecting portion in order of steps when contacting wiring through an insulating film. .

まず第3図(a)に示す′ように、ガラス基板11に下
部電極材料を成膜した復、パターニングし、下部配線1
2を形成する。次いでこの上に層間絶縁膜13をスパッ
タ法おるいはプラズマCVD法により成膜する。次に、
フォトレジスト14を塗布してコンタクト部を感光し、
現像する。次に、第3図(b)に示すように、ドライエ
ツチングあるいはウェット系エツチングにより絶縁膜1
3のコンタクトホール形成を行う。次に、第3図(C)
に示すように、フォトレジスト14を除去し、上部電極
材料を成膜して所望の大きさにパターニングし、上部配
線15の接続部が完成する。
First, as shown in FIG. 3(a), a lower electrode material is deposited on a glass substrate 11, and then patterned to
form 2. Next, an interlayer insulating film 13 is formed thereon by sputtering or plasma CVD. next,
Apply photoresist 14 and expose the contact area,
develop. Next, as shown in FIG. 3(b), the insulating film 1 is etched by dry etching or wet etching.
3. Form contact holes. Next, Figure 3 (C)
As shown in FIG. 3, the photoresist 14 is removed, a film of upper electrode material is formed and patterned to a desired size, and the connection portion of the upper wiring 15 is completed.

[発明が解決しようとする課題] しかしながら、以上のようにして形成されるコンタクト
ホールを用いた層間配線の接続法は、上部配線と下部配
線に層間絶縁膜と同じ段差がおり、その段差は補填され
ずに残るため、このホールの形状によっては上部配線の
断線を生じ、歩留まりの低下をきたすことがあった。そ
のため、層間配線接続部のコンタクトホールを平坦化さ
せる方法として、バイアススパッタ法によって上部電極
材料を成膜する方法や、あるいは上部電極材料を成膜後
、レーザによりその材料を溶解しホールを埋める方法等
が行われているものの、上部配線の断線を完全に防止す
ることはできなかった。
[Problems to be Solved by the Invention] However, in the method for connecting interlayer wiring using contact holes formed as described above, there is a difference in level between the upper wiring and the lower wiring, which is the same as that in the interlayer insulating film, and the difference in level cannot be compensated for. Depending on the shape of this hole, the upper wiring may be disconnected, resulting in a decrease in yield. Therefore, as a method for flattening the contact hole of the interlayer wiring connection part, there is a method of depositing the upper electrode material by bias sputtering method, or a method of depositing the upper electrode material and then melting the material with a laser to fill the hole. Although such measures have been taken, it has not been possible to completely prevent disconnection of the upper wiring.

さらに、従来の方法では必ず絶縁膜のエツチング工程が
必要でおり、そのため、その際のエツチングプロセス条
件により、デバイス特性に大きなばらつきを生じ、製造
歩留まりの低下の原因になるという問題点があった。
Furthermore, conventional methods always require an etching step for the insulating film, which has the problem of causing large variations in device characteristics depending on the etching process conditions and causing a reduction in manufacturing yield.

本発明は以上述べたような従来の課題に鑑みてなされた
もので、段差による断線がなく、デバイス特性が良好で
、製造歩留まりの向上した層間配線接続部の構造および
その形成方法を提供することを目的とする。
The present invention has been made in view of the above-mentioned conventional problems, and an object of the present invention is to provide a structure of an interlayer wiring connection part and a method for forming the same, which are free from disconnection due to steps, have good device characteristics, and improve manufacturing yield. With the goal.

[課題を解決するための手段] 本発明は、絶縁性基板上に下部金属配線、絶縁膜および
上部金属配線が順次形成され、該下部金属配線と該上部
金属配線は接続部を介して電気的に接続されてなる層間
配線接続部の構造において、下部金属配線は酸化可能な
第1の金属で形成され、絶縁膜は該第1の金属の酸化物
で形成され、かつ接続部は前記絶縁膜中に該絶縁膜と平
坦な表面を有して埋設された酸化されにくい第2の金属
で形成されていることを特徴とする層間配線接続部の構
造、および絶縁性基板上に酸化可能な第1の金属よりな
る下部金属配線を形成する工程と、該下部金属配線上の
所定の箇所に酸化されにくい第2の金属を島状に形成す
る工程と、該第2の金属をマスクとして前記下部金属配
線を選択的に酸化し、得られる絶縁膜が前記第2の金属
の表面と同じ高さになるまで酸化する工程と、該工程で
形成された前記第2の金属面を含む平坦面上に上部金属
配線を成膜する工程とを備えてなることを特徴とする層
間配線接続部の形成方法でおる。
[Means for Solving the Problems] In the present invention, a lower metal wiring, an insulating film, and an upper metal wiring are sequentially formed on an insulating substrate, and the lower metal wiring and the upper metal wiring are electrically connected via a connecting portion. In the structure of the interlayer interconnection connection section, the lower metal interconnection is formed of an oxidizable first metal, the insulating film is formed of an oxide of the first metal, and the connection section is connected to the insulating film. The structure of the interlayer wiring connection portion is characterized in that it is formed of a second metal that is hard to oxidize and has a flat surface with the insulating film, and is formed of a second metal that is hard to oxidize and has a flat surface with the insulating film. forming a second metal that is difficult to oxidize in an island shape at a predetermined location on the lower metal wiring; A step of selectively oxidizing the metal wiring until the obtained insulating film is at the same height as the surface of the second metal, and a flat surface including the second metal surface formed in the step. 1. A method for forming an interlayer wiring connection portion, comprising the steps of: and forming an upper metal wiring.

[作用] 本発明による層間配線接続部は、層間絶縁膜と平坦面を
形成する金属材料が絶縁膜中に埋設されているため、上
部配線は平坦な膜上に形成されることとなり、従って、
従来のようにコンタクトホール部の凹部に上部配線が形
成されることがなく、上部配線の断線が皆無になる。
[Function] In the interlayer wiring connection part according to the present invention, since the metal material forming the interlayer insulating film and the flat surface is buried in the insulating film, the upper wiring is formed on the flat film, and therefore,
Unlike the conventional method, the upper wiring is not formed in the recessed part of the contact hole portion, and there is no disconnection of the upper wiring.

また、本発明の層間配線接続部の形成方法では、下部金
属配線の材料として酸化可能な第1の金属を用いる。そ
の上に、クロム、チタン、金などの酸化されない第2の
金属を島状に形成し、該第2の金属をマスクとして陽極
酸化法、熱酸化法等によって選択的に下部金属を酸化し
て層間絶縁膜とりる。そのため、コンタクトホール形成
のためのエツチングプロセスが省略でき、安定にデバイ
ス形成をすることが可能になる。また、2層の絶縁膜を
用いた場合もコンタクトホール段差が低減でき、接続部
の信頼性が増す。
Further, in the method for forming an interlayer wiring connection portion of the present invention, an oxidizable first metal is used as the material of the lower metal wiring. On top of that, a non-oxidizable second metal such as chromium, titanium, or gold is formed in the form of an island, and the lower metal is selectively oxidized by an anodic oxidation method, thermal oxidation method, etc. using the second metal as a mask. Take an interlayer insulating film. Therefore, the etching process for forming contact holes can be omitted, and devices can be stably formed. Further, when a two-layer insulating film is used, the contact hole level difference can be reduced, and the reliability of the connection part is increased.

[実施例] 以下、本発明の実施例について、図面を参照して詳細に
説明する。
[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

第1図は本発明の層間配線接続部の一実施例の断面図で
ある。図示するように、ガラス基板1上に0.2.cm
のタンタルで形成された下部配線2が形成されている。
FIG. 1 is a sectional view of one embodiment of the interlayer wiring connection portion of the present invention. As shown in the figure, 0.2. cm
A lower wiring 2 is formed of tantalum.

その上の0.2層mのTaoxよりなる層間絶縁膜3に
は凹部がなく、o、 1柳のクロムJ、りなる上部配線
5は平面上に形成されている。
The interlayer insulating film 3 made of Taox and having a thickness of 0.2 m thereon has no recesses, and the upper wiring 5 made of chromium J of willow is formed on a flat surface.

なおコンタクト金属6は、島状に形成された0.2廟の
クロムである。このような接続部の形成により、上部配
線5がいかに薄くても、また絶縁膜3が厚くても、上下
の接続は確実にとれる。従って、この接続部の信頼性は
著しく向上する。
Note that the contact metal 6 is 0.2 cm of chromium formed into an island shape. By forming such a connection part, no matter how thin the upper wiring 5 is or how thick the insulating film 3 is, the upper and lower connections can be reliably established. Therefore, the reliability of this connection is significantly improved.

第2図(a)〜(d)は本発明の層間配線接続部の形成
方法を工程順に示した断面図である。
FIGS. 2(a) to 2(d) are cross-sectional views showing the method for forming an interlayer wiring connection portion according to the present invention in the order of steps.

まず第2図(a)に示すように、絶縁性基板として用い
たガラス基板1上にタンタル(Ta)をスパッタ法によ
りo、 1庫程度成膜した後、バターニングして下部配
線2を形成する。次に、第2図(b)に示すように、ク
ロムを0.1〜0.2庫裡度スパッタ法で成膜し、下部
配線2上のコンタクト形成部をコンタクト金属6でマス
クする。次に、第2図(C)に示すように、下部配線2
のタンタルをクエン酸水溶液を用いて陽極酸化を行い、
金属マスクであるコンタクト金属6と同じ膜厚まで五酸
化タンタル(TaOX)絶縁膜3を成長する。次に、第
2図(d)にホすように、上部電極材料を成膜後、パタ
ーニングを行って上部配線5を形成し、コンタクト金属
6を介して下部配線2と接続することにより、絶縁膜中
に金属が埋め込まれた接続部を形成する。
First, as shown in FIG. 2(a), a film of tantalum (Ta) is formed by sputtering on a glass substrate 1 used as an insulating substrate, and then the lower wiring 2 is formed by buttering. do. Next, as shown in FIG. 2(b), a chromium film is formed by sputtering at a depth of 0.1 to 0.2, and the contact formation portion on the lower wiring 2 is masked with a contact metal 6. Next, as shown in FIG. 2(C), the lower wiring 2
tantalum is anodized using a citric acid aqueous solution,
A tantalum pentoxide (TaOX) insulating film 3 is grown to the same thickness as the contact metal 6 serving as a metal mask. Next, as shown in FIG. 2(d), after forming the upper electrode material, patterning is performed to form the upper wiring 5, which is connected to the lower wiring 2 via the contact metal 6 to provide insulation. A connection part is formed in which metal is embedded in the film.

本実施例では、絶縁膜を陽極酸化法で形成したが、熱酸
化法等の他の酸化法を用いてもよい。また、金属マスク
の材料としては、本実施例ではクロムを用いたが、他の
金属、例えばチタン、金、ニッケル等でもよい。
In this embodiment, the insulating film was formed by an anodic oxidation method, but other oxidation methods such as a thermal oxidation method may be used. Furthermore, although chromium is used as the material for the metal mask in this embodiment, other metals such as titanium, gold, nickel, etc. may be used.

[発明の効果] 以上説明したように、本発明の層間配線接続部の構造に
よれば、コンタクトがとりたい任意の場所に既に金属が
埋まっているため、平坦面上に上部電極が形成でき、段
差による断線が皆無となり、製造歩留まりが向上する。
[Effects of the Invention] As explained above, according to the structure of the interlayer wiring connection part of the present invention, since the metal is already buried in any place where contact is desired, the upper electrode can be formed on a flat surface. There are no wire breaks due to steps, improving manufacturing yield.

また、本発明の層間配線接続部の形成方法によれば、絶
縁膜のエツチング工程が含まれないため、従来例と比べ
てエツチング形状によるコンタクト不良が低減できる効
果を有する。
Further, according to the method for forming an interlayer wiring connection portion of the present invention, since the step of etching the insulating film is not included, contact defects due to etched shapes can be reduced compared to the conventional method.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の層間配線接続部の一実施例の断面図、
第2図は本発明の層間配線接続部の形成方法の一実施例
を工程順に示す断面図、第3図は従来の層間配線接続部
の形成方法の一例を工程順に示す断面図である。 1.11・・・ガラス基板 2.12・・・下部配線 3.13・・・絶縁膜 5.15・・・上部配線 6・・・コンタクト金属 14・・・フォトレジスト
FIG. 1 is a sectional view of an embodiment of the interlayer wiring connection part of the present invention;
FIG. 2 is a cross-sectional view showing an example of a method for forming an interlayer wiring connection portion according to the present invention in the order of steps, and FIG. 3 is a cross-sectional view showing an example of a conventional method for forming an interlayer wiring connection portion in order of steps. 1.11...Glass substrate 2.12...Lower wiring 3.13...Insulating film 5.15...Upper wiring 6...Contact metal 14...Photoresist

Claims (2)

【特許請求の範囲】[Claims] (1)絶縁性基板上に下部金属配線、絶縁膜および上部
金属配線が順次形成され、該下部金属配線と該上部金属
配線は接続部を介して電気的に接続されてなる層間配線
接続部の構造において、下部金属配線は酸化可能な第1
の金属で形成され、絶縁膜は該第1の金属の酸化物で形
成され、かつ接続部は前記絶縁膜中に該絶縁膜と平坦な
表面を有して埋設された酸化されにくい第2の金属で形
成されていることを特徴とする層間配線接続部の構造。
(1) A lower metal wiring, an insulating film, and an upper metal wiring are sequentially formed on an insulating substrate, and the lower metal wiring and the upper metal wiring are electrically connected via a connection part to form an interlayer wiring connection part. In the structure, the lower metal interconnect is an oxidizable first
The insulating film is formed of an oxide of the first metal, and the connecting portion is formed of a second oxidizable metal that is buried in the insulating film and has a flat surface with the insulating film. A structure of an interlayer wiring connection part characterized by being formed of metal.
(2)絶縁性基板上に酸化可能な第1の金属よりなる下
部金属配線を形成する工程と、該下部金属配線上の所定
の箇所に酸化されにくい第2の金属を島状に形成する工
程と、該第2の金属をマスクとして前記下部金属配線を
選択的に酸化し、得られる絶縁膜が前記第2の金属の表
面と同じ高さになるまで酸化する工程と、該工程で形成
された前記第2の金属面を含む平坦面上に上部金属配線
を成膜する工程とを備えてなることを特徴とする層間配
線接続部の形成方法。
(2) A step of forming a lower metal wiring made of an oxidizable first metal on an insulating substrate, and a step of forming an island-like second metal that is difficult to oxidize at a predetermined location on the lower metal wiring. a step of selectively oxidizing the lower metal wiring using the second metal as a mask until the resulting insulating film is at the same height as the surface of the second metal; A method for forming an interlayer wiring connection portion, comprising the step of forming an upper metal wiring on a flat surface including the second metal surface.
JP18450389A 1989-07-19 1989-07-19 Structure of interlayer wiring connection part and its forming method Pending JPH0350726A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18450389A JPH0350726A (en) 1989-07-19 1989-07-19 Structure of interlayer wiring connection part and its forming method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18450389A JPH0350726A (en) 1989-07-19 1989-07-19 Structure of interlayer wiring connection part and its forming method

Publications (1)

Publication Number Publication Date
JPH0350726A true JPH0350726A (en) 1991-03-05

Family

ID=16154329

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18450389A Pending JPH0350726A (en) 1989-07-19 1989-07-19 Structure of interlayer wiring connection part and its forming method

Country Status (1)

Country Link
JP (1) JPH0350726A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019530242A (en) * 2016-09-30 2019-10-17 アプライド マテリアルズ インコーポレイテッドApplied Materials,Incorporated Method for forming self-aligned vias

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019530242A (en) * 2016-09-30 2019-10-17 アプライド マテリアルズ インコーポレイテッドApplied Materials,Incorporated Method for forming self-aligned vias
US11094544B2 (en) 2016-09-30 2021-08-17 Applied Materials, Inc. Methods of forming self-aligned vias

Similar Documents

Publication Publication Date Title
JPH0350726A (en) Structure of interlayer wiring connection part and its forming method
KR100350936B1 (en) Semiconductor device
JP2001201418A (en) Electrostatic capacity type semiconductor pressure sensor and its manufacturing method
JP3216124B2 (en) Semiconductor thin film device and method of manufacturing the same
JPS63271958A (en) Formation of multilayer interconnection
JPS60210851A (en) Semiconductor device and manufacture thereof
JPH03125469A (en) Structure for mim capacitor
KR100324341B1 (en) Manufacturing method for pad on semiconductor device
JPH0570301B2 (en)
JPH10189606A (en) Bump of semiconductor device and manufacture thereof
JP2659980B2 (en) Method for manufacturing semiconductor device
JPH03265140A (en) Semiconductor device and manufacture thereof
JPH03296024A (en) Mim liquid crystal panel and its manufacture
JPH063698A (en) Thin film transistor device
JPS63131569A (en) Semiconductor device
JPS6215818A (en) Connecting structure of electrode and forming method thereof
JPH09283617A (en) Semiconductor device and manufacture thereof
JPS6365643A (en) Manufacture of semiconductor device
JPS6152628A (en) Liquid crystal display device
JPH04102327A (en) Manufacture of semiconductor integrated circuit device
JPS6235537A (en) Semiconductor device and manufacture thereof
JPH01147843A (en) Manufacture of semiconductor device
JPH0212825A (en) Manufacture of semiconductor device
JPH10116996A (en) Composite device manufacture and composite device
JPS63122103A (en) Thin film nonlinear resistance element