JPH0350250U - - Google Patents
Info
- Publication number
- JPH0350250U JPH0350250U JP10889589U JP10889589U JPH0350250U JP H0350250 U JPH0350250 U JP H0350250U JP 10889589 U JP10889589 U JP 10889589U JP 10889589 U JP10889589 U JP 10889589U JP H0350250 U JPH0350250 U JP H0350250U
- Authority
- JP
- Japan
- Prior art keywords
- emulator
- bus line
- circuit
- target board
- controls
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
Description
第１図はこの考案によるエミユレータ装置の一
実施例のブロツク構成図、第２図はこの考案によ
るエミユレータ装置のＣＰＵ取り付け部の説明図
第３図は従来のエミユレータ装置のブロツク構成
図、第４図は従来のエミユレータ装置のＣＰＵ取
り付け部の説明図である。
図中１は供試体となるターゲツトボード、１０
はエミユレータポツド、１４はホストマシン、２
はターゲツトボード１上のＣＰＵ、３はＣＰＵコ
ネクタ、５はプログラムメモリ、４はチツプセレ
クト回路、６はＡＮＤ回路、８はバス線、１１は
バツフア回路、１３はモニタメモリ、１２は制御
回路、１５はターゲツトボード１上の端子である
なお、図中、同一符号は、同一または相当部分を
示す。
FIG. 1 is a block diagram of an embodiment of the emulator device according to this invention, FIG. 2 is an explanatory diagram of the CPU mounting part of the emulator device according to this invention, and FIG. 3 is a block diagram of a conventional emulator device. FIG. 1 is an explanatory diagram of a CPU mounting portion of a conventional emulator device. In the figure, 1 is the target board that is the specimen, 10
is the emulator pot, 14 is the host machine, 2
is the CPU on the target board 1, 3 is the CPU connector, 5 is the program memory, 4 is the chip select circuit, 6 is the AND circuit, 8 is the bus line, 11 is the buffer circuit, 13 is the monitor memory, 12 is the control circuit, 15 are terminals on the target board 1. In the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
れるエミユレータ装置において、ターゲツトボー
ドとなるＣＰＵ回路上のプログラムメモリの制御
をエミユレータ側から行うＡＮＤ回路と、その制
御信号を伝える制御信号線と、ターゲツトボード
上のＣＰＵと直接接触するコネクタと、ＣＰＵの
信号を伝えるバス線と、そのバス線と制御信号線
とでターゲツトボードと接続されるエミユレータ
ポツドと、そのエミユレータポツド内でバス線と
接続されエミユレータポツド内のバス線との接続
を制御するバツフアと、エミユレータポツド内の
バス線に接続されるモニタメモリと、エミユレー
タポツド内のバス線と制御線に接続されモニタメ
モリのデータを管理し、ターゲツトボード上のプ
ログラムメモリとモニタメモリとの切り替えを行
う制御回路と、制御回路と接続されプログラム開
発及びデバツグのマンマシンインターフエースと
なるホストマシンとで構成されたことを特徴とす
るエミユレータ装置。 In an emulator device used for developing/debugging a microprocessor, there is an AND circuit that controls the program memory on the CPU circuit that is the target board from the emulator side, a control signal line that conveys the control signal, and an AND circuit that controls the program memory on the CPU circuit that is the target board. A connector that makes direct contact with the CPU, a bus line that conveys CPU signals, an emulator pod that connects the target board with the bus line and control signal line, and a bus line that connects the emulator pod to the target board. A buffer that is connected and controls the connection with the bus line in the emulator pod, a monitor memory that is connected to the bus line in the emulator pod, and a buffer that controls the connection with the bus line in the emulator pod. It consists of a control circuit that is connected and manages data in the monitor memory and switches between the program memory and monitor memory on the target board, and a host machine that is connected to the control circuit and serves as a man-machine interface for program development and debugging. An emulator device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10889589U JPH0350250U (en) | 1989-09-18 | 1989-09-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10889589U JPH0350250U (en) | 1989-09-18 | 1989-09-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0350250U true JPH0350250U (en) | 1991-05-16 |
Family
ID=31657508
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10889589U Pending JPH0350250U (en) | 1989-09-18 | 1989-09-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0350250U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002267509A (en) * | 2001-03-12 | 2002-09-18 | Keyence Corp | Flowmeter equipped with display part |
| JP2007101825A (en) * | 2005-10-04 | 2007-04-19 | Toshiba Corp | Lcd display device for instrument |
-
1989
- 1989-09-18 JP JP10889589U patent/JPH0350250U/ja active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002267509A (en) * | 2001-03-12 | 2002-09-18 | Keyence Corp | Flowmeter equipped with display part |
| JP2007101825A (en) * | 2005-10-04 | 2007-04-19 | Toshiba Corp | Lcd display device for instrument |
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