JPH0345930A - Two-terminal type nonlinear element - Google Patents
Two-terminal type nonlinear elementInfo
- Publication number
- JPH0345930A JPH0345930A JP1181223A JP18122389A JPH0345930A JP H0345930 A JPH0345930 A JP H0345930A JP 1181223 A JP1181223 A JP 1181223A JP 18122389 A JP18122389 A JP 18122389A JP H0345930 A JPH0345930 A JP H0345930A
- Authority
- JP
- Japan
- Prior art keywords
- insulator
- semi
- nonlinear element
- transparent conductor
- terminal nonlinear
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000012212 insulator Substances 0.000 claims abstract description 38
- 239000004020 conductor Substances 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 11
- 238000002048 anodisation reaction Methods 0.000 claims description 2
- 238000004544 sputter deposition Methods 0.000 abstract description 6
- 229910004205 SiNX Inorganic materials 0.000 abstract description 5
- 230000003647 oxidation Effects 0.000 abstract description 3
- 238000007254 oxidation reaction Methods 0.000 abstract description 3
- 239000004642 Polyimide Substances 0.000 abstract description 2
- 229910020286 SiOxNy Inorganic materials 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 2
- 229910003070 TaOx Inorganic materials 0.000 abstract description 2
- 238000007743 anodising Methods 0.000 abstract description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract description 2
- 229920001721 polyimide Polymers 0.000 abstract description 2
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 2
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 abstract description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 6
- 239000000758 substrate Substances 0.000 description 5
- 238000001259 photo etching Methods 0.000 description 4
- 239000011521 glass Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、アクティブマトリックス方式液晶表示装置に
おいて液晶スイッチング素子に用いられる下層金属−絶
縁体−上層金属構造、あるいは下層金属−絶縁体−透明
導電体構造を有する２端子型非線形素子の構造に関する
。Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a lower metal-insulator-upper metal structure or a lower metal-insulator-transparent conductor structure used in a liquid crystal switching element in an active matrix liquid crystal display device. The present invention relates to the structure of a two-terminal nonlinear element having a body structure.
例えば、Ｔａ−陽極酸化膜（Ｔａ２０ｇ ）−酸化イン
ジウムスズ（ＩＴＯ）のような下層金属−絶縁体−透明
導電体の３層構造を持つ２端子型非線形素子（ｐ下、Ｍ
ＩＭ素子と略す）を液晶表示装置に使用する場合、第４
図を用いて説明するような工程によりこのＭＩＭ素子構
造を製造することができる。For example, a two-terminal nonlinear element (lower p, M
When using an IM element (abbreviated as IM element) in a liquid crystal display device, the fourth
This MIM element structure can be manufactured by the steps described with reference to the drawings.
第４図（ａ）はＭＩＭ素子を示す平面図であり、第４図
（ｂ）は、第４図！ａ）におけるＣ−Ｄ線断面図である
。ガラス基板１上にＴａ２をスパッタリング法により形
威し、フォトエツチングによりパターニングし、Ｔａ２
から紅るＭＩＭ素子の下部電極と配線とを形成する。こ
のＴａ２の平面パターン形状は、第４図（ａ）の実線１
０で示す。次に陽極酸化法によりＴａ２表面に絶縁体３
としてＴａ２０５を形成する。次に透明導電体４として
、ＩＴＯをスパッタリング法により形成し、フォトエツ
チングによりパターニングし、ＩＴＯからなるＭＩＭ素
子の上部電極と液晶駆動用画素電極とを形成する。FIG. 4(a) is a plan view showing the MIM element, and FIG. 4(b) is a plan view showing the MIM element. It is a sectional view taken along the CD line in a). Ta2 is formed on the glass substrate 1 by sputtering and patterned by photoetching.
The lower electrode and wiring of the MIM element are formed. The planar pattern shape of Ta2 is the solid line 1 in FIG. 4(a).
Indicated by 0. Next, an insulator 3 is applied to the Ta2 surface by anodic oxidation.
Ta205 is formed as a. Next, ITO is formed as a transparent conductor 4 by a sputtering method and patterned by photoetching to form an upper electrode of an MIM element and a pixel electrode for driving a liquid crystal made of ITO.
この透明導電体４の平面パターン形状は第４図（ａｌの
破線１１で示す。Ｔａ２と透明導電体４のクロス部がＭ
ＩＭ素子となる。The planar pattern shape of this transparent conductor 4 is shown by the broken line 11 in FIG. 4 (al).
It becomes an IM element.
第５図は、同一基板上に製作したＭＩＭ素子１００〔個
〕の電流−電圧特性を示したグラフであり、電圧を示す
横軸の極性は、下部電極Ｔａの極性に対応する。Ｔａを
負極にした場合の各素子間における電流−電圧特性の矢
印１４で示すノくラツキ（最大値と最小値に囲まれる範
囲）が著しく大きくｋる。これは、絶縁体であるＴ ａ
ｔ Ｏａ と上部電極であるＩＴＯとの界面接合の不
均一が原因である。FIG. 5 is a graph showing the current-voltage characteristics of 100 MIM elements fabricated on the same substrate, and the polarity of the horizontal axis indicating voltage corresponds to the polarity of the lower electrode Ta. When Ta is used as the negative electrode, the fluctuation (the range surrounded by the maximum value and the minimum value) shown by the arrow 14 in the current-voltage characteristics between each element becomes significantly large. This is an insulator, T a
This is caused by non-uniformity in the interfacial bond between t Oa and ITO, which is the upper electrode.
本発明は、この様な課題を解決したもので、表示品質の
高い２端子型非線形素子を用いたアクティブマトリクス
液晶表示装置を提供することを目的とする。The present invention has solved these problems, and an object of the present invention is to provide an active matrix liquid crystal display device using a two-terminal nonlinear element with high display quality.
本発明は２端子型非線形素子において、下層金属上に陽
極酸化により形成する絶縁体と、この絶縁体上に形成す
る半絶縁体膜と、この半絶縁体膜、上に形成する透明導
電体とを有することを特徴とし、２端子型非線形素子間
の電流−電圧特性のノくラツキを減少させるものである
。The present invention provides a two-terminal nonlinear element that includes an insulator formed on a lower metal layer by anodization, a semi-insulator film formed on the insulator, and a transparent conductor formed on the semi-insulator film. The present invention is characterized by having the following characteristics, and reduces fluctuations in current-voltage characteristics between two-terminal nonlinear elements.
以下、本発明の詳細を実施例に基づいて説明する。 Hereinafter, details of the present invention will be explained based on examples.
第２図は、本実施例により製作した２端子型非線形素子
の構造を示す平面図であり、第１図（ａ）〜（ｄ）は第
２図のＡ−Ｂ断面を示し、本発明の２端子型非線形素子
の構造を得るための製造方法の工程断面図である。以下
第１図と第２図とを交互に参照して説明する。FIG. 2 is a plan view showing the structure of a two-terminal nonlinear element manufactured according to this example, and FIGS. 1(a) to (d) show cross sections A-B in FIG. FIG. 3 is a process cross-sectional view of a manufacturing method for obtaining a structure of a two-terminal nonlinear element. The following description will be given with reference to FIG. 1 and FIG. 2 alternately.
本発明の構造は、第１図（ｄ）に示すように、下層金属
６と、この下層金属６を陽極酸化することにより形成さ
れた絶縁体７と、この絶縁体７上の全面に形成された半
絶縁体８と、この半絶縁体８上に形成された透明導電体
９からなる。As shown in FIG. 1(d), the structure of the present invention includes a lower metal layer 6, an insulator 7 formed by anodizing the lower metal layer 6, and an insulator 7 formed over the entire surface of the insulator 7. It consists of a semi-insulator 8 and a transparent conductor 9 formed on the semi-insulator 8.
この絶縁体７上に設ける半絶縁体８としてはプラズマＣ
ＶＤ法によるＳｉＮｘ、 ＳｉＯｘ、 ＳｉＯｘＮｙ、
スパッタリング法によるＴａＯｘ、 Ｓｉ／ＳｉＮｘか
らなる超格子膜、ポリイミドのＬＢ膜を用いることがで
き、半絶縁体の膜厚は５ （ｎ ｍ ） 〜５０ （ｎ
ｍ ）であれば十分な結果が得られた。As a semi-insulator 8 provided on this insulator 7, plasma C
SiNx, SiOx, SiOxNy, by VD method
A superlattice film made of TaOx, Si/SiNx, or polyimide LB film formed by sputtering can be used, and the film thickness of the semi-insulator is 5 (nm) to 50 (nm).
m), sufficient results were obtained.
以下に、本発明の１実施例の製造方法を示す。Below, a manufacturing method of one embodiment of the present invention will be shown.
まず第１図（ａ）に示すようにガラス基板５上に下層金
属６としてＴａをスパッタリング法により厚さ２００
（ｎ ｍ ］形成し、通常のフォトエツチングによりバ
ターニングする。次に、クエン酸０．１〔％〕水溶液中
で３０（Ｖ）の電圧で下層金属６であるＴａを陽極酸化
し、第１図（ｂ）に示すように絶縁体７としてＴ ａ
２０ ｓ を厚さ５０ Ｃｎｍ）形成する。この下層
金属６と絶縁体７との平面パターン形状は第２図の実線
１２で示す。First, as shown in FIG. 1(a), Ta was deposited on a glass substrate 5 as a lower metal layer 6 to a thickness of 200 mm by sputtering.
(n. As shown in Figure (b), T a as the insulator 7
20 s to a thickness of 50 Cnm). The planar pattern shape of the lower metal layer 6 and the insulator 7 is shown by a solid line 12 in FIG.
次に、第１図（Ｃ）に示す様にプラズマＣＶＤ法により
半絶縁体８としてＳｉＮｘを厚さ２０Ｃｎｍ）を全面に
形成する。次に透明導電体９として例えばＩＴＯをスパ
ッタリング法で厚さ２００（ｎｍ）形成し、第１図（ｄ
）に示すように通常のフォトエツチングにより透明導電
体９をバターニングする。Next, as shown in FIG. 1C, SiNx (20 Cnm thick) is formed as a semi-insulator 8 over the entire surface by plasma CVD. Next, as a transparent conductor 9, for example, ITO is formed to a thickness of 200 (nm) by sputtering method, and as shown in FIG.
), the transparent conductor 9 is patterned by ordinary photoetching.
この透明導電体９の平面パターン形状は第２図の破線１
３で示す。The planar pattern shape of this transparent conductor 9 is indicated by the broken line 1 in FIG.
Indicated by 3.
尚、製作した２端子型非線形素子部の面積は１６（μｍ
〕とした。また、半絶縁体８を通常のフォトエツチング
によりバターニングしても同様の結果が得られる。The area of the fabricated two-terminal nonlinear element section is 16 (μm
]. Similar results can also be obtained by patterning the semi-insulator 8 by conventional photoetching.
第３図は同一基板上に製作した本発明の２端子型非線形
素子１００〔個〕の電圧−電流特性を示したものである
。従来構造による第５図と比較し、Ｔａ負極時の矢印１
５で示す２端子型非線形素子間の特性バラツキが減少し
ている。これは絶縁体と上部電極との間に半絶縁体Ｓｉ
Ｎｘを設げたことによって、絶縁体であるＴａ、０．
と上部電極であるＩＴＯとの界面接合の不均一を解消
したためである。FIG. 3 shows the voltage-current characteristics of 100 two-terminal nonlinear elements of the present invention manufactured on the same substrate. In comparison with Fig. 5 for the conventional structure, arrow 1 for Ta negative electrode
Characteristic variations between the two-terminal nonlinear elements shown by 5 are reduced. This is a semi-insulator Si between the insulator and the upper electrode.
By providing Nx, the insulator Ta, 0.
This is because the non-uniformity of the interfacial bond between the upper electrode and ITO is eliminated.
〔発明の効果〕
以上の説明の如く、２端子型非線形素子の構造において
、陽極酸化による絶縁体形成後にさらに半絶縁体を形成
することにより、素子の電気特性の均一化が達成でき、
表示品質の高い２端子型非線形素子を用いたアクティブ
マトリクス液晶表示装置が得られる。またその効果は、
下層金属−絶縁体一半絶縁体一透明導電体構造以外の下
層金属−１絶縁体−半絶縁体−上層金属構造の２端子型
非線形素子においても同様に得られる。[Effects of the Invention] As explained above, in the structure of a two-terminal nonlinear element, by further forming a semi-insulator after forming an insulator by anodic oxidation, it is possible to achieve uniform electrical characteristics of the element.
An active matrix liquid crystal display device using a two-terminal nonlinear element with high display quality can be obtained. Also, the effect is
The same effect can be obtained in a two-terminal nonlinear element having a lower metal-insulator-semi-insulator-upper metal structure other than the lower metal-insulator-semi-insulator-transparent conductor structure.
第１図及び第２図はいずれも本発明における２端子型非
線形素子構造の製造方法を説明する図面で、第１図（ａ
ｌ〜（ｄｌは第２図のＡ−Ｂ断面を示す本発明の２端子
型非線形素子構造を得るための製造方法を工程順に示す
断面図、第２図は本発明により製作した２端子型非線形
素子の構造を示す平面図、第３図は本発明による２端子
型非線形素子の電流−電圧特性を示すグラフ、第４図（
ａ）、（ｂ）は従来例のＴ ａ −Ｔ ａ ２０ ｓ
−Ｉ Ｔ Ｏ構造の２端子型非線形素子の製造方法を
説明する図面で、第４図（ａ）はＭＩＭ素子を示す平面
図、第４図（ｂ）は第４図（ａｌのＣ−Ｄ断面を示す断
面図、第５図は従来例のＴ ａ−Ｔ ａ２０．−Ｉ Ｔ
Ｏ構造のＭＩＭ素子の電流−電圧特性を示すグラフであ
る。
５・・・・・・ガラス、基板、 ６・・・・・・下層
金属、７・・・・・・絶縁体、 ８・・・・・・半
絶縁体、９・・・・・・透明導電体。
第１図
第２図
第３図
２０
１５
−１（Ｊ
５
５
電圧（Ｖ）
Ｕ
１つ
Ｕ
第４図
（ｂ）Both FIG. 1 and FIG.
l~(dl is a cross-sectional view showing the manufacturing method for obtaining the two-terminal nonlinear element structure of the present invention in order of steps, showing the cross section A-B in Fig. 2. FIG. 3 is a plan view showing the structure of the device, and FIG. 4 is a graph showing the current-voltage characteristics of the two-terminal nonlinear device according to the present invention.
a) and (b) are conventional examples of T a - T a 20 s
- FIG. 4(a) is a plan view showing the MIM element, and FIG. 4(b) is the C-D of FIG. 4(al). A sectional view showing a cross section, FIG. 5 is a conventional example of T a-T a20.-I T
3 is a graph showing current-voltage characteristics of an O-structure MIM element. 5...Glass, substrate, 6...Lower metal, 7...Insulator, 8...Semi-insulator, 9...Transparent conductor. Figure 1 Figure 2 Figure 3 20 15 -1 (J 5 5 Voltage (V) U 1 U Figure 4 (b)
Claims (1)
体上に形成する半絶縁体膜と、該半絶縁体膜上に形成す
る透明導電体とを有することを特徴とする２端子型非線
形素子。A two-terminal nonlinear device comprising an insulator formed by anodization on a lower metal layer, a semi-insulator film formed on the insulator, and a transparent conductor formed on the semi-insulator film. element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1181223A JPH0345930A (en) | 1989-07-13 | 1989-07-13 | Two-terminal type nonlinear element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1181223A JPH0345930A (en) | 1989-07-13 | 1989-07-13 | Two-terminal type nonlinear element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0345930A true JPH0345930A (en) | 1991-02-27 |
Family
ID=16096967
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1181223A Pending JPH0345930A (en) | 1989-07-13 | 1989-07-13 | Two-terminal type nonlinear element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0345930A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010036618A1 (en) * | 2008-09-29 | 2010-04-01 | Sandisk 3D Llc | Miim diodes |
| WO2010036616A1 (en) * | 2008-09-29 | 2010-04-01 | Sandisk 3D Llc | Miim diodes having stacked structure |
| US7897453B2 (en) | 2008-12-16 | 2011-03-01 | Sandisk 3D Llc | Dual insulating layer diode with asymmetric interface state and method of fabrication |
| US7935594B2 (en) | 2008-09-29 | 2011-05-03 | Sandisk 3D Llc | Damascene process for carbon memory element with MIIM diode |
-
1989
- 1989-07-13 JP JP1181223A patent/JPH0345930A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010036618A1 (en) * | 2008-09-29 | 2010-04-01 | Sandisk 3D Llc | Miim diodes |
| WO2010036616A1 (en) * | 2008-09-29 | 2010-04-01 | Sandisk 3D Llc | Miim diodes having stacked structure |
| US7935594B2 (en) | 2008-09-29 | 2011-05-03 | Sandisk 3D Llc | Damascene process for carbon memory element with MIIM diode |
| US7969011B2 (en) | 2008-09-29 | 2011-06-28 | Sandisk 3D Llc | MIIM diodes having stacked structure |
| US7897453B2 (en) | 2008-12-16 | 2011-03-01 | Sandisk 3D Llc | Dual insulating layer diode with asymmetric interface state and method of fabrication |
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