JPH0342860A - Flexible printed wiring board - Google Patents
Flexible printed wiring boardInfo
- Publication number
- JPH0342860A JPH0342860A JP1177810A JP17781089A JPH0342860A JP H0342860 A JPH0342860 A JP H0342860A JP 1177810 A JP1177810 A JP 1177810A JP 17781089 A JP17781089 A JP 17781089A JP H0342860 A JPH0342860 A JP H0342860A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- insulating material
- thermosetting resin
- material layer
- circuit conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 43
- 230000003014 reinforcing effect Effects 0.000 claims abstract description 37
- 229920005989 resin Polymers 0.000 claims abstract description 31
- 239000011347 resin Substances 0.000 claims abstract description 31
- 239000004020 conductor Substances 0.000 claims abstract description 26
- 229920001187 thermosetting polymer Polymers 0.000 claims abstract description 16
- 239000011810 insulating material Substances 0.000 claims description 29
- 230000035515 penetration Effects 0.000 claims description 4
- 239000010410 layer Substances 0.000 abstract description 65
- 229920001721 polyimide Polymers 0.000 abstract description 7
- 239000012787 coverlay film Substances 0.000 abstract description 5
- 239000000853 adhesive Substances 0.000 abstract description 4
- 230000001070 adhesive effect Effects 0.000 abstract description 4
- 239000012790 adhesive layer Substances 0.000 abstract description 4
- 238000010438 heat treatment Methods 0.000 abstract description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 3
- 239000011889 copper foil Substances 0.000 abstract description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract description 3
- 238000005452 bending Methods 0.000 abstract description 2
- 239000010408 film Substances 0.000 abstract description 2
- 229910052737 gold Inorganic materials 0.000 abstract description 2
- 239000010931 gold Substances 0.000 abstract description 2
- 238000007493 shaping process Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 11
- 238000007789 sealing Methods 0.000 description 10
- 239000000463 material Substances 0.000 description 4
- 230000002787 reinforcement Effects 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 3
- 238000001723 curing Methods 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000001771 impaired effect Effects 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 229920002457 flexible plastic Polymers 0.000 description 1
- 238000013007 heat curing Methods 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000002985 plastic film Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000012815 thermoplastic material Substances 0.000 description 1
- 239000002966 varnish Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0393—Flexible materials
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【発明の詳細な説明】
「産業上の利用分野」
本発明はフレキシブルプリント配線板（以下ＦＰＣとい
う）に関するものである。DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a flexible printed wiring board (hereinafter referred to as FPC).
「従来の技術、１
従来、プリント配線板へ半導体を実装する手段として、
エポキシ樹脂やセラミックなどで半導体ペアチップ素子
を気密封止したパッケージ品が用いられており、これら
のパッケージ形態は、基板押入タイプのＤＩＰ （デュ
アルインサートパッケージ）から、表面実装用のｓｏｐ
（スモールアウトラインパッケージ）やＦＰ（フラッ
トパッケージ）などのような、より小型で省スペース化
されたものへ移りつつある。さらにまた、省スペース化
、あるいは、高集積化の要求の高い電子機器などにおい
ては、パッケージに収容されていた半導体ペアチップ素
子をプリント配線板上へ直接実装するようにしたいわゆ
るチップオンボード（以下ＣＯＢという）実装が行われ
ている。"Prior art, 1. Conventionally, as a means of mounting semiconductors on printed wiring boards,
Package products in which semiconductor pair chip elements are hermetically sealed with epoxy resin, ceramic, etc. are used, and these package forms range from board-insertion type DIP (dual insert package) to surface mount type SOP.
There is a shift toward smaller and space-saving products such as (small outline package) and FP (flat package). Furthermore, in electronic devices that require space saving or high integration, so-called chip-on-board (hereinafter referred to as COB) semiconductor pair chip elements housed in packages are mounted directly onto printed wiring boards. ) is being implemented.
上記ＣＯＢ実装には、半導体ペアチップ素子を配線基板
上に接着剤などでグイボンドした後、配線板上の電極回
路と半導体ペアチップ素子のポンディングパッドとを金
線などによりワイヤボンディングするワイヤボンディン
グ法（以下ＷＢ法という）と、半導体ペアチップ素子の
ポンディングパッドにはんだなどの接続用バンプを設け
、配線板電極回路と直接接続するフリップチップ法（以
下ＦＣ法という）とがある。The above-mentioned COB mounting uses the wire bonding method (hereinafter referred to as "wire bonding") in which the semiconductor pair chip element is bonded onto the wiring board with an adhesive or the like, and then the electrode circuit on the wiring board and the bonding pad of the semiconductor pair chip element are wire-bonded with gold wire or the like. WB method) and flip-chip method (hereinafter referred to as FC method) in which connection bumps such as solder are provided on the bonding pads of semiconductor pair chip elements and are directly connected to wiring board electrode circuits.
すなわち上記ＷＢ法によって製造されたものは、第６図
に示すように、絶縁性素材層（ベースフィルム）ｌに接
着層２を介して積層された銅箔をエツチングすることに
より回路導体３を形成し、これに、所定箇所に窓を供え
た絶縁性素材層（カバーレイ）１を積層してなるＦＰＣ
に半導体ペアチップ素子４を接着し、この半導体ペアチ
ップ素子４の上部のポンディングパッド５と回路導体３
の所定箇所との間をボンディングワイヤ６によって接続
し、さらに、封止樹脂７で被覆することによって（４ｉ
ｆｆするようにした構造となっている。That is, in the case manufactured by the above-mentioned WB method, as shown in FIG. 6, the circuit conductor 3 is formed by etching the copper foil laminated on the insulating material layer (base film) l via the adhesive layer 2. Then, an FPC is formed by laminating an insulating material layer (coverlay) 1 with windows at predetermined locations on this.
A semiconductor pair chip element 4 is bonded to the bonding pad 5 and a circuit conductor 3 on the upper part of the semiconductor pair chip element 4.
By connecting with a predetermined location of the
The structure is such that ff.
またＦＣ法によって製造されたものは、第７図に示すよ
うに、半導体ペアチップ素子５のポンディングパッド５
を回路導体３の表面にはんだ８を介して固着した構造と
なっている。In addition, as shown in FIG.
is fixed to the surface of the circuit conductor 3 via solder 8.
「発明が解決しようとする課題」
ところで、上記絶縁性素材層１がポリイミドなどの柔軟
なプラスチックフィルムにより形成されたＦＰＣにあっ
ては、外力、あるいは、経時的に発生する歪みに起因し
て絶縁性素材層ｌに聞げ変形が生じることが避けられず
、この変形に起因して、半導体ペアチップ５と回路導体
３との問、封止樹脂７と基板表面との間が剥離すると、
封止性が失われて半導体ペアチップ５の耐湿性をそこな
い、著しい場合には、機械的に破損してしまうこととな
る。また、絶縁性素材層１の変形によってボンディング
ワイヤ６の断線、はんｔご付は箇所の剥離などが生じる
こともあり得る。さらに、封止樹脂７として一般に用い
られているエポキシ樹脂は、封止性を発揮するために必
要な耐湿性、耐熱性、熱膨張計数（絶縁性素材層に近い
こと）などの条件を満たすものの、絶縁性素材層ｌとし
て一般に用いられているポリイミドとの接着性が比較的
わるく、上記剥離が起こり易い傾向がある。"Problems to be Solved by the Invention" By the way, in FPCs in which the insulating material layer 1 is formed of a flexible plastic film such as polyimide, insulation may deteriorate due to external force or distortion that occurs over time. Unavoidable deformation occurs in the flexible material layer 1, and due to this deformation, separation occurs between the semiconductor pair chip 5 and the circuit conductor 3, and between the sealing resin 7 and the substrate surface.
The sealing performance is lost and the moisture resistance of the semiconductor pair chip 5 is impaired, and in severe cases, mechanical damage may occur. Further, deformation of the insulating material layer 1 may cause disconnection of the bonding wire 6 and peeling of the solder at a location. Furthermore, the epoxy resin that is generally used as the sealing resin 7 satisfies the requirements such as moisture resistance, heat resistance, and thermal expansion coefficient (close to that of an insulating material layer) to exhibit sealing properties. The adhesion to polyimide, which is generally used as the insulating material layer l, is relatively poor, and the above-mentioned peeling tends to occur easily.
そこで、図中鎖線で示すように、絶縁性素材層１の裏面
に予め補強板９を接着しておくことが考えられるが、こ
の場合、次のような新たな問題が生じる。Therefore, it is conceivable to adhere the reinforcing plate 9 to the back surface of the insulating material layer 1 in advance as shown by the chain line in the figure, but in this case, the following new problem arises.
■ 充分な補強効果を得るには、補強板の厚さを大きく
せざるを得ず、その結果ＦＰＣの本質的な特徴であると
ころの薄さ、および、柔軟性が損なわれる。(2) In order to obtain a sufficient reinforcing effect, the thickness of the reinforcing plate must be increased, and as a result, the essential characteristics of FPC, such as thinness and flexibility, are impaired.
■ 補強板の接着には、絶縁性素材層１を構成するポリ
イミドとの接着性などを考慮してアクリルなどの熱可ｆ
ｆ１ａ樹脂やＮＢＲなどのゴム質のものが一般的に使用
されているが、これらの物質は、ワイヤボンディングが
行なわれる温度条件、すなわち、１２０℃〜２８０℃で
軟化してしまい、ボンイング荷重の減衰や超音波出力の
分散といったボンイング不良の原因となる。■ For adhesion of the reinforcing plate, a thermoplastic material such as acrylic is used, taking into account the adhesion with the polyimide that constitutes the insulating material layer 1.
Rubbery materials such as f1a resin and NBR are commonly used, but these materials soften under the temperature conditions at which wire bonding is performed, i.e., 120°C to 280°C, resulting in attenuation of the bonding load. This may cause bong failures such as dispersion of ultrasonic output.
本発明は上記事情１こ鑑みてなされたもので、ＦＰＣの
本質的な特徴である薄さおよび柔軟性を損なうことなく
これを有効に補強するとともに、半導体素子と回路導体
との電気的な接続の信頼性を高めることを目的とするも
のである。The present invention has been made in view of the above-mentioned circumstances 1, and is capable of effectively reinforcing FPC without impairing its essential characteristics of thinness and flexibility, as well as providing electrical connections between semiconductor elements and circuit conductors. The purpose is to increase the reliability of
「課題を解決するための手段」
上記目的を達成するため、本願の特許請求の範囲第１項
記載の発明は、
フィルム状の絶縁性素材層の表面に所定のパターンで回
路導体を設け、この回路導体に電気的に接続された半導
体を前記絶縁性素材層もしくは回路導体に機械的に固着
してなるフレキシブルプリント配線板において、前記絶
縁性素材層における半導体の固着箇所の周囲に絶縁性素
材層の表面から半導体の高さよりも高く突出する熱硬化
性樹脂製の表側補強層を設けるとともに、前記半導体の
固着箇所の反対側に熱硬化性樹脂製の裏側補強層を設け
た構成としてなるものである。"Means for Solving the Problem" In order to achieve the above object, the invention described in claim 1 of the present application provides a circuit conductor in a predetermined pattern on the surface of a film-like insulating material layer. In a flexible printed wiring board in which a semiconductor electrically connected to a circuit conductor is mechanically fixed to the insulating material layer or the circuit conductor, an insulating material layer is provided around the fixed portion of the semiconductor in the insulating material layer. A front reinforcing layer made of a thermosetting resin is provided that protrudes from the surface of the semiconductor at a height higher than the height of the semiconductor, and a back reinforcing layer made of a thermosetting resin is provided on the opposite side of the fixing location of the semiconductor. be.
また特許請求の範囲第２項記載の発明は、前記特許請求
の範囲第１項記載の発明において、絶縁性素材層におけ
る回路パターンの形成範囲外に、絶縁性素材層を貫通す
る貫通部を設け、該貫通部に、前記表側および裏側の補
強層と一体の熱硬化性樹脂製の連結部を設けた構成とし
てなるものである。Furthermore, the invention as set forth in claim 2 is the invention as set forth in claim 1, in which a penetration portion that penetrates the insulating material layer is provided outside the area in which the circuit pattern is formed in the insulating material layer. , the penetrating portion is provided with a connecting portion made of thermosetting resin that is integral with the reinforcing layers on the front side and the back side.
「作用」
特許請求の範囲第１項記載の発明の構成であると、絶縁
性素材層に積層された熱硬化性樹脂によって、半導体の
搭載範囲の剛性が高められる。また半導体の搭載範囲す
周囲に充分な高さをもって設けられた補強層は、外力が
半導体へ直接的に作用するのを特徴する
特許請求の範囲第２項記載の発明の構成であると、表側
および裏側の補強層を構成すべく塗布、あるいは印刷さ
れた樹脂が、絶縁性素材層を表ワ１に貫通する貫通部を
介して一体化され、さらに硬化することによって連結部
となり、前記表裏の補強層を強固に連結して、これらの
間の各層の助げ変形や、これにともなう剥離が防止され
る。"Function" With the structure of the invention described in claim 1, the rigidity of the semiconductor mounting area is increased by the thermosetting resin laminated on the insulating material layer. In addition, in the structure of the invention set forth in claim 2, in which an external force is directly applied to the semiconductor, the reinforcing layer provided at a sufficient height around the mounting area of the semiconductor is provided on the front side. The resin coated or printed to form the reinforcing layer on the front and back sides is integrated through the penetration part that penetrates the insulating material layer to the front wire 1, and when further hardened, it becomes a connecting part. By firmly connecting the reinforcing layers, deformation of the layers between them and accompanying peeling can be prevented.
「実施例」
以下、図ｉＴ＋ｉを参Ｊ！ｌ！ シて本発明の詳細な説
明する。なお図中従来例と共通の構成には同一符号を付
し、説明を簡略化する。"Example" See Figure iT+i below. l! The present invention will now be described in detail. In the figure, components common to the conventional example are given the same reference numerals to simplify the explanation.
第１図および第２図は本発明の一実施例を示すものであ
って、このＦＰＣは、所定のパターンの回路導体３が設
けられた絶縁性素材層（ベース）ｌを備えるとともに、
半導体ペアチップ素子４の搭載範囲に窓を備えた絶縁性
素材層（カバーレイ）ｌが積層された構造となっている
。また半導体ペアチップ素子４は、絶縁性素材層ｌがな
く、回路導体３が露出した箇所に設けられており、この
半導体ペアチップ素子４の搭載箇所の周囲には熱硬化性
樹脂からなる補強層１０が積層されている。さらに、補
強層１０に囲まれた範囲には、封止樹脂７が充填されて
前記半導体ペアチップ素子４を）夏うようになっている
。FIG. 1 and FIG. 2 show an embodiment of the present invention, and this FPC includes an insulating material layer (base) l on which a circuit conductor 3 of a predetermined pattern is provided,
It has a structure in which an insulating material layer (coverlay) l having a window in the mounting area of the semiconductor pair chip element 4 is laminated. Further, the semiconductor pair chip element 4 is provided at a location where the insulating material layer l is not present and the circuit conductor 3 is exposed, and a reinforcing layer 10 made of thermosetting resin is provided around the mounting location of the semiconductor pair chip element 4. Laminated. Further, the area surrounded by the reinforcing layer 10 is filled with a sealing resin 7 to enclose the semiconductor pair chip element 4.
上記構成のＦＰＣは、例えば下記のような工程により製
造される。The FPC having the above structure is manufactured, for example, by the following steps.
■厚さ２５μｍ程度のポリイミドフィルムからなる絶縁
性素材層ｌと、回路導体３となる厚さ１８μｍ程度の銅
箔とを接着層２を介してラミネートしてなる銅張積層板
を用い、マスキング→回路パターンの露光→現像→エツ
チングによって所定の回路導体を形成する。■Masking using a copper-clad laminate made by laminating an insulating material layer l made of polyimide film with a thickness of about 25 μm and copper foil with a thickness of about 18 μm, which will become the circuit conductor 3, via an adhesive layer 2 → A predetermined circuit conductor is formed by exposing the circuit pattern, developing it, and then etching it.
■厚さ２５μｍ程度のポリイミドフィルムに接着剤を塗
布してＢステージ（熱硬化前の柔軟な状態）まで硬化さ
せてなるカバーレイフィルム１の所定位置に窓を形成し
、上記■工程により、形成されたものの表面に、積層し
、加熱プレスによって接着剤に回路導体間の隙間を埋め
させながら、カバーレイフィルム１を完全に硬化させる
。■A window is formed at a predetermined position of the coverlay film 1, which is made by applying an adhesive to a polyimide film with a thickness of about 25 μm and curing it to the B stage (flexible state before heat curing), and then forming it by the above step (■). The coverlay film 1 is laminated on the surface of the circuit conductor, and the coverlay film 1 is completely cured while the adhesive is used to fill the gaps between the circuit conductors using a hot press.
■以上のようにして作成された基板のＣＯＢ実装部分、
特に、ワイヤボンディング用電極回路の部分に高純度の
金めつき処理を施した後、半導体ペアチップ素子４を実
装する面における実装範囲の周囲（ワイヤボンディング
される範囲の外）、および、他方の面全体に、補強層１
０となる熱硬化性樹脂をスクリーン印刷などによって塗
布し、加熱炉で加熱することにより硬化させる。■COB mounting part of the board created as above,
In particular, after high-purity gold plating is applied to the electrode circuit portion for wire bonding, the area around the mounting area on the surface where the semiconductor pair chip element 4 is mounted (outside the area to be wire bonded) and the other surface. Reinforcement layer 1 throughout
0 thermosetting resin is applied by screen printing or the like, and cured by heating in a heating furnace.
■以上のようにして作成された基板のＣＯＢ実装部のグ
イパッドに、銀ペーストなどを用いて、半導体ペアチッ
プ素子４をグイボンドし、素子４のポンディングパッド
５と回路導体３とをワイヤボンドする。その結果、第２
図に示すようなＦＰＣが得られる。(2) Using silver paste or the like, the semiconductor pair chip element 4 is bonded to the bonding pad of the COB mounting portion of the board created as described above, and the bonding pad 5 of the device 4 and the circuit conductor 3 are bonded by wire. As a result, the second
An FPC as shown in the figure is obtained.
なお、前記補強層１０を構成すべくＦＰＣの表面に塗布
される樹脂は、例えば熱硬化型樹脂ワニスであって、Ｔ
ｇが１００″Ｃとなる程度の耐熱性を持るものが採用さ
れ、その塗布範囲は、ＦＰＣの外周から１ｍｍ程度内側
の領域とされている。The resin applied to the surface of the FPC to form the reinforcing layer 10 is, for example, a thermosetting resin varnish, and T
A material having heat resistance such that g is 100''C is used, and its application range is approximately 1 mm inside from the outer periphery of the FPC.
■さらに、前記補強層１０によって囲まれた範囲の凹部
に封止樹脂７を充填して硬化させる。(2) Furthermore, the sealing resin 7 is filled into the recessed area surrounded by the reinforcing layer 10 and hardened.
以上のように構成されたＦＰＣは、補強層１０によって
半導体ペアチップ素子４の実装部分の周囲、および裏面
が補強されているから、この部分の曲げ変形を最小限に
抑制して、基板の表面にグイボンドされた素子４の剥が
れ、あるいは、ボンディング不良の発生を防止すること
ができる。また補強層１０は、エポキシ樹脂などからな
る封止樹脂７との間で良好接着性を有し、したがって、
封止を確実にすることができる。In the FPC configured as described above, the area around the mounting part of the semiconductor pair chip element 4 and the back surface are reinforced by the reinforcing layer 10, so bending deformation in this part is suppressed to a minimum and the surface of the board is Peeling of the bonded element 4 or occurrence of bonding defects can be prevented. Further, the reinforcing layer 10 has good adhesion with the sealing resin 7 made of epoxy resin or the like, and therefore,
Sealing can be ensured.
さらに、補強層１０は、第２図に示すように半導体ペア
チップ素子４の上面よりさらに上方に達することができ
る程度の厚さで形成されているから、封止樹脂７を上方
から圧縮しようとする荷重が加わった場合にも、これを
実装部分およびその周囲部分に分散させて半導体ペアチ
ップ素子４を保護することができる。Furthermore, since the reinforcing layer 10 is formed to have a thickness that allows it to reach further above the upper surface of the semiconductor pair chip element 4 as shown in FIG. 2, it tends to compress the sealing resin 7 from above. Even if a load is applied, it is possible to protect the semiconductor pair chip element 4 by distributing the load to the mounting portion and its surrounding area.
次いで、第３図および第４図は本発明の他の実施例を示
すものである。この実施例は、ＦＰＣを表裏に貫通する
開口部１１を設け、この開口部ｌｌを介して表側の補強
層１０と裏側の補強層ｌＯとをこれらと一体の樹脂から
なる連結部１２によって互いに連結するようにしたもの
である。Next, FIGS. 3 and 4 show other embodiments of the present invention. In this embodiment, an opening 11 penetrating the FPC from the front and back is provided, and a reinforcing layer 10 on the front side and a reinforcing layer IO on the back side are connected to each other through the opening 11 by a connecting part 12 made of resin integral with them. It was designed to do so.
すなわち、一般のＦＰＣにあっては、表裏の回路導体を
導通させるため、スルーホールと呼ばれる貫通孔を形成
するから、この貫通孔を形成するための打ち抜き加工と
同一の工程において前記開口部１１を形成しておき、前
記■の工程における熱硬化性樹脂の印刷（塗布）ととも
に、この開口部１１内に表側および表側から互いに樹脂
を送り込んで一体化し、これを加熱、硬化させることに
よって、表裏の補強層１０− ｔｏを互いに接続する前
記連結部１２が形成されることになる。That is, in a general FPC, a through hole called a through hole is formed in order to conduct the circuit conductors on the front and back sides, so the opening 11 is formed in the same process as the punching process to form the through hole. In addition to printing (coating) the thermosetting resin in the step (2) above, the resin is fed into the opening 11 from the front side and the front side to integrate it, and by heating and curing it, the front and back sides are formed. The connecting portion 12 is formed to connect the reinforcing layers 10-to to each other.
なお、前記開口部１１は、ＦＰＣの周囲より１ｍｍ程度
内側に形成された補強層１０よりもさらに１ｍｍ程度内
側の領域であって、回路導体３が形成される範囲より外
側の領域に設定されることにより、補強層１０の強度を
保存し、かつ、回路導体３を切断してしまうことのない
ように配慮されている。The opening 11 is set in a region further about 1 mm inside the reinforcing layer 10 formed about 1 mm inside the periphery of the FPC, and outside the range where the circuit conductor 3 is formed. By doing so, consideration is given to preserving the strength of the reinforcing layer 10 and preventing the circuit conductor 3 from being cut.
以上のように構成されたＦＰＣは、補強層１０の存在に
よって、前記一実施例のものと同様の効果を得ているの
はもちろんのこと、表裏の補強層１０が連結部１２によ
って連結されて、両層の間の間隔を連結部１２により一
定に維持して、これらの間の各層の剥離が確実に防止さ
れている。The FPC configured as described above not only obtains the same effect as the one of the above embodiment due to the presence of the reinforcing layer 10, but also has the front and back reinforcing layers 10 connected by the connecting portion 12. The spacing between both layers is maintained constant by the connecting portion 12, and peeling of each layer between these layers is reliably prevented.
なお前記開口部１１の幅寸法は、補強層１０を構成する
熱硬化型樹脂の流動性を考慮してほぼ１゜５ｍｍ程度に
設定されている。すなわち、開口部１０を介して表裏の
樹脂を流通させて両側の補強層１０を確実に連結するに
は、開口部の幅寸法を大きくし、あるいは、溶剤等によ
り樹脂を薄めて流動性を高めることが有効であるが、硬
化時に反り、歪みなどが発生しない程度の濃度を維持し
、かつ、補強層１０の連結を確実にするため、上記１．
５ｍｍ程度の寸法に設定されている。The width of the opening 11 is set to about 1.degree. 5 mm in consideration of the fluidity of the thermosetting resin constituting the reinforcing layer 10. That is, in order to flow the front and back resins through the openings 10 and reliably connect the reinforcing layers 10 on both sides, the width of the openings must be increased, or the resin may be diluted with a solvent or the like to increase fluidity. However, in order to maintain the concentration to such an extent that warpage, distortion, etc. do not occur during curing, and to ensure the connection of the reinforcing layer 10, the above-mentioned 1.
The size is set to about 5 mm.
さらに、前記他の実施例では、ＦＰＣの表裏を貫通する
開口部１１を連続的なスリット状としたが、第５図に示
すように、前記実施例において開口部１０が設けられた
範囲に複数の貫通孔１３を均一に分布させて配置するよ
うにしてもよい。Furthermore, in the other embodiments, the openings 11 passing through the front and back sides of the FPC were formed into continuous slits, but as shown in FIG. The through holes 13 may be arranged in a uniformly distributed manner.
「発明の効果］
以上の説明で明らかなように、本願の特許請求の範囲第
１項記戦の発明では、フレキシブルプリント配線板にお
ける半導体の搭載範囲の周囲、および、その裏側に補強
層が設けられているから、この部分の剛仕を高めて藺げ
変形を抑制して、各層の剥がれ、あついは、半導体の機
械的あるいは電気的な結合部分の剥がれを防止すること
ができるとともに、半導体の周囲で充分な高さを持つ補
強層により、半導体へ作用する圧縮荷重を分散させて半
導体チップの機械的な砿壊、あるいは、電気的な接続不
良の発生を防止することができる。"Effects of the Invention" As is clear from the above explanation, in the invention recited in claim 1 of the present application, a reinforcing layer is provided around the mounting range of the semiconductor in the flexible printed wiring board and on the back side thereof. By increasing the rigidity of this part and suppressing deformation, it is possible to prevent the peeling of each layer and the peeling of the mechanical or electrical bonding parts of the semiconductor. A reinforcing layer having a sufficient height around the periphery can disperse the compressive load acting on the semiconductor, thereby preventing mechanical fracture of the semiconductor chip or occurrence of electrical connection failure.
また特許請求の範囲第２項記載の発明では、第１項記載
の発明に加えて、絶縁性素材層を貫通する連結部を介し
て表裏の補強層が一体化されているから、これらの補強
層の間の絶縁性素材層、回路導体の剥離をさらに確実に
防止することができる。Furthermore, in the invention described in claim 2, in addition to the invention described in claim 1, since the front and back reinforcing layers are integrated via a connecting portion that penetrates the insulating material layer, these reinforcement layers are integrated. Peeling of the insulating material layer and the circuit conductor between the layers can be more reliably prevented.
なお、上記実施例は本発明をＷＢ法に適用した場合を示
したが、ＦＣ法により製造されるプリント配線板にも適
用し得るのはもちろんである。In addition, although the above-mentioned example showed the case where this invention was applied to the WB method, it goes without saying that it can also be applied to a printed wiring board manufactured by the FC method.
第１図および第２図は本発明の一実施例を示すもので、
第１図は外観を示す斜視図、第２図は第１図の■−■線
に沿う断面図、第３図および第４図は本発明の他の実施
例を示すもので、第３図は第２図と同一部分の断面図、
第４図は開口部の配置を示す平面図、第５図はさらに他
の実施例における貫通孔の配置を示す平面図、第６図お
よび第７図は従来方法により製造されたプリント配線板
の断面図であって、第６図はＷＢ法による場合を、第７
図はＦＣ法による場合をそれぞれ示すものである。
１・・・・・・絶縁性素材層、２・・・・・・接着層、
３・・・・・・回路導体、４・・・・・・半導体ペアチ
ップ素子、５・・・・・・ポンディングパッド、６・・
・・・・ボンディングワイヤ、７・・・・・・封止樹脂
、８・・・・・・はんだ、９・・・・・・補強板、１０
・・・・・・補強層、１１・・・・・・開口部、１２・
・・・・・連結部、１３・・・・・・貫通孔。1 and 2 show an embodiment of the present invention,
FIG. 1 is a perspective view showing the external appearance, FIG. 2 is a sectional view taken along the line ■-■ in FIG. 1, and FIGS. 3 and 4 show other embodiments of the present invention. is a sectional view of the same part as Figure 2,
FIG. 4 is a plan view showing the arrangement of openings, FIG. 5 is a plan view showing the arrangement of through holes in another embodiment, and FIGS. 6 and 7 are of a printed wiring board manufactured by the conventional method. FIG. 6 is a cross-sectional view of the case using the WB method, and FIG.
The figures each show the case of the FC method. 1... Insulating material layer, 2... Adhesive layer,
3... Circuit conductor, 4... Semiconductor pair chip element, 5... Bonding pad, 6...
... Bonding wire, 7 ... Sealing resin, 8 ... Solder, 9 ... Reinforcement plate, 10
... Reinforcement layer, 11 ... Opening, 12.
...Connecting portion, 13...Through hole.
Claims (2)
ンで回路導体を設け、この回路導体に電気的に接続され
た半導体を前記絶縁性素材層もしくは回路導体に機械的
に固着してなるフレキシブルプリント配線板において、
前記絶縁性素材層における半導体の固着箇所の周囲に絶
縁性素材層の表面から半導体の高さよりも高く突出する
熱硬化性樹脂製の表側補強層を設けるとともに、前記半
導体の固着箇所の反対側に熱硬化性樹脂製の裏側補強層
を設けたことを特徴とするフレキシブルプリント配線板
。(1) A circuit conductor is provided in a predetermined pattern on the surface of a film-like insulating material layer, and a semiconductor electrically connected to the circuit conductor is mechanically fixed to the insulating material layer or the circuit conductor. In flexible printed wiring boards,
A front reinforcing layer made of thermosetting resin that protrudes from the surface of the insulating material layer to a height higher than the height of the semiconductor is provided around the point where the semiconductor is fixed in the insulating material layer, and on the opposite side of the point where the semiconductor is fixed. A flexible printed wiring board characterized by having a back side reinforcing layer made of thermosetting resin.
囲外に、絶縁性素材層を貫通する貫通部を設け、該貫通
部に、前記表側および裏側の補強層と一体の熱硬化性樹
脂製の連結部を設けたことを特徴とするフレキシブルプ
リント配線板。(2) A penetration part that penetrates the insulating material layer is provided outside the area where the circuit pattern is formed in the insulating material layer, and a thermosetting resin made of thermosetting resin integral with the front and back reinforcing layers is provided in the penetration part. A flexible printed wiring board characterized by having a connecting portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1177810A JPH0342860A (en) | 1989-07-10 | 1989-07-10 | Flexible printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1177810A JPH0342860A (en) | 1989-07-10 | 1989-07-10 | Flexible printed wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0342860A true JPH0342860A (en) | 1991-02-25 |
Family
ID=16037487
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1177810A Pending JPH0342860A (en) | 1989-07-10 | 1989-07-10 | Flexible printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0342860A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09283889A (en) * | 1996-04-09 | 1997-10-31 | Rohm Co Ltd | Reinforcing method of flexible substrate and flexible substrate |
| CN103715164A (en) * | 2012-09-29 | 2014-04-09 | 富葵精密组件(深圳)有限公司 | Flexible circuit board and chip package structure |
| JP2019068016A (en) * | 2017-10-05 | 2019-04-25 | Dic株式会社 | Method of manufacturing flexible printed wiring board with reinforcing portion |
| CN110402016A (en) * | 2019-07-31 | 2019-11-01 | Oppo（重庆）智能科技有限公司 | Flexible circuit board component |
| CN110402017A (en) * | 2019-07-31 | 2019-11-01 | Oppo（重庆）智能科技有限公司 | Flexible circuit board component |
| WO2022209240A1 (en) * | 2021-03-30 | 2022-10-06 | Ｎｉｓｓｈａ株式会社 | Electronic-component-attached resin housing and method for making same |
-
1989
- 1989-07-10 JP JP1177810A patent/JPH0342860A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09283889A (en) * | 1996-04-09 | 1997-10-31 | Rohm Co Ltd | Reinforcing method of flexible substrate and flexible substrate |
| CN103715164A (en) * | 2012-09-29 | 2014-04-09 | 富葵精密组件(深圳)有限公司 | Flexible circuit board and chip package structure |
| JP2019068016A (en) * | 2017-10-05 | 2019-04-25 | Dic株式会社 | Method of manufacturing flexible printed wiring board with reinforcing portion |
| CN110402016A (en) * | 2019-07-31 | 2019-11-01 | Oppo（重庆）智能科技有限公司 | Flexible circuit board component |
| CN110402017A (en) * | 2019-07-31 | 2019-11-01 | Oppo（重庆）智能科技有限公司 | Flexible circuit board component |
| WO2022209240A1 (en) * | 2021-03-30 | 2022-10-06 | Ｎｉｓｓｈａ株式会社 | Electronic-component-attached resin housing and method for making same |
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