JPH0342730B2 - - Google Patents
Info
- Publication number
- JPH0342730B2 JPH0342730B2 JP59029739A JP2973984A JPH0342730B2 JP H0342730 B2 JPH0342730 B2 JP H0342730B2 JP 59029739 A JP59029739 A JP 59029739A JP 2973984 A JP2973984 A JP 2973984A JP H0342730 B2 JPH0342730 B2 JP H0342730B2
- Authority
- JP
- Japan
- Prior art keywords
- sampling
- voltages
- input signal
- time
- predetermined
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000003990 capacitor Substances 0.000 claims description 29
- 238000005070 sampling Methods 0.000 claims description 16
- 238000010586 diagram Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 241000270708 Testudinidae Species 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H19/00—Networks using time-varying elements, e.g. N-path filters
- H03H19/004—Switched capacitor networks
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Filters That Use Time-Delay Elements (AREA)
- Analogue/Digital Conversion (AREA)
Description
【発明の詳細な説明】
（発明の属する技術分野）
本発明は複数の信号を時分割に処理するスイツ
チド・キヤパシタ・フイルタに関する。DETAILED DESCRIPTION OF THE INVENTION (Technical field to which the invention pertains) The present invention relates to a switched capacitor filter that processes a plurality of signals in a time division manner.
（従来技術）
MOS集積回路技術を用いて構成できるフイル
タとしてスイツチド・キヤパシタ・フイルタ（以
下SCFと称す）がある。SCFは演算増幅器、キヤ
パシタおよびスイツチ素子で構成され、その周波
数特性はサンプリング周波数と容量比とで定まる
ため、無調整で、精度の良いフイルタを製造でき
る。このようなSCFの一種に、複数の信号を時分
割処理できる時分割多重スイツチド・キヤパシ
タ・フイルタがある。このSCFは、Digest of
Technical Papers、1980IEEE International
Solid−State Circuts Conferenceの第92頁〜第
93頁に所載のPatrick W.Bosshartの論文“Ａ
Multiplexed Switched Capacitor Filter
Bank”に提案されている。この時分割多重SCF
においては、一つの演算増幅器を複数のフイルタ
間で共用できるので、集積回路化したときのチツ
プ面積および消費電力の減少を達成できる。この
従来の時分割多重SCFについて、Ｎ（２以上の整
数）個の信号を時分割処理する場合を例として説
明する。(Prior Art) A switched capacitor filter (hereinafter referred to as SCF) is a filter that can be constructed using MOS integrated circuit technology. The SCF consists of an operational amplifier, a capacitor, and a switch element, and its frequency characteristics are determined by the sampling frequency and capacitance ratio, so it is possible to manufacture highly accurate filters without adjustment. One type of SCF is a time-division multiplexed switched capacitor filter that can time-divisionally process multiple signals. This SCF is a Digest of
Technical Papers, 1980 IEEE International
Solid-State Circuts Conference, pages 92-9
Patrick W. Bosshart’s paper “A” on page 93
Multiplexed Switched Capacitor Filter
This time division multiplexed SCF
Since one operational amplifier can be shared among a plurality of filters, it is possible to reduce the chip area and power consumption when integrated into a circuit. This conventional time-division multiplexing SCF will be explained by taking as an example a case where N (an integer of 2 or more) signals are time-divisionally processed.
第１図は、従来の時分割多重SCFの基本回路と
なる従来の積分器を示す回路図である。第１図に
おいて、この積分器は、入力端子１と、出力端子
２と、スイツチド・キヤパシタ３と、それぞれ第
２図ｄおよびｅに示すような一定周期のクロツク
φ1およびφ2によつて動作しスイツチド・キヤパ
シタ３に入力信号Vnを充電させるサンプリング
スイツチ４および５と、それぞれ容量値C1〜CN
を持つＮ個の積分キヤパシタ６−１〜６−Ｎと、
演算増幅器７と、それぞれ第２図ｃに示すような
信号P1〜PNで制御される時分割スイツチ８−１
〜８−Ｎおよび９−１〜９−Ｎとから構成され
る。サンプリングスイツチ４および５ならびに時
分割スイツチ８−１〜８−Ｎおよび９−１〜９−
ＮはMOSトランジスタで構成され、ゲート電圧
が高レベルのとき導通（ON）し、低レベルのと
き非導通（OFF）となる。 FIG. 1 is a circuit diagram showing a conventional integrator that is a basic circuit of a conventional time division multiplexed SCF. In FIG. 1, this integrator is operated by an input terminal 1, an output terminal 2, a switched capacitor 3, and constant period clocks φ 1 and φ 2 as shown in FIGS. 2d and e, respectively. Sampling switches 4 and 5 charge input signal Vn to switched capacitor 3, and capacitance values C 1 to C N respectively.
N integral capacitors 6-1 to 6-N having
an operational amplifier 7 and a time division switch 8-1 controlled by signals P 1 to P N as shown in FIG. 2c, respectively;
~8-N and 9-1 ~ 9-N. Sampling switches 4 and 5 and time division switches 8-1 to 8-N and 9-1 to 9-
N is composed of a MOS transistor, which is conductive (ON) when the gate voltage is at a high level and non-conductive (OFF) when the gate voltage is at a low level.
ここで、入力端子１には、第２図ａに示すよう
なＮ種の信号v1〜vNが時分割に入力される。信号
voを入力するときには、時分割スイツチ８−ｎお
よび９−ｎがONする。ここで、ｎは１≦ｎ≦Ｎ
となる整数である。サンプリングスイツチ４およ
び５が交互にON、OFFすることにより、入力信
号voがスイツチドキヤパシタ３に充電され、その
充電電荷が積分キヤパシタ６−ｎに転送される。
出力端子２には、第２図ｂに示すように、時分割
された出力信号V1〜VNが出力されるがこの積分
器の伝達関数（入出力電圧の比）は次のようにな
る。ｎ番目の信号に対して、
■■■ 亀の甲 ［0001］ ■■■
ただし、
Ｚ＝ej2〓f/fc
となり、fcはｎ番目の信号に対するサンプリング
周期を示し、サンプリングスイツチ４および５の
動作周期の１／Ｎである。式(1)はｎ＝１，２…，
Ｎについて成立することから、この積分器は異る
キヤパシタ６−ｎを選択することによりＮ個の入
力信号v1〜vNに対して異る伝達関数を与えること
ができる。すなわち、一つの積分器でＮ個の信号
を異る伝達関数で時分割処理できる。 Here, N types of signals v 1 to v N as shown in FIG. 2a are input to the input terminal 1 in a time-division manner. signal
When inputting v o , time division switches 8-n and 9-n are turned on. Here, n is 1≦n≦N
is an integer. By alternately turning ON and OFF the sampling switches 4 and 5, the input signal vo is charged into the switched capacitor 3, and the charged charge is transferred to the integrating capacitor 6-n.
As shown in Figure 2b, time-divided output signals V 1 to V N are output to output terminal 2, and the transfer function (ratio of input and output voltages) of this integrator is as follows. . For the n-th signal, ■■■ Tortoise Shell [0001] ■■■ However, Z=e j2 〓 f/fc , where f c indicates the sampling period for the n-th signal, and the operation of sampling switches 4 and 5 It is 1/N of the period. Equation (1) is n=1, 2...,
Since this holds true for N, this integrator can provide different transfer functions to N input signals v 1 to v N by selecting different capacitors 6-n. That is, one integrator can time-divisionally process N signals using different transfer functions.
SCFは複数個の積分器を組み合わせて構成され
るので、第１図の積分器をもとに、Ｎ個の信号を
入出力する時分割SCFが実現できる。 Since the SCF is constructed by combining a plurality of integrators, a time-division SCF that inputs and outputs N signals can be realized based on the integrator shown in FIG.
しかしながら、このような従来の時分割多重
SCFには次のような欠点がある。すなわち、Ｎ個
の入力信号を時分割多重して処理するＮチヤンネ
ルの時分割多重SCFにおいて、出力されるＮ個の
出力信号が各チヤンネルで異る直流オフセツト電
圧を有することである。この直流オフセツトは、
フイルタ出力を整流する場合やピーク値を検出す
る場合に誤差の原因となる。もし、この直流オフ
セツト電圧を除去しようとするならば、オフセツ
ト調整回路をＮ個の各チヤンネル対して設ける必
要があり、回路が複雑になる。 However, such traditional time division multiplexing
SCF has the following drawbacks. That is, in an N-channel time-division multiplexing SCF that processes N input signals by time-division multiplexing, the N output signals have different DC offset voltages for each channel. This DC offset is
This causes errors when rectifying the filter output or detecting the peak value. If this DC offset voltage is to be removed, it is necessary to provide an offset adjustment circuit for each of the N channels, making the circuit complex.
各チヤンネルにおいて直流オフセツト電圧に差
が出る理由を第３図を参照して説明する。第３図
は第１図の積分器のサンプリングパルスφ2が立
ち下がつたときの状態を示す等価回路である。た
だし、時分割スイツチ８−ｎおよび９−ｎがON
し、積分キヤパシタ６−ｎが接続されているとす
る。通常、MOSトランジスタはゲートとドレイ
ンおよびソース間に寄生容量を有するため、ゲー
ト信号の変化時にソースおよびドレインに寄生容
量を介して電荷がもれる現象が生じる。そのた
め、第３図において、サンプリングパルスφ2が
立ち下がり、サンプリングスイツチ５を形成する
MOSトランジスタがOFF状態に移るとき、寄生
容量Cgを介して積分キヤパシタ６−ｎに電荷の
移動が起こる。この結果、積分キヤパシタ６−ｎ
に保持されている電荷が変わるため出力電圧が変
化し、オフセツト誤差を生ずる。このときの電荷
の移動量はサンプリング容量Csと積分容量Cnと
の関数であることが知られており、それを△Ｑ
（Cs、Cn）で表わせばオフセツト電圧△Vnは
△Vn＝△Ｑ（Cs、Cn）／Cn ……(2)
と書ける。(2)式はｎ＝１，２…，Ｎについて成り
立ち、積分容量Cnの値は各チヤンネルで異るた
め△Vnの値も各チヤンネルで異る。すなわち、
第１図の積分器は各チヤンネルが異るオフセツト
電圧を持つ。 The reason why there is a difference in DC offset voltage in each channel will be explained with reference to FIG. FIG. 3 is an equivalent circuit showing the state when the sampling pulse φ 2 of the integrator shown in FIG. 1 falls. However, time division switches 8-n and 9-n are ON.
Assume that an integral capacitor 6-n is connected. Generally, a MOS transistor has parasitic capacitance between the gate, drain, and source, so that when a gate signal changes, charge leaks to the source and drain via the parasitic capacitance. Therefore, in FIG. 3, the sampling pulse φ 2 falls and forms the sampling switch 5.
When the MOS transistor is turned off, charge is transferred to the integrating capacitor 6-n via the parasitic capacitance Cg. As a result, the integral capacitor 6-n
The output voltage changes because the charge held in the output voltage changes, causing an offset error. It is known that the amount of charge movement at this time is a function of the sampling capacitance Cs and the integral capacitance Cn, and it is expressed as △Q
If expressed as (Cs, Cn), the offset voltage △Vn can be written as △Vn = △Q (Cs, Cn)/Cn... (2). Equation (2) holds true for n=1, 2, . . . , N, and since the value of the integral capacitance Cn differs for each channel, the value of ΔVn also differs for each channel. That is,
The integrator of FIG. 1 has each channel having a different offset voltage.
（発明の目的）
本発明の目的は上述の欠点を除去しオフセツト
電圧の調整が容易な時分割多重SCFを提供するこ
とにある。(Object of the Invention) An object of the present invention is to provide a time division multiplexed SCF that eliminates the above-mentioned drawbacks and allows easy adjustment of offset voltage.
（発明の構成）
本発明のスイツチドキヤパシタフイルタは、Ｎ
個の信号が時分割多重された多重信号が入力され
抵抗分割によりＮ個の異なる電圧を出力する抵抗
分割手段と、該分割手段からのＮ個の出力電圧を
それぞれ入力信号に同期して時分割に選択する第
１の時分割切替手段と、該切替手段からの出力信
号を一定周期でサンプリングするサンプリング手
段と、該サンプリング手段からの出力信号を充電
するスイツチド・キヤパシタと、容量値の等しい
Ｎ個の積分キヤパシタと、１つの演算増幅器と、
該演算増幅器の出力端子と一方の入力端子との間
に前記Ｎ個の積分キヤパシタをそれぞれ入力信号
に同期して時分割に選択接続する第２の時分割切
替手段とを備えた積分器を少なくとも含んでい
る。(Structure of the Invention) The switched capacitor filter of the present invention has N
resistor dividing means that receives a multiplexed signal obtained by time-division multiplexing multiplexed signals and outputs N different voltages by resistor division; and time-dividing the N output voltages from the dividing means in synchronization with the input signals. a first time-division switching means that selects the switching means, a sampling means that samples the output signal from the switching means at a constant cycle, a switched capacitor that charges the output signal from the sampling means, and N pieces of equal capacitance. an integrating capacitor, an operational amplifier,
At least an integrator comprising a second time division switching means for selectively connecting the N integration capacitors in a time division manner in synchronization with the input signal between the output terminal and one input terminal of the operational amplifier. Contains.
（実施例）
次に本発明について図面を参照して詳細に説明
する。(Example) Next, the present invention will be described in detail with reference to the drawings.
第４図を参照すると、本発明のSCFの基本回路
の一実施例は、第１図の従来回路に、それぞれ制
御信号P1〜PNにより制御されるＮ個の時分割ス
イツチ１０−１〜１０−Ｎと、抵抗分割回路１１
とを付加し、積分キヤパシタ６−１〜６−Ｎをそ
れぞれ容量値Ciを有する積分キヤパシタ１２−１
〜１２−Ｎで置き換えた構成を有する。スイツチ
１０−１〜１０−Ｎにはそれぞれ抵抗分割回路１
１により端子１からの入力電圧がＮ種類の分割比
で分割された電圧が出力される。 Referring to FIG. 4, an embodiment of the basic circuit of the SCF of the present invention is added to the conventional circuit of FIG . 10-N and resistor divider circuit 11
and integral capacitors 6-1 to 6-N are integral capacitors 12-1 each having a capacitance value Ci.
~12-N. Each of the switches 10-1 to 10-N has a resistor divider circuit 1.
1 outputs voltages obtained by dividing the input voltage from terminal 1 at N different division ratios.
ｎ番目の入力信号voに対して、時分割スイツチ
１０−ｎがONとなつたときの抵抗の分割比が
Ci／Cnとなるようにすると伝達関数は、
■■■ 亀の甲 ［0002］ ■■■
となり、式(1)と同じ関数となる。 For the n-th input signal v o , the resistance division ratio when the time division switch 10-n is turned on is
When Ci/Cn is set, the transfer function becomes ■■■ Turtle Shell [0002] ■■■, which is the same function as Equation (1).
したがつて、本回路は抵抗分割回路１１の分割
比を適当に選べば、第１図の回路と同じ動作をす
る。このときの出力電圧のオフセツト電圧につい
て考えると、式(2)と同様に導びかれ、
△Vn＝△Ｑ（Cs、Ci）／Ci ……(4)
となり、本回路の各チヤンネルのオフセツト電圧
はｎに依存しなくなる。すなわち、各チヤンネル
の出力信号に含まれるオフセツト電圧を等しくで
きる。 Therefore, if the division ratio of the resistance divider circuit 11 is appropriately selected, this circuit operates in the same way as the circuit shown in FIG. Considering the offset voltage of the output voltage at this time, it is derived in the same way as equation (2), and becomes △Vn = △Q (Cs, Ci) / Ci ... (4), and the offset voltage of each channel of this circuit is becomes independent of n. That is, the offset voltages included in the output signals of each channel can be made equal.
第５図は第４図の基本回路を２つ縦続接続して
２次のSCFを構成した例を示す回路図である。 FIG. 5 is a circuit diagram showing an example in which two of the basic circuits shown in FIG. 4 are connected in cascade to form a secondary SCF.
（発明の効果）
以上、本発明には、全チヤネルの直流オフセツ
ト電圧の除去を一括して行えるのでオフセツト電
圧調整回路が簡単になるという効果がある。(Effects of the Invention) As described above, the present invention has the effect that the offset voltage adjustment circuit can be simplified because the DC offset voltages of all channels can be removed at once.
第１図は従来の時分割多重スイツチドキヤパシ
タフイルタを構成する積分器を示す回路図、第２
図は第１図の回路のタイミングチヤートを示す
図、第３図は第１図の等価回路、第４図は本発明
の一実施例を示す回路図および第５図は本発明に
よる２次の時分割多重スイツチド・キヤパシタ・
フイルタを示す回路図である。
図において、８−１〜８−Ｎ，９−１〜９−
Ｎ，１０−１〜１０−Ｎ……時分割スイツチ、１
１……抵抗分割回路、７……演算増幅器、６−１
〜６−Ｎ，１２−１〜１２−Ｎ……積分キヤパシ
タ、３……スイツチドキヤパシタ、４，５……サ
ンプリングスイツチ、１……入力端子、２……出
力端子。
Figure 1 is a circuit diagram showing an integrator that constitutes a conventional time division multiplexed switched capacitor filter;
3 shows an equivalent circuit of FIG. 1, FIG. 4 shows a circuit diagram of an embodiment of the present invention, and FIG. 5 shows a circuit diagram of a secondary circuit according to the present invention. Time division multiplexed switched capacitor
FIG. 3 is a circuit diagram showing a filter. In the figure, 8-1 to 8-N, 9-1 to 9-
N, 10-1 to 10-N...Time division switch, 1
1... Resistance divider circuit, 7... Operational amplifier, 6-1
~6-N, 12-1~12-N... Integral capacitor, 3... Switched capacitor, 4, 5... Sampling switch, 1... Input terminal, 2... Output terminal.
Claims (1)
定められた多重化タイミングで時分割多重された
入力信号を受け、前記Ｎチヤンネルの各々に対し
て設けられた予め定めた異なる周波数特性を有す
るＮ個のフイルタを前記入力信号のチヤンネルご
とに切り換えて用いる時分割多重構成のスイツチ
ド・キヤパシタ・フイルタにおいて、 前記入力信号を受けて、前記Ｎチヤンネルの多
重化タイミングに同期して、対応するＮ個の電圧
を発生する電圧発生手段と、 この電圧発生手段の出力電圧を前記多重化タイ
ミングでサンプリングするサンプリング手段と、 前記サンプリングの結果を反転入力に受け、非
反転入力を接地された演算増幅器と、 この演算増幅器の出力端子と前記反転入力間に
並列接続された、Ｎ個のキヤパシタと、 前記電圧発生手段と同期して前記Ｎ個のキヤパ
シタのうち１つを選択する選択手段とから構成さ
れ、 前記電圧発生手段として、前記入力信号を受け
てＮ個の異なる電圧に分圧して出力する抵抗分割
手段を用いるとともに、前記Ｎ個のキヤパシタを
等容量とすることにより、前記予め定めた異なる
周波数特性を有するＮ個のフイルタが有するオフ
セツト誤差を均一化したことを特徴とするスイツ
チド・キヤパシタ・フイルタ。[Claims] An input signal in which signals of 1 N (an integer of 2 or more) channels are time-division multiplexed at a predetermined multiplexing timing is received, and a predetermined In a switched capacitor filter having a time division multiplexing configuration in which N filters having different frequency characteristics are switched for each channel of the input signal, receiving the input signal and synchronizing with the multiplexing timing of the N channels. , voltage generating means for generating N voltages corresponding to N voltages, sampling means for sampling the output voltage of the voltage generating means at the multiplexing timing, receiving the result of the sampling at an inverting input, and having a non-inverting input grounded. an operational amplifier; N capacitors connected in parallel between the output terminal of the operational amplifier and the inverting input; and selection means for selecting one of the N capacitors in synchronization with the voltage generation means. As the voltage generating means, a resistor dividing means is used which receives the input signal, divides it into N different voltages, and outputs the divided voltages, and the N capacitors are made to have equal capacitance, so that the predetermined 1. A switched capacitor filter characterized in that offset errors of N filters having different predetermined frequency characteristics are equalized.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59029739A JPS60173916A (en) | 1984-02-20 | 1984-02-20 | Switched capacitor filter |
| US06/703,576 US4623854A (en) | 1984-02-20 | 1985-02-20 | Switched capacitor filter |
| CA000474723A CA1234415A (en) | 1984-02-20 | 1985-02-20 | Switched capacitor filter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59029739A JPS60173916A (en) | 1984-02-20 | 1984-02-20 | Switched capacitor filter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60173916A JPS60173916A (en) | 1985-09-07 |
| JPH0342730B2 true JPH0342730B2 (en) | 1991-06-28 |
Family
ID=12284471
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59029739A Granted JPS60173916A (en) | 1984-02-20 | 1984-02-20 | Switched capacitor filter |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US4623854A (en) |
| JP (1) | JPS60173916A (en) |
| CA (1) | CA1234415A (en) |
Families Citing this family (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH063864B2 (en) * | 1985-09-30 | 1994-01-12 | 株式会社東芝 | Switch switch circuit |
| US4849662A (en) * | 1986-04-14 | 1989-07-18 | Crystal Semiconductor Corporation | Switched-capacitor filter having digitally-programmable capacitive element |
| JP2685050B2 (en) * | 1986-06-11 | 1997-12-03 | 富士通株式会社 | Comparator circuit |
| US4855627A (en) * | 1987-01-14 | 1989-08-08 | Kabushiki Kaisha Toshiba | Filter circuit |
| FR2619975B1 (en) * | 1987-08-28 | 1989-11-17 | France Etat | BIQUADRATIC CELL WITH SWITCHED CAPACITIES WITHOUT CONTINUOUS FEEDBACK LOOP AND WITH LOW SENSITIVITY IN RELATION TO THE GAIN OF THE OPERATIONAL AMPLIFIERS AND TO THE RATIO OF THE CAPACITIES |
| JP2746955B2 (en) * | 1988-11-17 | 1998-05-06 | 日本電気株式会社 | Offset correction circuit |
| IT1237596B (en) * | 1989-10-03 | 1993-06-08 | Marelli Autronica | INTEGRABLE INTERFACE CIRCUIT IN CMOS TECHNOLOGY FOR THE TREATMENT OF THE SIGNAL PROVIDED BY A CAPACITIVE SENSOR, IN PARTICULAR A PIEZOELECTRIC ACCELEROMETRIC SENSOR |
| JPH04367113A (en) * | 1991-06-14 | 1992-12-18 | Matsushita Electric Ind Co Ltd | Roll off filtering device |
| GB2260833A (en) * | 1991-10-22 | 1993-04-28 | Burr Brown Corp | Reference voltage circuit allowing fast power-up |
| US5274583A (en) * | 1992-01-02 | 1993-12-28 | National Semiconductor Corporation | Charge-integrating preamplifier for ferroelectric memory |
| US5434446A (en) * | 1993-07-07 | 1995-07-18 | Analog Devices, Inc. | Parasitic capacitance cancellation circuit |
| JP3799618B2 (en) * | 1994-10-21 | 2006-07-19 | 株式会社デンソー | Signal processing circuit |
| US5565812A (en) * | 1995-03-23 | 1996-10-15 | Texas Instruments Incorporated | Increased sensitivity signal shaper circuit to recover a data stream coming from a digitally modulated channel |
| US5617473A (en) * | 1995-06-23 | 1997-04-01 | Harris Corporation | Sign bit integrator and method |
| DE10031190A1 (en) * | 2000-06-27 | 2002-01-17 | Infineon Technologies Ag | Compensation circuit for an operational amplifier includes regulator system with selective compensation elements |
| US20050151576A1 (en) * | 2003-09-23 | 2005-07-14 | Chao-Cheng Lee | Adjustable impedance circuit |
| TWI294610B (en) * | 2004-09-03 | 2008-03-11 | Au Optronics Corp | A reference voltage circuit with a compensating circuit and a method of the same |
| JP2007043433A (en) * | 2005-08-03 | 2007-02-15 | Renesas Technology Corp | Semiconductor integrated circuit device |
| JP2007116493A (en) * | 2005-10-21 | 2007-05-10 | Oki Electric Ind Co Ltd | Offset canceller |
| US7830682B2 (en) * | 2007-12-19 | 2010-11-09 | Honeywell International Inc. | DC component elimination at output voltage of PWM inverters |
| US8111097B1 (en) * | 2009-05-10 | 2012-02-07 | Cypress Semiconductor Corporation | Device with reconfigurable continuous and discrete time functionality |
| US10024887B2 (en) | 2016-08-24 | 2018-07-17 | Texas Instruments Incorporated | Methods and circuitry for analyzing voltages |
| US10263615B2 (en) | 2016-08-24 | 2019-04-16 | Texas Instruments Incorporated | Circuit and method for driving a device through drive cycles |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58205322A (en) * | 1982-05-26 | 1983-11-30 | Nec Corp | Variable switched capacitor filter |
-
1984
- 1984-02-20 JP JP59029739A patent/JPS60173916A/en active Granted
-
1985
- 1985-02-20 US US06/703,576 patent/US4623854A/en not_active Expired - Lifetime
- 1985-02-20 CA CA000474723A patent/CA1234415A/en not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58205322A (en) * | 1982-05-26 | 1983-11-30 | Nec Corp | Variable switched capacitor filter |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60173916A (en) | 1985-09-07 |
| CA1234415A (en) | 1988-03-22 |
| US4623854A (en) | 1986-11-18 |
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