JPH0341146A - Resin composition - Google Patents
Resin compositionInfo
- Publication number
- JPH0341146A JPH0341146A JP1325234A JP32523489A JPH0341146A JP H0341146 A JPH0341146 A JP H0341146A JP 1325234 A JP1325234 A JP 1325234A JP 32523489 A JP32523489 A JP 32523489A JP H0341146 A JPH0341146 A JP H0341146A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- semiconductor chip
- coating
- stress
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000011342 resin composition Substances 0.000 title claims abstract 4
- 229920005989 resin Polymers 0.000 claims abstract description 51
- 239000011347 resin Substances 0.000 claims abstract description 51
- 239000000843 powder Substances 0.000 claims abstract description 18
- 239000010453 quartz Substances 0.000 claims abstract description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229920002857 polybutadiene Polymers 0.000 claims abstract description 13
- 239000007788 liquid Substances 0.000 claims description 2
- 239000007822 coupling agent Substances 0.000 claims 1
- QGBSISYHAICWAH-UHFFFAOYSA-N dicyandiamide Chemical compound NC(N)=NC#N QGBSISYHAICWAH-UHFFFAOYSA-N 0.000 claims 1
- 239000004850 liquid epoxy resins (LERs) Substances 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 abstract description 56
- 239000000758 substrate Substances 0.000 abstract description 39
- 239000003822 epoxy resin Substances 0.000 abstract description 14
- 229920000647 polyepoxide Polymers 0.000 abstract description 14
- VTYYLEPIZMXCLO-UHFFFAOYSA-L Calcium carbonate Chemical compound [Ca+2].[O-]C([O-])=O VTYYLEPIZMXCLO-UHFFFAOYSA-L 0.000 abstract description 12
- 229920001971 elastomer Polymers 0.000 abstract description 11
- 229910000019 calcium carbonate Inorganic materials 0.000 abstract description 6
- 229910010272 inorganic material Inorganic materials 0.000 abstract description 4
- 239000011147 inorganic material Substances 0.000 abstract description 4
- 229910010271 silicon carbide Inorganic materials 0.000 abstract description 4
- 239000000203 mixture Substances 0.000 abstract description 3
- FRWYFWZENXDZMU-UHFFFAOYSA-N 2-iodoquinoline Chemical compound C1=CC=CC2=NC(I)=CC=C21 FRWYFWZENXDZMU-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 2
- LTPBRCUWZOMYOC-UHFFFAOYSA-N beryllium oxide Inorganic materials O=[Be] LTPBRCUWZOMYOC-UHFFFAOYSA-N 0.000 abstract description 2
- 229920002379 silicone rubber Polymers 0.000 abstract description 2
- 239000004945 silicone rubber Substances 0.000 abstract description 2
- 239000004020 conductor Substances 0.000 abstract 2
- 229910003465 moissanite Inorganic materials 0.000 abstract 2
- 235000010216 calcium carbonate Nutrition 0.000 abstract 1
- 239000000806 elastomer Substances 0.000 abstract 1
- 229920001187 thermosetting polymer Polymers 0.000 abstract 1
- 229910000679 solder Inorganic materials 0.000 description 70
- 238000000576 coating method Methods 0.000 description 48
- 239000011248 coating agent Substances 0.000 description 46
- 239000011521 glass Substances 0.000 description 27
- 239000002245 particle Substances 0.000 description 19
- 239000000463 material Substances 0.000 description 18
- 238000002156 mixing Methods 0.000 description 17
- 238000010586 diagram Methods 0.000 description 16
- 230000000694 effects Effects 0.000 description 13
- 238000000034 method Methods 0.000 description 12
- 239000005060 rubber Substances 0.000 description 10
- 239000005062 Polybutadiene Substances 0.000 description 7
- 230000007423 decrease Effects 0.000 description 7
- 229910052718 tin Inorganic materials 0.000 description 7
- 238000002844 melting Methods 0.000 description 6
- 230000008018 melting Effects 0.000 description 6
- 239000004973 liquid crystal related substance Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 229920001296 polysiloxane Polymers 0.000 description 5
- 238000009826 distribution Methods 0.000 description 4
- 238000002474 experimental method Methods 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 3
- 239000013013 elastic material Substances 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 239000004925 Acrylic resin Substances 0.000 description 2
- 229920000178 Acrylic resin Polymers 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 2
- CDBYLPFSWZWCQE-UHFFFAOYSA-L Sodium Carbonate Chemical compound [Na+].[Na+].[O-]C([O-])=O CDBYLPFSWZWCQE-UHFFFAOYSA-L 0.000 description 2
- 239000000872 buffer Substances 0.000 description 2
- 239000006185 dispersion Substances 0.000 description 2
- 239000000835 fiber Substances 0.000 description 2
- 239000003365 glass fiber Substances 0.000 description 2
- 239000008187 granular material Substances 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- RSWGJHLUYNHPMX-UHFFFAOYSA-N Abietic-Saeure Natural products C12CCC(C(C)C)=CC2=CCC2C1(C)CCCC2(C)C(O)=O RSWGJHLUYNHPMX-UHFFFAOYSA-N 0.000 description 1
- 235000001543 Corylus americana Nutrition 0.000 description 1
- 240000007582 Corylus avellana Species 0.000 description 1
- 235000007466 Corylus avellana Nutrition 0.000 description 1
- KHPCPRHQVVSZAH-HUOMCSJISA-N Rosin Natural products O(C/C=C/c1ccccc1)[C@H]1[C@H](O)[C@@H](O)[C@@H](O)[C@@H](CO)O1 KHPCPRHQVVSZAH-HUOMCSJISA-N 0.000 description 1
- 239000006087 Silane Coupling Agent Substances 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000006172 buffering agent Substances 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 239000000498 cooling water Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- KHPCPRHQVVSZAH-UHFFFAOYSA-N trans-cinnamyl beta-D-glucopyranoside Natural products OC1C(O)C(O)C(CO)OC1OCC=CC1=CC=CC=C1 KHPCPRHQVVSZAH-UHFFFAOYSA-N 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Compositions Of Macromolecular Compounds (AREA)
- Epoxy Resins (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明、半導体チップの電極端子をＣＣＢ法（Ｃｏｎｔ
ｒｏｌｌｅｄ Ｃｏ１１ａｐｓｅ Ｂｏｎｄｉｎｇ法）
により基板上の電極端子に接合した後、樹脂により被覆
してなる構造の半導体装置に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention provides electrode terminals of semiconductor chips using the CCB method (Cont
rolled Co11apse Bonding method)
The present invention relates to a semiconductor device having a structure in which the semiconductor device is bonded to an electrode terminal on a substrate and then covered with a resin.
このような構造の半導体装置が適用された具体的な一例
として、第１図に示す要部断面構造図のように、液晶表
示素子の形成されたガラス基板上に、その液晶表示素子
を開動する半導体チップを載置して一体形成したものが
知られている。即ち、ガラス基板１の上面に形成された
電極端子２と、シリコン半導体からなる半導体チップ（
以下、Ｓｉチップと称する）３の下面に形成された電極
端子４とを対向配置し、これらの電極端子２，４間をＣ
ＣＢ法により形成されるはんだバンプ５によって接合し
１次にシリコ、ンゲル等の如き柔軟性を有する樹脂６を
、ガラス基板上とＳｉチップ３の空隙部に充填し、さら
に、Ｓｉチップ３の上及び側面を炭酸カルシウムを混入
したビスフェニール型の低膨張エポキシ系樹脂７により
被覆した構造となっている。As a specific example in which a semiconductor device with such a structure is applied, as shown in the cross-sectional structural diagram of the main part shown in FIG. 1, a liquid crystal display element is opened on a glass substrate on which a liquid crystal display element is formed. A device in which a semiconductor chip is mounted and formed integrally is known. That is, an electrode terminal 2 formed on the upper surface of a glass substrate 1 and a semiconductor chip (
The electrode terminals 4 formed on the lower surface of the 3 (hereinafter referred to as Si chips) are arranged to face each other, and the electrode terminals 2 and 4 are connected by C.
They are bonded by solder bumps 5 formed by the CB method, and then a flexible resin 6 such as silicone or gel is filled into the gap between the glass substrate and the Si chip 3. It has a structure in which the side surfaces are coated with bisphenyl type low expansion epoxy resin 7 mixed with calcium carbonate.
ところが、上述構造の半導体装置について、４０℃←→
１００℃の温度条件で温度サイクル試験を行ったところ
、被覆のないもの（以下、裸チップと称する）よりも耐
熱疲労性がかなり劣るという結果が得られた。そこで、
その原因を実験等により検討した結果、（１）樹脂材料
、（２）樹脂被覆構造、及び（３）はんだバンプ構造の
３点について１次に述べるような欠点があることが判っ
た。However, for the semiconductor device with the above structure, the temperature at 40°C←→
When a temperature cycle test was conducted under a temperature condition of 100° C., the result was that the thermal fatigue resistance was considerably inferior to that of a chip without a coating (hereinafter referred to as a bare chip). Therefore,
As a result of examining the causes of this through experiments and the like, it was found that there are three drawbacks as described below: (1) resin material, (2) resin coating structure, and (3) solder bump structure.
即ち、炭酸カルシウム粉をエポキシ樹脂に混入すると、
膨張係数を大きく下げることができるが。That is, when calcium carbonate powder is mixed into epoxy resin,
Although it is possible to significantly lower the expansion coefficient.
Ｓｉチップやガラス基板に比較するとまだ大であること
、しかも炭酸カルシウムの混入率を増すと樹脂の硬度が
増大することから、必ずしも耐熱疲労性は向上しない。It is still large compared to Si chips and glass substrates, and furthermore, increasing the proportion of calcium carbonate increases the hardness of the resin, so the thermal fatigue resistance does not necessarily improve.
また、低膨張エポキシ樹脂を用いた樹脂被覆の形状、及
びはんだバンプの形状に関する応力分布。Also, stress distribution regarding the shape of resin coating using low expansion epoxy resin and the shape of solder bumps.
特に応力集中及びはんだバンプの柔軟性は、耐熱疲労性
に大きく影響する。In particular, stress concentration and solder bump flexibility greatly affect thermal fatigue resistance.
本発明の目的は、耐熱疲労性を向上させることができる
被覆樹脂の材料、被覆の形状、及びはんだバンプの形状
を有してなる半導体装置を提供することにある。An object of the present invention is to provide a semiconductor device having a coating resin material, a coating shape, and a solder bump shape that can improve thermal fatigue resistance.
〔課題を解決するための手段〕
本発明は、被覆樹脂はエポキシ樹脂を主材料とし、これ
にエポキシ樹脂よりも小さい熱膨張係数を有する無機材
料からなる第１の粉粒体、及びゴム状弾性材料からなる
第２の粉粒体を少なくとも混入したものとし、
また、前記被覆樹脂は半導体チップの周囲とその上面を
被い、且つ前記半導体チップ周辺の基板上面に形成する
樹脂被覆の幅は、その幅方向の半導体チップ幅の１倍以
上１．５倍以下とし、さらに、はんだバンプ、の形状は
円柱型またはっづみ型に形成することによって、耐熱疲
労性を向上させようとするものである。[Means for Solving the Problems] The present invention provides that the coating resin is mainly made of epoxy resin, and a first granular material made of an inorganic material having a coefficient of thermal expansion smaller than that of the epoxy resin, and a rubber-like elastic material. At least a second granular material made of a material is mixed therein, and the coating resin covers the periphery and the upper surface of the semiconductor chip, and the width of the resin coating formed on the upper surface of the substrate around the semiconductor chip is as follows: The solder bumps are designed to improve thermal fatigue resistance by making the solder bumps at least 1 times and 1.5 times the width of the semiconductor chip in the width direction, and by forming the solder bumps into a cylindrical or cylindrical shape. .
以下１本発明を実施例に基づいて説明する。 The present invention will be explained below based on examples.
まず１本発明の被覆樹脂材料について説明する。First, the coating resin material of the present invention will be explained.
エポキシ樹脂の熱膨張係数αＲＯは約１００ＸＩＯ−’
／ ’Ｃであり、半導体チップ、例えばＳｉチップの
熱膨張係数αｓ ｉ ； ３ Ｘ １０− ’ ／ ”
Ｃ−や、基板、例えばガラス基板のソーダガラスの熱膨
張係数αｏ ； ９．３３ｘ １０−” ／ ”Ｃに比
べて大きい、一般に、耐熱疲労性を向上させるには、熱
膨張係数が半導体チップや基板のそれに近い被覆樹脂を
適用することが望ましい。The coefficient of thermal expansion αRO of epoxy resin is approximately 100XIO-'
/'C, and the thermal expansion coefficient αs i of a semiconductor chip, for example, a Si chip; 3 x 10-'/''
9.33 It is desirable to apply a coating resin similar to that of the substrate.
そこで、エポキシ樹脂に炭酸カルシウムや石英粉等の如
き、熱膨張係数の小さな無機材料（以下、低膨張化材と
称する）を混入して低膨張化するようにしている。例え
ば、体積にして５０％の石英粉を混入すると、熱膨張係
数αＲは約２５Ｘ１０−’／℃に低下する。しかし、混
入率を高くするにしたがって樹脂の粘度が高くなり、流
動性が低下する。流動性が低下すると、被覆工程におい
ては、はんだバンプ周囲の空隙部に樹脂が侵入しにくく
なって、空隙部が残ったり、基板との密着性が低したり
、被覆の作業性が低下するという問題が生ずる。この結
果、逆に耐熱疲労性及び耐湿性が低下してしまうことが
ある。また、混入率を高くすると樹脂の柔軟性が低下し
て、基板との接着部に応力が集中するため、この応力に
よりガラス等の基板が破損されてしまうことがある。Therefore, an inorganic material with a small coefficient of thermal expansion (hereinafter referred to as a low-expansion material), such as calcium carbonate or quartz powder, is mixed into the epoxy resin to reduce the expansion. For example, when 50% by volume of quartz powder is mixed, the coefficient of thermal expansion αR decreases to about 25×10 −′/° C. However, as the mixing rate increases, the viscosity of the resin increases and fluidity decreases. When fluidity decreases, it becomes difficult for the resin to penetrate into the voids around the solder bumps during the coating process, resulting in voids remaining, poor adhesion to the board, and reduced coating workability. A problem arises. As a result, thermal fatigue resistance and moisture resistance may be adversely reduced. Furthermore, when the mixing rate is increased, the flexibility of the resin decreases and stress is concentrated at the bonded portion with the substrate, which may damage the substrate such as glass.
したがって、単に低膨張化材を混入して低膨張化するだ
けでは、耐熱疲労性の向上に一定の限度があるため、さ
らにその流動性及び柔軟性を改善する必要がある。Therefore, there is a certain limit to improving thermal fatigue resistance by simply mixing a low-expansion material to lower the expansion, so it is necessary to further improve the fluidity and flexibility.
そこで、本発明は低膨張化材に加えて粒状の弾性材料１
例えばポリブタジェンやシリコン等のゴム粒子を分散混
入し、これによって柔軟性及び流動性を向上させようと
するものである。つまり、被覆樹脂内のゴム粒子は応力
緩衝材とし作用するので柔軟性が向上して応力集中や歪
が緩和されることから、これによって耐熱疲労性を向上
させようとするものである。また、粒状のゴム粒子の作
用によって流動性を向上させようとするものである。し
かし、後述するように、ゴム粒子の混入率にも最適な範
囲がある。例えば、粒径１μｍレベルのポリブタン１ン
（ＣＴＢＮ １３００ｘ９）からなるゴム粒子を混入
した場合、エポキシ樹脂に対するゴム粒子の重量比を１
００対２０以上（以下、重量部または単に部と称し、例
えば２０部以上と表現する）にすると、ゴム粒子の分散
が不均一になってしまうとともに、ポリブタジェンの熱
膨張係数αＰＢは約８０ Ｘ １０−’／℃と大きいの
で、混入後の被覆樹脂の熱膨張係数αＲが大となってし
まい、耐熱疲労性を低下させる原因となるのである。ま
た、流動性向上の効果にあっても飽和現象があるので大
幅向上は期待できない。Therefore, the present invention provides a granular elastic material 1 in addition to the low expansion material.
For example, rubber particles such as polybutadiene or silicone are dispersed and mixed in to improve flexibility and fluidity. In other words, the rubber particles in the coating resin act as a stress buffer, improving flexibility and relieving stress concentration and strain, thereby improving thermal fatigue resistance. Further, it is intended to improve fluidity through the action of granular rubber particles. However, as will be described later, there is an optimum range for the mixing ratio of rubber particles. For example, when rubber particles made of polybutane 1300x9 (CTBN 1300x9) with a particle size of 1 μm are mixed, the weight ratio of the rubber particles to the epoxy resin is 1 μm.
If the ratio is 0.00 to 20 or more (hereinafter referred to as parts by weight or simply parts, for example, expressed as 20 parts or more), the dispersion of rubber particles will become uneven, and the thermal expansion coefficient αPB of polybutadiene will be approximately 80 x 10 -'/°C, which increases the coefficient of thermal expansion αR of the coating resin after mixing, which causes a decrease in thermal fatigue resistance. Furthermore, even with the effect of improving fluidity, there is a saturation phenomenon, so a significant improvement cannot be expected.
これらのことを、実施例を用いて行った実験結果に基づ
いて説明する。第１表に、エポキシ樹脂（ＥＰ−８２８
）を主材料とし１粒径的ｌｐｍの石英粉を低膨張化材と
し、粒径的１μｍのポリブタジェンの均一なゴム粒子を
緩衝材とし、それらの混入率の異なる種々の樹脂により
被覆した半導体装置を試料として、前述と同一の温度サ
イクル試験を行った判定結果を示す、なお、基板、半導
体チップ及びはんだバンプは第１図図示と同一構成のも
のとし、判定は、樹脂被覆を施さない裸チップのものに
比較して、早いサイクルにて故障に至った試料を不合格
として×印で示し、合格したものについては故障率を基
準に、優れている順に０、Δ印で示した。故障率の一例
として、第２図（Ａ）に石英粉の混入率を３５体積％に
固定し、ポリブタジェンゴム粒子の混入率を変化させた
場合を、第２図（Ｂ）にポリブタジェンゴム粒子の混入
率をＩＯ部に固定し１石英粉の混入率を変化させた場合
を、それぞれ示す、なお、第２図（Ａ）（Ｂ）図中実線
で示したものは、１サイクル／工時間の温度サイクル試
験を９００サイクル行った例であり、図中点線で示した
ものは同様に５００サイクルの例である。These matters will be explained based on the results of experiments conducted using Examples. Table 1 shows epoxy resin (EP-828
) as the main material, 1 lpm quartz powder as the low expansion agent, 1 μm particle size uniform rubber particles of polybutadiene as the buffer material, and covered with various resins with different mixing ratios. This is the result of the same temperature cycle test as above using the same sample as above.The substrate, semiconductor chip, and solder bumps are of the same configuration as shown in Figure 1, and the judgment is based on the bare chip without resin coating. Samples that failed in an earlier cycle than the sample were marked with an x as a failure, and those that passed were marked with a 0 or Δ mark in order of superiority based on the failure rate. As an example of the failure rate, Fig. 2 (A) shows the case where the mixing rate of quartz powder is fixed at 35% by volume and the mixing rate of polybutadiene rubber particles is varied, and Fig. 2 (B) shows the case where the mixing rate of polybutadiene rubber particles is fixed at 35% by volume. The cases in which the mixing rate of Gen rubber particles is fixed in the IO part and the mixing rate of 1 quartz powder are varied are shown. In addition, the solid lines in Figure 2 (A) and (B) indicate 1 cycle. This is an example in which a temperature cycle test of /manufacturing time was performed for 900 cycles, and the dotted line in the figure is also an example for 500 cycles.
また、被覆樹脂には硬化温度を低くするための添加剤、
例えば硬化促進剤としてイソダゾル（２部４ＭＨ２）を
５重量％、硬化剤としてジシアンアミドを１０重量％、
シランカップリング剤（Ａ−１８７）を２重量％等を混
入し、硬化温度１３０℃、＊化温度を時間として基板の
熱的影響を避けるようにした。In addition, additives are added to the coating resin to lower the curing temperature.
For example, 5% by weight of isodazole (2 parts 4MH2) as a curing accelerator, 10% by weight of dicyanamide as a curing agent,
A silane coupling agent (A-187) was mixed in an amount of 2% by weight, and the curing temperature was set at 130° C., and the * temperature was set as the time to avoid thermal influence on the substrate.
第１表に示す判定結果から、低膨張化剤と緩衝剤の混入
効果について考察する。まず、ポリブタジェンの混入率
が０部、即ち石英粉のみを混入した試料は、全て裸チッ
プのものより悪い判定結果となっているが、樹脂被覆さ
れた試料相互間で定量的に比較すると１石英粉の混入率
を高めるにしたがい熱疲労寿命が増大されるということ
を実験で確認している。但し、石英粉の混入により流動
性が低下して、Ｓｉチップ３下側とはんだバンプ５の周
囲への浸透が悪くなるので、この点からみて１石英粉の
混入率は６０体積％が限界である。Based on the determination results shown in Table 1, the effect of mixing the low expansion agent and buffering agent will be discussed. First, samples with a polybutadiene content of 0 parts, that is, samples containing only quartz powder, all had worse judgment results than those with bare chips, but when compared quantitatively between resin-coated samples, 1 quartz powder was mixed. It has been confirmed through experiments that the thermal fatigue life increases as the powder content increases. However, the mixing of quartz powder lowers the fluidity and makes it difficult to penetrate into the lower side of the Si chip 3 and around the solder bumps 5, so from this point of view, the limit for the mixing rate of 1 quartz powder is 60% by volume. be.
一方、ポリブタジェンは若干混入するだけで、第２図（
Ａ）に示すように、急激に故障率が低下されており、緩
衝材及び流動化材としての効果が顕著に表れ、耐熱疲労
性において裸チップよりも優れた特性が得られた。但し
、ポリブタジェン混入率を高くすると、前述したように
、その分散が不均一となり、耐熱疲労性が低下する。On the other hand, polybutadiene is only slightly mixed, as shown in Figure 2 (
As shown in A), the failure rate was rapidly reduced, the effect as a buffering material and fluidizing material was remarkable, and properties superior to bare chips in terms of thermal fatigue resistance were obtained. However, if the polybutadiene mixing ratio is increased, the dispersion becomes non-uniform as described above, and the thermal fatigue resistance decreases.
これらのこと及び第１表から１石英粉の混入率は３０〜
５５体積％、ポリブタジェンゴム粒子の混入率は１〜２
０部の範囲に選定することにより、裸チップよりも優れ
た耐熱疲労性のものとすることができる０例えば、石英
粉５０体積％、ポリブタジェン５部を混入したものの耐
熱疲労性（寿命）は、裸チップの３倍以上であり、信頼
性が大幅に向上された。From these facts and Table 1, the mixing rate of 1 quartz powder is 30~
55% by volume, the mixing rate of polybutadiene rubber particles is 1-2
For example, the thermal fatigue resistance (life) of a chip mixed with 50% by volume of quartz powder and 5 parts of polybutadiene is as follows: This is more than 3 times that of a bare chip, and reliability has been greatly improved.
なお、低膨張化材としては石英の他、炭酸カルシウム、
炭化シリコン、ぶ化シリコン、または酸化ベリリウム混
入の炭化シリコン等の如き、いわゆる熱膨張係数の小さ
な無機材料が適用可能であり、同一の効果が得られる。In addition to quartz, low-expansion materials include calcium carbonate,
Inorganic materials with a so-called small coefficient of thermal expansion, such as silicon carbide, silicon nitride, or silicon carbide mixed with beryllium oxide, can be used, and the same effect can be obtained.
この低膨張化材の粒径にあっても、上記実施例の１μｍ
に限られるものではない。Even if the particle size of this low expansion material is 1 μm as in the above example,
It is not limited to.
また１弾性材としてはポリブタジェンゴム粒子の他、シ
リコンゴム粒子等の如き、いわゆる弾性の大きなゴム粒
子が適用可能であり、その粒径にあっても、１μｍに限
られるものではない。Further, as the first elastic material, in addition to polybutadiene rubber particles, so-called highly elastic rubber particles such as silicone rubber particles can be used, and the particle size thereof is not limited to 1 μm.
次に、樹脂被覆の形状について説明する。Next, the shape of the resin coating will be explained.
前述したように１石英粉等の低膨張化材を混入しても、
エポキシ樹脂の熱膨張係数αＲはソーダガラスや半導体
チップに比べてまだ大きな値である。そして、それらの
部材間の熱膨張量の差により生ずる応力によって半導体
チップ、はんだバンプ、ガラス基板、又はそれら部材の
接続部が破損されるのである。実験によると、はんだバ
ンプと半導体チップとの接続部が、繰返し応力に対して
最も弱いことが判った。As mentioned above, even if low expansion materials such as quartz powder are mixed in,
The coefficient of thermal expansion αR of epoxy resin is still larger than that of soda glass or semiconductor chips. The semiconductor chip, solder bumps, glass substrate, or connection portions of these members are damaged due to stress caused by the difference in the amount of thermal expansion between these members. Experiments have shown that the connection between the solder bump and the semiconductor chip is the most vulnerable to repeated stress.
そこで、その接続部に発生する応力を低減することがで
きる樹脂被覆の形状、即ち、半導体チップ上面の被覆厚
みと、半導体チップ周辺部の被覆幅について、有限要素
法により求めた。Therefore, the shape of the resin coating that can reduce the stress generated at the connection part, that is, the coating thickness on the upper surface of the semiconductor chip and the coating width around the semiconductor chip, was determined using the finite element method.
即ち、半導体チップ上面の被覆厚みｔ＋＋ａとしたとき
、はんだバンプと半導体チップの接続部にかかる最大応
力（破損に関係する引張応力）を求め、第３図（Ａ）に
裸チップにおける最大引張応力に対する比率として示し
た。なお、第３図（Ｂ）、（Ｃ）に示すように、ガラス
基板１、半導体チップ３は６ｍ角のＳｉチップ、はんだ
チップ５は球欠体形状のものとし、樹脂被覆７は全体＠
Ｌを１５ｍ角一定としたものをモデルとし１図示矢印９
の方向の最大応力を求めたものである。矢印９の位置に
おける応力は、温度が室温（２０℃）から１００℃に変
化したときは引張応力となり、室温（２０℃）から−４
０℃に変化したときは圧縮応力になる。また、樹脂はエ
ポキシ樹脂に石英粉のみを混入した流動性の劣るものと
し、基板１とチップ３のとの間に空隙８が生じたものを
モデルとした。That is, when the coating thickness on the top surface of the semiconductor chip is t++a, the maximum stress (tensile stress related to breakage) applied to the connection between the solder bump and the semiconductor chip is determined, and Fig. 3 (A) shows the maximum stress applied to the bare chip with respect to the maximum tensile stress. Shown as a ratio. As shown in FIGS. 3(B) and 3(C), the glass substrate 1, the semiconductor chip 3 is a 6 m square Si chip, the solder chip 5 is in the shape of a truncated ball, and the resin coating 7 is entirely @
The model is one in which L is constant at 15 m square. 1 Arrow 9
The maximum stress in the direction of is calculated. The stress at the position of arrow 9 becomes tensile stress when the temperature changes from room temperature (20°C) to 100°C, and from room temperature (20°C) to -4°C.
When the temperature changes to 0°C, compressive stress occurs. In addition, the resin was made of an epoxy resin mixed with only quartz powder and had poor fluidity, and a model was used in which a gap 8 was created between the substrate 1 and the chip 3.
第３図（Ａ）から明らかなように、被覆厚みｔが増すに
つれて、半導体チップ３とはんだバンプ５の接続部にか
かる最大引張応力が大きくなることから、被覆厚みｔは
薄いほどよいということになるが、機械的保護及び耐湿
性保持から許容最小厚みが制限され、ｔは１±０．５ｍ
の範囲で選定することが望ましい。As is clear from FIG. 3(A), as the coating thickness t increases, the maximum tensile stress applied to the connection between the semiconductor chip 3 and the solder bumps 5 increases, so the thinner the coating thickness t, the better. However, the minimum allowable thickness is limited due to mechanical protection and moisture resistance, and t is 1 ± 0.5 m.
It is desirable to select within the range of .
一方、第４図（Ａ）に半導体チップの周辺に形成される
樹脂被覆の幅と、前記接続部にかかる最大応力との関係
を示す、なお、モデルは第４図（Ｂ）、（Ｃ）に示すよ
うに第３図（Ｂ）、（Ｃ）と同様のものであり、被覆厚
みｔを１．５ｎｎ一定、半導体チップ３の幅を２ａ、半
導体チップ端縁から被覆外縁までの寸法、即ち半導体チ
ップ周辺領域に形成される被覆の幅を悲とした。On the other hand, Fig. 4(A) shows the relationship between the width of the resin coating formed around the semiconductor chip and the maximum stress applied to the connection part.The model is shown in Fig. 4(B) and (C). As shown in FIG. 3(B) and (C), the coating thickness t is constant at 1.5 nn, the width of the semiconductor chip 3 is 2a, and the dimension from the edge of the semiconductor chip to the outer edge of the coating, i.e. The width of the coating formed in the peripheral area of the semiconductor chip was determined.
第４図（Ａ）に示すように、Ｑ ／ ａが増すにつれて
最大引張応力が現象する傾向にある。このことは、周辺
域の被覆幅悲が広くなると、被覆幅悲の中心（図示Ｂ、
Ｂ’）より内側の被覆が温度上昇時に内側方向に伸び、
これによって半導体チップ３に対して圧縮方向に応力が
作用すると考えられる。なお、このことは計算によって
確認している。As shown in FIG. 4(A), the maximum tensile stress tends to increase as Q/a increases. This means that when the coverage width of the peripheral area becomes wider, the center of the coverage width (as shown in figure B)
B') The inner coating stretches inward when the temperature rises,
It is thought that this causes stress to act on the semiconductor chip 3 in the compressive direction. This fact has been confirmed through calculation.
したがって、Ｑ ／ ａを大にすれば最大引張応力を減
少することができる。即ち、被覆樹脂の熱膨張係数が大
であっても、被覆形状を適切なものとすることにより、
裸チップのものより耐熱疲労性を向上させることができ
る。しかし、Ｑ ／ ａ≧３．０以上にしても、最大引
張応力の低減効果が小さくなる反面、ガラス基板１と樹
脂被覆７との接合部のガラス破損が起こりやすくなるこ
と、及び樹脂被覆１４全体の面積的制限を考慮すると、
Ｑ ／ ａは２〜３が望ましい範囲である。因に、最適
な形状の一例を示せば、半導体チップ上面の被覆厚みｔ
は０．５ｎｎ、Ｑ／ａは２となる。Therefore, the maximum tensile stress can be reduced by increasing Q/a. In other words, even if the thermal expansion coefficient of the coating resin is large, by making the coating shape appropriate,
Thermal fatigue resistance can be improved compared to bare chips. However, even if Q/a≧3.0 or more, the effect of reducing the maximum tensile stress will be reduced, but on the other hand, glass breakage will easily occur at the joint between the glass substrate 1 and the resin coating 7, and the entire resin coating 14 will be damaged. Considering the area limitation of
Q/a is preferably in the range of 2 to 3. Incidentally, to give an example of the optimal shape, the coating thickness t on the top surface of the semiconductor chip
is 0.5nn, and Q/a is 2.
次に、はんだバンプの形状について説明する。Next, the shape of the solder bump will be explained.
上述した被覆樹脂材料及び被覆形状についての実施例で
は、はんだバンプの形状が球欠体の場合として説明した
が、樹脂の変形に追従できるはんだバンプ形状、又はは
んだバンプにかかる応力を低減できる形状にすれば、＃
熱疲労性は飛躍的に向上される筈である。In the above-mentioned examples regarding the coating resin material and the coating shape, the solder bump shape was described as a rounded part, but the solder bump shape could be a shape that can follow the deformation of the resin or a shape that can reduce the stress applied to the solder bump. if,#
Thermal fatigue resistance should be dramatically improved.
そこで、はんだバンプの形状を第５図（Ａ）〜（Ｄ）に
示す形状に形成し、熱疲労寿命と機械的強度とを実験的
に求めた。なお、第５図（Ａ）〜（Ｄ）に示すはんだバ
ンプは全て同一体積とし、ＣＣＢ法において半導体チッ
プと基板との間隙寸法を変えることによって、はんだバ
ンプの高さ及び中央部の径すを変えた。Therefore, the shapes of solder bumps were formed as shown in FIGS. 5(A) to 5(D), and the thermal fatigue life and mechanical strength were experimentally determined. The solder bumps shown in FIGS. 5(A) to 5(D) all have the same volume, and by changing the gap size between the semiconductor chip and the substrate in the CCB method, the height and center diameter of the solder bumps can be adjusted. changed.
第６図は上述のように形成されたはんだバンプを有する
裸チップに対し、縦横の強制歪を与えたとき、熱疲労寿
命及び機械的強度がどのようになるかを示した線図であ
る。同図において、横軸にはんだバンプの中央の径すと
端子径Ｃの比ｂ ／ ｃをとり、縦軸に第５図（Ｄ）に
示す球欠体型の熱疲労寿命を１とし、これに対する各形
状の熱疲労寿命を比で示すとともに、同様に圧縮強度又
は引張強度からなる機械的強度の比で示した。FIG. 6 is a diagram showing how the thermal fatigue life and mechanical strength change when vertical and horizontal forced strain is applied to a bare chip having solder bumps formed as described above. In the same figure, the ratio b/c of the center diameter of the solder bump to the terminal diameter C is plotted on the horizontal axis, and the thermal fatigue life of the ball-cut type shown in FIG. 5 (D) is plotted as 1 on the vertical axis. The thermal fatigue life of each shape is shown as a ratio, and also as a ratio of mechanical strength consisting of compressive strength or tensile strength.
第６図図示曲線（Ｉ）に示すように、熱疲労寿命特性は
、ｂ／ｃが大になるほど、即ち球欠体形状になるほど急
激に悪くなることが判る。このことは、はんだバンプ内
の応力分布がその形状によて大きく異なっているためで
ある。即ち、第５図（Ａ）、（Ｂ）に示したｂ ／ ｃ
＜ １のいわゆるつづみ型のはんだバンプにかかる応
力を有限要素法により求めたところ、第７図（Ａ）に示
す分布となることが判った。同図において、矢印は各区
画領域における応力の方向とその大きさを表しており、
応力はほぼ一様に分布していることが判る。As shown in the curve (I) in FIG. 6, it can be seen that the thermal fatigue life characteristics deteriorate rapidly as b/c increases, that is, as the shape becomes a truncated sphere. This is because the stress distribution within the solder bump varies greatly depending on its shape. That is, b/c shown in FIGS. 5(A) and (B)
When the stress applied to the so-called Tsuzumi-type solder bumps with < 1 was determined by the finite element method, it was found that the stress was distributed as shown in FIG. 7(A). In the figure, the arrows represent the direction and magnitude of stress in each section,
It can be seen that the stress is distributed almost uniformly.
これに対し、第５図（Ｄ）に示したｂ ／ ｃ ＞ １
の球欠体型のはんだバンプの場合は、第７図（Ｂ）に示
す応力分布となり、両端の接合界面部に応力が集中し、
この部分から熱疲労破断が発生する。On the other hand, b/c > 1 shown in Fig. 5(D)
In the case of a spherical solder bump, the stress distribution is shown in Figure 7 (B), and the stress is concentrated at the bonding interface at both ends.
Thermal fatigue fracture occurs from this part.
また、はんだバンプの高さが大になるつづみ型ものにあ
っては、一定量の変形に対して歪は相対的に小さくなる
ことから、熱疲労寿命が向上されるのである。しかし、
ｂ ／ ｃをさらに小さくした極端なつづみ型にすると
、応力が中央部に集中するようになるのと、第６図図中
曲線（ＩＩ）で示す機械的強度が低下するので、はんだ
バンプが破断してしまうことから、熱疲労寿命の増大が
おさえられてしまう。In addition, in the case of a solder bump type in which the height of the solder bump is large, the strain becomes relatively small for a certain amount of deformation, so the thermal fatigue life is improved. but,
If b/c is made even smaller to make the solder bump shape more extreme, the stress will be concentrated in the center and the mechanical strength shown by curve (II) in Figure 6 will decrease, so the solder bumps will be Since it breaks, the increase in thermal fatigue life is suppressed.
従って、はメツだバンプの形状は少なくともｂ／ｃ＝１
の円柱型とし、好ましくは０．５≦ｂ ／ ｃくｌの範
囲のつづみ型とするのがよい。Therefore, the shape of the bump is at least b/c=1
It is preferable to have a cylindrical shape, preferably a cylindrical shape in the range of 0.5≦b/cc.
ところで、上述は裸チップのものであるが、樹脂被覆を
施したものの場合は、樹脂の熱膨張係数が大であること
から、はんだバンプの形状としては大きな変形量に対し
て追従できるものが望ましい、この点についても、つづ
み型は高さが大きいことから、前述したように、一定変
形量に対し相対的に歪が小さくなるので望ましいことに
なる。By the way, the above description is of a bare chip, but in the case of a resin-coated chip, since the coefficient of thermal expansion of the resin is large, it is desirable that the shape of the solder bump can follow a large amount of deformation. In this respect as well, the tsume type is desirable because it has a large height and, as mentioned above, the strain is relatively small for a given amount of deformation.
例えば、第８図（Ａ）に示すように、はんだバンプ１０
はつづみ型のものとし、低膨張化エポキシ樹脂からなる
樹脂被ｒＩ１１１を施した場合、はんだバンプ１０に作
用する変形応力は、同図（Ｂ）の矢印１２．１３に示す
縦・横方向に作用する。For example, as shown in FIG. 8(A), solder bumps 10
When the solder bump 10 is made into a hazel shape and is coated with a resin coating rI111 made of a low-expansion epoxy resin, the deformation stress acting on the solder bump 10 will be in the vertical and horizontal directions as shown by the arrows 12.13 in the same figure (B). act.
第８図（Ａ）、（Ｂ）図示のものにおいて、ガラス基板
１の熱膨張係数をα□Ｓｉチップ３の熱膨張係数をαＳ
８、樹脂被覆１１の熱膨張係数をαＲ１横方向最大変形
量をΔＱｘ、縦方向最大変形量をΔＱｙ、Ｓｉチップ３
の１辺を２ａ、はんだバンプ１０の高さをｈ、せん断歪
をγ、軸方向歪をε、温度変化量をへＴ、定数をに１．
ｋ２． Ａ。8(A) and (B), the thermal expansion coefficient of the glass substrate 1 is α□The thermal expansion coefficient of the Si chip 3 is αS
8. The thermal expansion coefficient of the resin coating 11 is αR1, the maximum horizontal deformation is ΔQx, the vertical maximum deformation is ΔQy, and the Si chip 3
One side of is 2a, the height of the solder bump 10 is h, the shear strain is γ, the axial strain is ε, the amount of temperature change is T, and the constant is 1.
k2. A.
合計歪をＥ、熱疲労寿命をＮｔとすると、次式（１）〜
（５）が成立する。If the total strain is E and the thermal fatigue life is Nt, then the following formula (1) ~
(5) holds true.
ΔＱｘ”ａ （ａｔ ａｓｓ） ΔＴ
・（Ｌ）Δ１２ｙ＝ｈαＲΔＴ
・・・（２）γ＝に、ＩＩＱＸ ・
・・（３）・−に、ＡＱｙ ・・・（４
）ＩＩ
Ｎｔ ”Ａ・□＝Ａ ・・・（
５）Ｒ２γ２＋ε２
これらの式から、はんだバンプの高さｈが大であれば、
樹脂被覆の熱膨張によって生ずるΔ氾χ。ΔQx”a (at ass) ΔT
・(L)Δ12y=hαRΔT
...(2) γ=, IIQX ・
... (3) -, AQy ... (4
) II Nt ”A・□=A ・・・(
5) R2γ2+ε2 From these equations, if the height h of the solder bump is large, ∆ flood χ caused by thermal expansion of the resin coating.
ＡＱｙに対し、歪γ、εは小さくなる。Strains γ and ε become smaller with respect to AQy.
したがって、っづみ型のはんだバンプとすることにより
、はんだバンプ高さｈが大であることから歪が小さくな
り、しかも応力集中が緩和されることから、はんだバン
プと半導体チップとの接合部の破損が低減されて、耐熱
疲労性が著るしく向上するという効果がある。Therefore, by using the solder bump type, the solder bump height h is large, so the strain is small, and the stress concentration is alleviated, resulting in damage to the joint between the solder bump and the semiconductor chip. This has the effect of significantly improving thermal fatigue resistance.
なお、はんだの熱膨張係数は約２５Ｘ１０−’／℃程度
であり、低膨張化エポキシ樹脂と同等であることから、
はんだバンプ自体が樹脂被覆によって拘束されることは
少ない。Note that the thermal expansion coefficient of solder is approximately 25 x 10-'/°C, which is equivalent to a low-expansion epoxy resin.
The solder bump itself is rarely restrained by the resin coating.
以上、本発明の被覆樹脂材料、被覆形状、及びはんだバ
ンプ形状をそれぞれ個別に適用した実施例について説明
したが、それらの実施例を組み合わせることによって、
−層耐熱疲労特性に優れたものとすることができること
は言うまでもない。The embodiments in which the coating resin material, coating shape, and solder bump shape of the present invention are applied individually have been described above, but by combining these embodiments,
- It goes without saying that the layer can be made to have excellent thermal fatigue resistance.
なお、半導体チップの半導体素子が形成されている面は
、はんだバンプが接合されている面であるが、一般にこ
の面にはＳｉＯ□又はポリイミドなどの薄膜により保護
されている。しかし、はんだバンプが接合される部分は
それらの薄膜が形成されていないため、耐湿性の問題に
ついて考察する。一般に知られているＤ Ｉ Ｐ （Ｄ
ｕａｌ ＩｎｌｉｎｅＰａｃｋａｇｅ ）型の樹脂モー
ルド半導体装置にあっては、リードフレームのタブ上に
Ｓｉチップが接続され、素子側の端子はアルミニウム（
ＡＱ）線を超音波ボンディング法により接続し、その全
体を樹脂モールドした構造となっている。ところが、リ
ード線と樹脂の界面を伝わって水分が侵入し。Note that the surface of the semiconductor chip on which the semiconductor element is formed is the surface to which the solder bumps are bonded, and this surface is generally protected by a thin film of SiO□ or polyimide. However, since these thin films are not formed in the areas where the solder bumps are bonded, we will consider the issue of moisture resistance. The commonly known D I P (D
In a resin-molded semiconductor device of the ual InlinePackage) type, the Si chip is connected to the tab of the lead frame, and the terminals on the element side are made of aluminum (
AQ) wires are connected by ultrasonic bonding, and the entire structure is resin molded. However, moisture entered through the interface between the lead wire and the resin.
さらにＡＱ線にまで伝わってＡＱｌＪＡを腐食したり、
Ａｌ１線と素子の接合界面を腐食させて断線等の故障が
発生していた。Furthermore, it may be transmitted to the AQ line and corrode AQlJA,
The bonding interface between the Al1 wire and the element corroded, causing failures such as wire breakage.
しかし、本発明に係るＣＣＢ法により形成された構造の
樹脂被覆されたものによれば、樹脂被覆部分に上記ＤＩ
Ｐのリードの如き引出し線が無いこと、半導体チップ周
囲の被覆幅が大きいのでガラス基板と樹脂の界面から水
分は侵入しにくいこと、及びはんだ（Ｐｂ−５％Ｓｎ、
Ｐｂ−６０％Ｓｎ）はＡＱ線に比べて耐食性に優れてい
ることなどから、総じて耐湿性に優れていると言うこと
ができる。However, according to the resin-coated structure formed by the CCB method according to the present invention, the resin-coated portion has the above-mentioned DI.
There are no lead wires such as P leads, the coating width around the semiconductor chip is large, so it is difficult for moisture to enter from the interface between the glass substrate and the resin, and the solder (Pb-5%Sn,
Since Pb-60%Sn) has better corrosion resistance than AQ wire, it can be said that it has better moisture resistance overall.
さらに、厳しく耐湿性を要求される場合には。Furthermore, when moisture resistance is strictly required.
第９図に示すように、柔軟なシリコンゲル１４を半導体
チップ３の下に充填する２液被覆法が有効である。シリ
コンゲル１４は柔軟なことからはんだバンプ５表面、ガ
ラス基板上表面及び半導体チップ３表面との馴じみが良
く、水分の侵入を阻止することができる。しかん、シリ
コンゲル１４の熱膨張係数は約ｔｏｏｘｌｏ−’／’Ｃ
と大きいので、はんだバンプ５の表面を薄く被覆する程
度が望ましい、また、樹脂被覆１１とガラス基板１との
界面に防湿効果を有するアクリル樹脂膜１５を予め薄く
コーティングしておくと、ガラス割れを防止することが
できる。As shown in FIG. 9, a two-liquid coating method in which a flexible silicone gel 14 is filled under the semiconductor chip 3 is effective. Since the silicone gel 14 is flexible, it fits well with the surface of the solder bump 5, the upper surface of the glass substrate, and the surface of the semiconductor chip 3, and can prevent moisture from entering. However, the coefficient of thermal expansion of the silicone gel 14 is about tooxlo-'/'C.
Therefore, it is desirable to coat the surface of the solder bump 5 thinly.Also, if the interface between the resin coating 11 and the glass substrate 1 is thinly coated with an acrylic resin film 15 having a moisture-proofing effect in advance, glass cracking can be prevented. It can be prevented.
次に、第１０図に示した一実施例装置により、はんだバ
ンプ形状を所望のっづみ型に形成する方法について説明
する。Next, a method of forming a solder bump shape into a desired shape using the apparatus shown in FIG. 10 will be described.
第１０図に示す装置は、ガラス基板１に半導体チップ３
をＣＣＢ法により接合する装置である。The device shown in FIG. 10 has a semiconductor chip 3 on a glass substrate 1.
This is a device that joins materials using the CCB method.
また、ガラス基板１は液晶表示装置の表示素子１６の基
板を兼ねているものの例である。Further, the glass substrate 1 is an example of one that also serves as a substrate for a display element 16 of a liquid crystal display device.
本製法は、ソーダガラス等のガラス基板１は急激に加熱
すると割れる恐れがあり、また液晶の表示素子１６等に
対する熱影響を軽減するため、半導体チップ３を予熱し
た後、ガラス基板１を透過させて赤外線をはんだバンプ
５に一定時間照射して溶融させ、そして半導体チップ３
とガラス基板ｌの間隔を引き伸して、はんだバンプ５の
形状を所望形状に形成しようとすることにある。In this manufacturing method, the glass substrate 1 made of soda glass or the like may break if heated rapidly, and in order to reduce the heat effect on the liquid crystal display element 16, etc., the semiconductor chip 3 is preheated, and then the glass substrate 1 is allowed to pass through the glass substrate 1. The solder bumps 5 are irradiated with infrared rays for a certain period of time to melt them, and then the semiconductor chip 3 is
The purpose is to extend the distance between the glass substrate 1 and the glass substrate 1 to form the solder bumps 5 into a desired shape.
第１０図に示すように、予め蒸着法等により電極端子面
にはんだが盛られた半導体チップ３を、その電極端子面
を上側にして予熱板２１上に載置する。その半導体チッ
プ３の上にガラス基板１を対向する電極端子の位置を合
わせて載置する。液晶の許容温度は最大１３０℃である
ことから、予熱板２１とは熱的に遮へいするようにして
いる。As shown in FIG. 10, a semiconductor chip 3 whose electrode terminal surfaces are coated with solder in advance by vapor deposition or the like is placed on a preheating plate 21 with its electrode terminal surfaces facing upward. The glass substrate 1 is placed on the semiconductor chip 3 with the opposing electrode terminals aligned. Since the maximum permissible temperature of the liquid crystal is 130° C., it is designed to be thermally shielded from the preheating plate 21.
はんだの組成は耐熱疲労性に優れたＰｂ−５％Ｓｎ（融
点約３１０℃）とし、電極端子上のはんだに予めロジン
系フラックスを塗布した。The composition of the solder was Pb-5% Sn (melting point: about 310° C.), which has excellent thermal fatigue resistance, and rosin-based flux was applied to the solder on the electrode terminals in advance.
接合工程を第１を図に示したはんだバンプ５の実測温度
の時間変化曲線を参照しながら説明する６まず、予熱ヒ
ータ２２により半導体チップ３側から接合部全体を１０
０℃程度に予熱する。しかる後、赤外線ランプ２３によ
りはんだバンプ５部に赤外線を照射する０次に、はんだ
が溶融すると同時にチップ吸引装置２４を開動して、基
板１と半導体チップ３の間隔を所定間隔２５に引伸ばす
。The bonding process will be explained with reference to the time change curve of the measured temperature of the solder bump 5 shown in the first figure.6 First, the entire bonding portion is heated from the semiconductor chip 3 side using the preheating heater 22.
Preheat to around 0℃. Thereafter, the solder bumps 5 are irradiated with infrared rays by the infrared lamp 23, and at the same time as the solder melts, the chip suction device 24 is activated to extend the distance between the substrate 1 and the semiconductor chip 3 to a predetermined distance 25.
これと同時に、赤外線うシブ２３、予熱ヒータ２２を切
り、冷却管２６に冷却水を通して冷却し、はんだバンプ
を凝固させるようにする。なお、はんだの溶融時間は約
１５秒であり、その間にチップ吸引装Ｗ２４が作動して
初期間隔２７から所定間隔２Ｓに引伸ばされる。この引
伸ばしに要する時間は約１秒程度である。また、はんだ
バンプ５の形状は、予熱板２１の突起高さ２８を調整す
ることにより変えることができる。At the same time, the infrared rays 23 and preheater 22 are turned off, and cooling water is passed through the cooling pipe 26 to cool the solder bumps and solidify them. The melting time of the solder is approximately 15 seconds, during which time the chip suction device W24 is operated to extend the initial distance 27 to the predetermined distance 2S. The time required for this stretching is about 1 second. Further, the shape of the solder bump 5 can be changed by adjusting the protrusion height 28 of the preheating plate 21.
なお、はんだ組成は、上記のものに代えて。In addition, the solder composition is replaced with the one mentioned above.
Ｐｂ−６０％Ｓｎ（融点１９１℃）を用いてもよく、そ
の場合低融点でＣＣＢ接合可能であることから、熱影響
を避けたい基板等の場合には好適である。Pb-60%Sn (melting point: 191° C.) may be used, and in that case, CCB bonding is possible at a low melting point, so it is suitable for substrates where it is desired to avoid heat effects.
また、アルミナ基板等のように赤外線を透過しないもの
には適用することはできず、周知の方法（特開昭５０−
１３１６４７号公報）の如く、半導体チップ側から加熱
溶融させるようにしなければならない。In addition, it cannot be applied to materials that do not transmit infrared rays, such as alumina substrates, and the well-known method (Japanese Patent Application Laid-Open No.
131647), the semiconductor chip must be heated and melted from the side.
上述の製法は、上面に電極膜の形成されたガラス基板に
、半導体チップをＣＣＢ接合してなる構造のものに適用
した実施例であるが、以下に述べる構造を有する半導体
装置にも適用可能であり、同様の効果を得ることができ
る。The above manufacturing method is an example in which it is applied to a structure in which a semiconductor chip is CCB bonded to a glass substrate on which an electrode film is formed, but it can also be applied to a semiconductor device having the structure described below. Yes, you can get the same effect.
第１２図に示す実施例は、スルーホールビン型の低膨張
多層プリント基板３工に適用したものであり、同図（Ａ
）は断面構造図、（Ｂ）は半導体チップ３の下面図、（
Ｃ）は多層プリント基板３１の下面図である。図に示す
ように、電極端子数の多い半導体チップ（例えば超ＬＳ
Ｉにあっては端子数が２００個以上にも達する）の場合
、ワイヤボンディング方式で基板の端子と接続すること
は困難である。したがって、ＣＣＢ法による接合構造が
好適であり、上記製法を適用することによって、耐熱疲
労性に優れた信頼性の高いものとすることができる。The embodiment shown in Fig. 12 is applied to three through-hole bottle-type low-expansion multilayer printed circuit boards.
) is a cross-sectional structural diagram, (B) is a bottom view of the semiconductor chip 3, (
C) is a bottom view of the multilayer printed circuit board 31. As shown in the figure, semiconductor chips with a large number of electrode terminals (for example, ultra-LS
In the case of I, the number of terminals reaches 200 or more), it is difficult to connect to the terminals of the board by wire bonding. Therefore, a bonded structure based on the CCB method is suitable, and by applying the above manufacturing method, a highly reliable structure with excellent thermal fatigue resistance can be obtained.
なお、多層プリント基板３１としては、ガラスもしくは
セラミック材料からなる単一基板、又はガラス繊維含有
エポキシ、ガラス繊維含有ポリイミドもしくは高弾性率
高強力繊維を含有するエポキシ又はポリイミド多層基板
等が知られている。As the multilayer printed circuit board 31, a single substrate made of glass or ceramic material, a glass fiber-containing epoxy, a glass fiber-containing polyimide, or an epoxy or polyimide multilayer substrate containing high elastic modulus and high strength fibers are known. .
なお、高弾性率高張力繊維の具体例としては、ケプラー
（米国デュポン社製）が知られている。また、多層セラ
ミック基板等にも適用可能なことは言うまでもない。Note that Kepler (manufactured by DuPont, USA) is known as a specific example of the high elastic modulus and high tensile strength fiber. It goes without saying that it is also applicable to multilayer ceramic substrates and the like.
第１３図は、第１２図図示実施例のものに放熱フィン３
３をはんだ３４により取付けたものである。半導体チッ
プ３の上面にＣｒ −Ｃｕ −Ａ ｕをメタライズし、
はんだ３４ははんだバンプ５よりも一段低融点のはんだ
を用いる０例えば、はんだバンプ５がＰｂ−５％Ｓｎで
あれば、はんだ３４はＰｂ−６０％Ｓｎ、５ｎ−３，５
％Ａｇ（融点約２２０℃）、Ａｕ−２０％Ｓｎ（融点２
８０℃）等を用いる。また、半導体チップ３の発熱量に
よって、要求される放熱特性が緩やかな場合には、第１
４図に示すように、放熱フィン３３を樹脂接着とすれば
、被［樹脂により一度で接合させることができ、製作工
程が簡単化される。FIG. 13 shows the radiation fin 3 of the embodiment shown in FIG.
3 is attached with solder 34. Metallize Cr-Cu-Au on the top surface of the semiconductor chip 3,
For example, if the solder bump 5 is Pb-5%Sn, the solder 34 is Pb-60%Sn, 5n-3,5.
%Ag (melting point approximately 220°C), Au-20%Sn (melting point 2
80°C) etc. In addition, if the required heat dissipation characteristics are moderate depending on the amount of heat generated by the semiconductor chip 3, the first
As shown in FIG. 4, if the heat dissipation fins 33 are bonded with resin, they can be bonded in one step using the resin, which simplifies the manufacturing process.
以上説明したように、本発明によれば、耐衝撃、耐振動
等に優れている樹脂被覆型の効果に加えて。As explained above, according to the present invention, in addition to the effects of the resin-coated type, which is excellent in shock resistance, vibration resistance, etc.
耐熱疲労性が向上されるという効果がある。This has the effect of improving thermal fatigue resistance.
第１図は従来例の断面構造図、第２図（Ａ）。
ＣＢ）はそれぞれ本発明の一実施例の故障率を示す線図
、第３図（Ａ）は被覆厚と応力との関係の一例を示す線
図であり、同図（Ｂ）、（Ｃ）はその説明図、第４図（
Ａ）は半導体チップ幅に対する被覆幅と応力との関係の
一例を示す線図であり、同図（Ｂ）、（ｃ）はその説明
図、第５図（Ａ）〜（Ｄ）ははんだバンプの形状図、第
６図ははんだバンプ形状と熱疲労寿命及び機械的強度と
の関係を示す線図、第７図（Ａ）、（Ｂ）ははんだバン
プの応力分布図、第８図（Ａ）は本発明の一実施例の断
面構造図、同図（Ｂ）は説明図、第９図は本発明の他の
実施例の断面構造図、第１０図は本発明法の適用された
ＣＣＢＣ合接による装置の構成図、第１１図は第１０図
図示実施例の動作説明のためのはんだバンプ温度を示す
線図、第１２図（Ａ）〜（Ｃ）、第１３図及び第１４図
は本発明の他の実施例の構造図ぐある。
１・・・ガラス基板、２・・・電極端子、３・・・半導
体チップ、５・・・はんだバンプ、７，１１・・・被覆
樹脂、１０・・・はんだバンプ、１５・・・アクリル樹
脂膜、３１・・・多層プリント基板。FIG. 1 is a cross-sectional structural diagram of a conventional example, and FIG. 2 (A). CB) is a diagram showing the failure rate of an embodiment of the present invention, FIG. 3(A) is a diagram showing an example of the relationship between coating thickness and stress, and FIG. is its explanatory diagram, Figure 4 (
A) is a diagram showing an example of the relationship between coating width and stress with respect to the semiconductor chip width, FIGS. 5(B) and 5(c) are explanatory diagrams, and FIGS. Figure 6 is a diagram showing the relationship between solder bump shape, thermal fatigue life and mechanical strength, Figures 7 (A) and (B) are stress distribution diagrams of solder bumps, and Figure 8 (A ) is a cross-sectional structural diagram of one embodiment of the present invention, FIG. 9 (B) is an explanatory diagram, FIG. 9 is a cross-sectional structural diagram of another embodiment of the present invention, and FIG. 11 is a diagram showing the solder bump temperature for explaining the operation of the embodiment shown in FIG. 10; FIGS. 12(A) to (C); FIGS. 13 and 14; FIG. is a structural diagram of another embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Glass substrate, 2...Electrode terminal, 3...Semiconductor chip, 5...Solder bump, 7, 11...Coating resin, 10...Solder bump, 15...Acrylic resin Film, 31...Multilayer printed circuit board.
Claims (1)
ン系ゴム１〜２０重量部、ジシアンジアミド０〜１０重
量部、カップリング材０〜２重量部、イミダゾール０．
５〜５重量部からなる樹脂と、全体として２０〜６５体
積％を占める石英粉とからなることを特徴とする樹脂組
成物。1. 100 parts by weight of liquid epoxy resin, 1 to 20 parts by weight of liquid polybutadiene rubber, 0 to 10 parts by weight of dicyandiamide, 0 to 2 parts by weight of coupling agent, 0.
A resin composition characterized by comprising a resin comprising 5 to 5 parts by weight and quartz powder accounting for 20 to 65% by volume as a whole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1325234A JPH0639563B2 (en) | 1989-12-15 | 1989-12-15 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1325234A JPH0639563B2 (en) | 1989-12-15 | 1989-12-15 | Manufacturing method of semiconductor device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58171992A Division JPS6063951A (en) | 1983-09-16 | 1983-09-16 | Semiconductor device and manufacture thereof |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2246822A Division JPH03245558A (en) | 1990-09-17 | 1990-09-17 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0341146A true JPH0341146A (en) | 1991-02-21 |
| JPH0639563B2 JPH0639563B2 (en) | 1994-05-25 |
Family
ID=18174528
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1325234A Expired - Lifetime JPH0639563B2 (en) | 1989-12-15 | 1989-12-15 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0639563B2 (en) |
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| US6130112A (en) * | 1996-03-19 | 2000-10-10 | Hitachi, Ltd. | Semiconductor device |
| WO2000052739A3 (en) * | 1999-03-03 | 2001-01-11 | Intel Corp | A controlled collapse chip connection (c4) integrated circuit package that has a filler which seals an underfill material |
| US6528345B1 (en) | 1999-03-03 | 2003-03-04 | Intel Corporation | Process line for underfilling a controlled collapse |
| JP2005183777A (en) * | 2003-12-22 | 2005-07-07 | Nichia Chem Ind Ltd | Semiconductor device and its manufacturing method |
| US7019410B1 (en) * | 1999-12-21 | 2006-03-28 | Micron Technology, Inc. | Die attach material for TBGA or flexible circuitry |
| US7141448B2 (en) | 1999-03-03 | 2006-11-28 | Intel Corporation | Controlled collapse chip connection (C4) integrated circuit package which has two dissimilar underfill materials |
| US7239068B2 (en) * | 2002-03-29 | 2007-07-03 | Fujitsu Media Devices Limited | Method for mounting surface acoustic wave element and surface acoustic wave device having resin-sealed surface acoustic wave element |
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| JPS5756954A (en) * | 1980-09-22 | 1982-04-05 | Hitachi Ltd | Resin-sealed electronic parts |
| JPS57131223A (en) * | 1981-02-06 | 1982-08-14 | Hitachi Ltd | Resin composition |
| JPS57180626A (en) * | 1981-04-30 | 1982-11-06 | Hitachi Ltd | Thermosetting resin composition |
| JPS5834824A (en) * | 1981-08-26 | 1983-03-01 | Sumitomo Bakelite Co Ltd | Epoxy resin composition and its production |
| JPS5873126A (en) * | 1981-10-27 | 1983-05-02 | Seiko Keiyo Kogyo Kk | Mounting method of semiconductor device |
| JPS58107641A (en) * | 1981-12-21 | 1983-06-27 | Seiko Keiyo Kogyo Kk | Sealing method for semiconductor device |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6130112A (en) * | 1996-03-19 | 2000-10-10 | Hitachi, Ltd. | Semiconductor device |
| WO2000052739A3 (en) * | 1999-03-03 | 2001-01-11 | Intel Corp | A controlled collapse chip connection (c4) integrated circuit package that has a filler which seals an underfill material |
| US6238948B1 (en) | 1999-03-03 | 2001-05-29 | Intel Corporation | Controlled collapse chip connection (C4) integrated circuit package that has a fillet which seals an underfill material |
| US6528345B1 (en) | 1999-03-03 | 2003-03-04 | Intel Corporation | Process line for underfilling a controlled collapse |
| US7141448B2 (en) | 1999-03-03 | 2006-11-28 | Intel Corporation | Controlled collapse chip connection (C4) integrated circuit package which has two dissimilar underfill materials |
| US7019410B1 (en) * | 1999-12-21 | 2006-03-28 | Micron Technology, Inc. | Die attach material for TBGA or flexible circuitry |
| US7239068B2 (en) * | 2002-03-29 | 2007-07-03 | Fujitsu Media Devices Limited | Method for mounting surface acoustic wave element and surface acoustic wave device having resin-sealed surface acoustic wave element |
| JP2005183777A (en) * | 2003-12-22 | 2005-07-07 | Nichia Chem Ind Ltd | Semiconductor device and its manufacturing method |
| JP4496774B2 (en) * | 2003-12-22 | 2010-07-07 | 日亜化学工業株式会社 | Manufacturing method of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0639563B2 (en) | 1994-05-25 |
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