JPH0337112Y2 - - Google Patents
Info
- Publication number
- JPH0337112Y2 JPH0337112Y2 JP5702984U JP5702984U JPH0337112Y2 JP H0337112 Y2 JPH0337112 Y2 JP H0337112Y2 JP 5702984 U JP5702984 U JP 5702984U JP 5702984 U JP5702984 U JP 5702984U JP H0337112 Y2 JPH0337112 Y2 JP H0337112Y2
- Authority
- JP
- Japan
- Prior art keywords
- relay
- relays
- analog signal
- capacitor
- contacts
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003990 capacitor Substances 0.000 claims description 16
- 238000010586 diagram Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000013480 data collection Methods 0.000 description 1
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 1
- 229910052753 mercury Inorganic materials 0.000 description 1
Landscapes
- Arrangements For Transmission Of Measured Signals (AREA)
- Selective Calling Equipment (AREA)
Description
【考案の詳細な説明】
（技術分野）
本考案は多点アナログ信号を順次切換えて入力
するデータ収集回路に係わり、特にアナログ信号
の切換回路に関する。[Detailed Description of the Invention] (Technical Field) The present invention relates to a data acquisition circuit that sequentially switches and inputs multi-point analog signals, and particularly relates to an analog signal switching circuit.
（従来技術と問題点）
従来のデータ収集回路は、第１図に示すよう
に、フライングコンデンサによる走査で行なわれ
ている。各種アナログ信号源１1〜１oの出力端は
２回路のトランスフア接点を持つリレー２1〜２o
の固定接点に接続され、リレー２1〜２oの夫々ト
ランスフア接点の可動接点間にコンデンサ３1〜
３oが接続され、該トランスフア接点の他方の固
定接点は各リレー２1〜２o間で共通接続されてア
ナログ−デイジタル変換器等のアナログ信号入力
回路４の入力にされる。各リレー２1〜２oは図示
状態から順次接点切換え制御がなされ、コンデン
サ３1〜３oの充電電圧として記憶された各アナロ
グ信号源１1〜１oの電圧信号がアナログ信号入力
回路４に順次取込まれる。(Prior Art and Problems) A conventional data acquisition circuit, as shown in FIG. 1, performs scanning using a flying capacitor. The output ends of various analog signal sources 1 1 to 1 o are relays 2 1 to 2 o that have two circuits of transfer contacts.
The capacitors 3 1 to 3 are connected between the movable contacts of the transfer contacts of the relays 2 1 to 2 o , respectively.
3 o is connected, and the other fixed contact of the transfer contacts is commonly connected between each of the relays 2 1 to 2 o and is input to an analog signal input circuit 4 such as an analog-to-digital converter. The relays 2 1 to 2 o are sequentially controlled to switch their contacts from the illustrated state, and the voltage signals from the analog signal sources 1 1 to 1 o stored as the charging voltages of the capacitors 3 1 to 3 o are sent to the analog signal input circuit 4. Imported sequentially.
この従来回路は、コンデンサ３1〜３oに耐ノイ
ズ性向上の機能を持たせ、リレー２1〜２oにデー
タ入力走査時の他入力点からのリーク電流による
信号精度への影響を取除く機能を持たせている。
しかし、従来回路では切換えにリレー２1〜２oと
して高い絶縁性のドライ接点を必要とし、しかも
２回路接点間の動作に時間差を無くして一次二次
間の混触によるトラツキング誤差を無くすことを
必要として高価な２トランスフアの水銀リレーを
必要とした。 In this conventional circuit, the capacitors 3 1 to 3 o have a function to improve noise resistance, and the relays 2 1 to 2 o eliminate the influence on signal accuracy caused by leakage current from other input points during data input scanning. It has a function.
However, in conventional circuits, highly insulating dry contacts are required as relays 21 to 2o for switching, and it is also necessary to eliminate the time difference in the operation between the two circuit contacts to eliminate tracking errors due to cross contact between the primary and secondary circuits. This required an expensive 2-transfer mercury relay.
（考案の目的）
本考案の目的は、通常の低廉なリレーを使つて
従来と同等の信号切換性能を持たせることができ
るデータ収集回路を提供するにある。(Purpose of the invention) The purpose of the invention is to provide a data collection circuit that can have the same signal switching performance as the conventional one using ordinary inexpensive relays.
（考案の概要）
本考案は各アナログ信号源をリレーのメーク接
点を介して共通のコンデンサの電圧として取込
み、各リレーは適当なインターバルを持つて順次
動作させ、各リレーのインターバル期間にコンデ
ンサの電圧をアナログ信号入力回路に取込むこと
を特徴とする。(Summary of the invention) This invention takes in each analog signal source as the voltage of a common capacitor through the make contact of the relay, operates each relay sequentially at appropriate intervals, and voltage of the capacitor during the interval of each relay. is incorporated into the analog signal input circuit.
（実施例）
第２図は本考案の一実施例を示す回路図であ
る。各アナログ信号源１1〜１oの出力端は２回路
のメーク接点を持つリレー５1〜５oの固定接点に
接続され、リレー５1〜５oの可動接点端子は共通
に接続されて１つのフライングコンデンサ６の両
端に接続される。さらに、コンデンサ６の両端は
２回路のメーク接点を持つリレー７を介してアナ
ログ信号入力回路４の入力にされる。リレー５1
〜５oは第３図に示すように走査制御回路（図示
しない）によつて走査周期T0を持つて一定時間
T1だけオン制御され、各リレーのオンから次の
リレーのオンまでにはインターバル期間Txが設
けられる。リレー７は各リレー５1〜５oのオフ制
御の都度かつインターバル期間Tx内で１回オン
制御される。このリレー７は各リレー５1〜５oの
ブレーク接点からタイミング信号を得るか、又は
走査制御回路で発生する各リレー５1〜５oの制御
クロツクからタイミング信号を得て制御される。(Embodiment) FIG. 2 is a circuit diagram showing an embodiment of the present invention. The output ends of each analog signal source 11 to 1o are connected to the fixed contacts of relays 51 to 5o , which have two circuits of make contacts, and the movable contact terminals of the relays 51 to 5o are connected in common. It is connected to both ends of two flying capacitors 6. Further, both ends of the capacitor 6 are input to the analog signal input circuit 4 via a relay 7 having two circuits of make contacts. relay 5 1
~5 o is a constant time period with a scanning period T 0 by a scanning control circuit (not shown) as shown in Fig. 3.
The ON control is performed for T1 , and an interval period Tx is provided from when each relay is turned on to when the next relay is turned on. The relay 7 is controlled to be turned on once each time each of the relays 5 1 to 5 o is turned off and within the interval period Tx. This relay 7 is controlled by obtaining a timing signal from the break contact of each relay 5 1 -5 o or by obtaining a timing signal from a control clock of each relay 5 1 -5 o generated in the scanning control circuit.
こうした構成により、リレー５1〜５oの順次オ
ン動作で各信号源１1〜１oのデータが逐次コンデ
ンサ６の充電電圧として記憶され当該リレー５1
〜５oのオフ動作の都度該コンデンサ６の電圧が
リレー７を通して入力回路４に読込まれる。この
とき、リレー５1〜５oとリレー７とは排他的オン
動作であり、これにより信号源１1〜１o（一次）
と入力回路４（二次）との間の絶縁が確保されリ
レー５1〜５o，７に必ずしもドライコンタクトを
必要としない。また、リレー接点動作のバラツキ
も一次、二次間及び一次間で何ら影響しない。 With this configuration, when the relays 5 1 to 5 o are sequentially turned on, the data of each signal source 1 1 to 1 o is sequentially stored as the charging voltage of the capacitor 6, and the relay 5 1 to 5 o is sequentially turned on.
The voltage of the capacitor 6 is read into the input circuit 4 through the relay 7 each time the OFF operation is performed. At this time, relays 5 1 to 5 o and relay 7 are in exclusive ON operation, which causes signal sources 1 1 to 1 o (primary)
Insulation between the input circuit 4 and the input circuit 4 (secondary) is ensured, and the relays 5 1 to 5 o and 7 do not necessarily require dry contacts. Furthermore, variations in relay contact operation do not affect the primary, secondary, or inter-primary.
（考案の効果）
本考案によれば、各アナログ信号源をリレーを
介して共通にコンデンサ電圧として順次取込み、
この信号を該リレーのインターバル期間に第２の
リレーによつて入力回路側に取込むため、従来の
ドライコンタクトを持つリレーを不要にしながら
同等の絶縁、耐リーク、耐ノイズ性能を持たせる
ことができる。また、信号記憶とノイズ除去のた
めのコンデンサは１つで済む。従つて、一般の低
廉なリレーを使つてまた１つのコンデンサを使つ
て多点アナログ信号を信頼性良く取込むことがで
きる。(Effects of the invention) According to the invention, each analog signal source is sequentially taken in as a common capacitor voltage via a relay,
Since this signal is taken into the input circuit side by the second relay during the interval period of the relay, it is possible to have the same insulation, leak resistance, and noise resistance performance while eliminating the need for conventional relays with dry contacts. can. Furthermore, only one capacitor is required for signal storage and noise removal. Therefore, multi-point analog signals can be reliably taken in using general inexpensive relays and one capacitor.
第１図は従来のデータ収集回路、第２図は本考
案の一実施例を示す回路図、第３図は第２図の動
作タイムチヤートである。
１1，１2，１o……アナログ信号源、４……ア
ナログ信号入力回路、５1，５2，５o……リレー、
６……コンデンサ、７……リレー。
FIG. 1 is a conventional data acquisition circuit, FIG. 2 is a circuit diagram showing an embodiment of the present invention, and FIG. 3 is an operation time chart of FIG. 2. 1 1 , 1 2 , 1 o ... Analog signal source, 4 ... Analog signal input circuit, 5 1 , 5 2 , 5 o ... Relay,
6... Capacitor, 7... Relay.
Claims (1)
点を持つて該メーク接点の出力端を共通接続した
多数の第１リレーと、各第１リレーのメーク接点
の共通接続点に設けられるコンデンサと、このコ
ンデンサの充電電圧端にメーク接点を接つて該メ
ーク接点の出力端をアナログ信号入力回路の入力
端に接続する第２リレーと、上記第１リレーを所
定のインターバルを持たせて順次オン動作させ、
かつ各インターバル期間内にその都度上記第２リ
レーをオン動作させる制御手段とを備えたことを
特徴とするデータ収集回路。 a plurality of first relays each having a make contact at each output end of a multi-point analog signal source and having the output ends of the make contacts commonly connected; and a capacitor provided at a common connection point of the make contacts of each of the first relays; A second relay connects a make contact to the charging voltage end of the capacitor and connects the output end of the make contact to the input end of the analog signal input circuit, and the first relay is sequentially turned on at a predetermined interval. ,
and a control means for turning on the second relay each time within each interval period.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5702984U JPS60169989U (en) | 1984-04-18 | 1984-04-18 | data acquisition circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5702984U JPS60169989U (en) | 1984-04-18 | 1984-04-18 | data acquisition circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60169989U JPS60169989U (en) | 1985-11-11 |
| JPH0337112Y2 true JPH0337112Y2 (en) | 1991-08-06 |
Family
ID=30581175
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5702984U Granted JPS60169989U (en) | 1984-04-18 | 1984-04-18 | data acquisition circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60169989U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10609473B2 (en) | 2014-09-30 | 2020-03-31 | Apple Inc. | Audio driver and power supply unit architecture |
| US10652650B2 (en) | 2014-09-30 | 2020-05-12 | Apple Inc. | Loudspeaker with reduced audio coloration caused by reflections from a surface |
| US11256338B2 (en) | 2014-09-30 | 2022-02-22 | Apple Inc. | Voice-controlled electronic device |
-
1984
- 1984-04-18 JP JP5702984U patent/JPS60169989U/en active Granted
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10609473B2 (en) | 2014-09-30 | 2020-03-31 | Apple Inc. | Audio driver and power supply unit architecture |
| US10652650B2 (en) | 2014-09-30 | 2020-05-12 | Apple Inc. | Loudspeaker with reduced audio coloration caused by reflections from a surface |
| US10728652B2 (en) | 2014-09-30 | 2020-07-28 | Apple Inc. | Adaptive array speaker |
| US11256338B2 (en) | 2014-09-30 | 2022-02-22 | Apple Inc. | Voice-controlled electronic device |
| US10834497B2 (en) | 2016-09-23 | 2020-11-10 | Apple Inc. | User interface cooling using audio component |
| US10911863B2 (en) | 2016-09-23 | 2021-02-02 | Apple Inc. | Illuminated user interface architecture |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60169989U (en) | 1985-11-11 |
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