JPH0336731A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0336731A JPH0336731A JP17231989A JP17231989A JPH0336731A JP H0336731 A JPH0336731 A JP H0336731A JP 17231989 A JP17231989 A JP 17231989A JP 17231989 A JP17231989 A JP 17231989A JP H0336731 A JPH0336731 A JP H0336731A
- Authority
- JP
- Japan
- Prior art keywords
- silicon nitride
- wiring
- silicon dioxide
- film
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 26
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 14
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 13
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 abstract description 12
- 238000000034 method Methods 0.000 abstract description 10
- 238000001312 dry etching Methods 0.000 abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 4
- 238000000059 patterning Methods 0.000 abstract description 2
- 238000001259 photo etching Methods 0.000 abstract description 2
- 238000000206 photolithography Methods 0.000 abstract description 2
- 239000012808 vapor phase Substances 0.000 abstract 1
- 238000001947 vapour-phase growth Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 23
- 239000007789 gas Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000003491 array Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010574 gas phase reaction Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は半導体装置の多層配線の形成方法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a method for forming multilayer wiring in a semiconductor device.
［従来の技術］
近年、半導体素子の高集積化に劣るチップサイズの大型
化や、配線長増加にともなう配線抵抗の増大による素子
動作性能の低下などを改善するための配線の多層化が行
にわれている。特にゲートアレイなどではその利点を最
大限に生かすために配線技術が重要であり、相補型ＭＯ
Ｓゲートアレイでは二層配線が、バイボー２．ゲートア
レイでは三層配線が主流となっている。ところがこのよ
うな多層配線′ｇ造をもつ半導体装置においては、第２
図に示すように下層配線２０２と上層配線２０５が導通
をとる部分において上層配線の被覆が悪くなるという問
題を生じる。この傾向は配線の多層化が進む程に顕著に
１１つ、配線抵抗の増大や配線の断線による素子の不良
が引き起こされる。[Prior Art] In recent years, there has been an increase in the number of layers in wiring in order to improve the problems such as the increase in chip size that is inferior to the high integration of semiconductor devices, and the deterioration in device operating performance due to increased wiring resistance due to increased wiring length. It is being said. In particular, wiring technology is important in gate arrays, etc. in order to make the most of their advantages, and complementary MO
In the S gate array, two-layer wiring is bi-bo 2. Three-layer wiring is the mainstream in gate arrays. However, in a semiconductor device with such a multilayer wiring structure, the second
As shown in the figure, a problem arises in that the coverage of the upper layer wiring becomes poor at the portion where the lower layer wiring 202 and the upper layer wiring 205 are electrically connected. This tendency becomes more noticeable as the wiring becomes more multi-layered, causing element failure due to increased wiring resistance and disconnection of the wiring.
［発明が解決しようとする課題］
以上述べてきたように多層の配線をもつ半導体装置にお
いては、導通孔部分での上層配線の被覆が悪くなるとい
う問題を生じる。よって、本発明は導通孔部分での配線
断線等を防ぐことを目的とするものである。[Problems to be Solved by the Invention] As described above, in a semiconductor device having multilayer wiring, a problem arises in that the upper layer wiring does not cover the conductive hole portion. Therefore, an object of the present invention is to prevent wiring breakage and the like at the conduction hole portion.
［課題を解決するための手段］
本発明の半導体装置の製造方法は、シリコン基板上に形
成される少なくとも二層以上の配線構造をもつ半導体装
置において、下層の配線パターンを形成した後に前記下
層の配線パターンを含む基板表面に二酸化シリコン膜を
形成する工程、前記二酸化シリコン膜を含む基板表面に
窒化シリコン膜を形成する工程、前記二酸化シリコン膜
と前記窒化シリコン膜よりなる絶縁層に対し、前記下層
の配線と、前記絶縁層を介しより上層に形成される配線
層との間に導通をとるために選択的に開孔部を形成する
工程を有し、前記絶縁層の開孔の際に二酸化シリコンと
窒化シリコンに対し二りチングＶ−）が異なるエツチン
グ条件を用いることを特徴とする。[Means for Solving the Problems] The method for manufacturing a semiconductor device of the present invention provides a semiconductor device having a wiring structure of at least two layers formed on a silicon substrate, after forming a wiring pattern of the lower layer. a step of forming a silicon dioxide film on the surface of the substrate including the wiring pattern; a step of forming a silicon nitride film on the surface of the substrate including the silicon dioxide film; selectively forming an opening in order to establish conduction between the wiring and a wiring layer formed in an upper layer via the insulating layer; The double etching (V-) is characterized by using different etching conditions for silicon and silicon nitride.
［実施例］
第１図（α）〜（Ｃ）に本発明の半導体装置の製造方法
による一実施例の工程断面図を示す。[Example] FIGS. 1(α) to (C) show process cross-sectional views of an example of the method for manufacturing a semiconductor device of the present invention.
本発明の実施例における製造方法を用いた半導体装置は
、基本的には第１図（ｃ）に示す構造をしている。A semiconductor device manufactured using the manufacturing method according to the embodiment of the present invention basically has the structure shown in FIG. 1(c).
１０１は半導体基板、１０２は下層の金属配線１０３は
二酸化シリコン［ｉＪ、１０４は窒化シリコン膜、１０
６は上層の金属配線、１０７はパッシヘーシ菖ン族テあ
り、１０５はフォトレジストである。101 is a semiconductor substrate, 102 is a lower layer metal wiring 103 made of silicon dioxide [iJ, 104 is a silicon nitride film, 10
6 is an upper layer metal wiring, 107 is a passivation layer, and 105 is a photoresist.
以下、詳細に説明する。This will be explained in detail below.
半導体基板１０１上の下層の金属１０２をフォト・エツ
チング法によりバターニングした後、二ｔｌＮＢシ＋）
−ｙン膜１ｏ ３ヲ４ ｏ ｏ ｏ 〜６ｏ ｏ ｏ
ｉ程度にモノシラン（ｓｉａ４）と酸素（０，）等との
気相反応によって形成する。さらに窒化シリコン膜１０
４をプラズマ気相成長法により２０００〜４０００Ｘ程
度形成する。次にポジ型フォトレジストを前記窒化シリ
コン膜上に８０００〜２゜０００Ｘ程度塗布しフォトリ
ングラフ法により選択的に開口部を設ける。（第１図（
α）） 次にエツチングガスにＯＦ４．０．を用いドラ
イエツチングにより窒化シリコン膜１０４および二酸化
シリコン膜１０３をエツチングする。このドライエツチ
ングにおいてエンチングガスの組成比、圧力などを変え
ることにより窒化シリコン膜のエツチング速度を二酸化
シリコン膜に対し２〜８倍程度に制御することができる
。この選択比を利用したドライエツチングによれば第１
図（ｂ）に示すように開口部の側壁に順テーパーをもっ
導通孔が形成され、第１図（ｃ）に示すように下層の金
属配線１０２との導通部において上層の金属配線１０６
の被覆性が第２図に示す従来方法のものに比べ著しく向
上していることがわかる。After patterning the lower metal layer 102 on the semiconductor substrate 101 by photo-etching,
-yin membrane 1o 3wo 4o o o ~6o o o
It is formed by a gas phase reaction between monosilane (SIA4) and oxygen (0,), etc. Furthermore, the silicon nitride film 10
4 is formed by plasma vapor phase epitaxy at about 2000 to 4000X. Next, a positive type photoresist is coated on the silicon nitride film at a thickness of about 8000 to 2.000×, and openings are selectively formed using a photolithography method. (Figure 1 (
α)) Next, apply etching gas to OF4.0. The silicon nitride film 104 and the silicon dioxide film 103 are etched by dry etching. In this dry etching, the etching rate of the silicon nitride film can be controlled to be about 2 to 8 times that of the silicon dioxide film by changing the composition ratio, pressure, etc. of the etching gas. According to dry etching using this selectivity, the first
As shown in FIG. 1(b), a conductive hole with a forward taper is formed in the side wall of the opening, and as shown in FIG.
It can be seen that the coverage is significantly improved compared to that of the conventional method shown in FIG.
以上は本発明の一実施例であり、エツチングガスについ
てはここに述べたｏｐ、、ｏ、の他にｙｙ、、Ｏｌ、の
組合せ、又はＯＦ、、Ｈ，の組合せなどを用いることあ
るいは複数ステップによるエツチングにより下層の金属
配線の材質に適した条件や適正なエツチング速度の選択
比が実現できる。また、ここに述べた２層の金属配線４
ｄ造だけでなく３層以上の多層配線構造をもつ半導体装
置においても同様の効果が得られる。The above is one embodiment of the present invention, and as for the etching gas, in addition to the etching gases described here, a combination of yy, ,Ol, or a combination of OF, ,H, etc. may be used, or a plurality of steps may be used. Etching can achieve conditions suitable for the material of the underlying metal wiring and an appropriate etching rate selection ratio. In addition, the two-layer metal wiring 4 described here
Similar effects can be obtained not only in semiconductor devices having a d-structure but also in semiconductor devices having a multilayer wiring structure of three or more layers.
［発明の効果］
以上述べた本発明の半導体装置の製造方法によれば、少
なくとも２層以上の金属配線構造をもつ半導体装置にお
いて上層の金属配線と下層の金属配線が導通する部分で
の上層の金属配線層の被覆性が著しく向上し、金属配線
の断線や配線抵抗の増大などの問題を解決することがで
きる。さらに上層の金属配線の上に形成される層間膜あ
るいはオーバーコート膜の被覆性も向上される。[Effects of the Invention] According to the method for manufacturing a semiconductor device of the present invention described above, in a semiconductor device having a metal wiring structure of at least two layers, the upper layer is The coverage of the metal wiring layer is significantly improved, and problems such as disconnection of the metal wiring and increase in wiring resistance can be solved. Furthermore, the coverage of the interlayer film or overcoat film formed on the upper layer metal wiring is also improved.
第１図Ｃ（Ｌ）〜＜ｃ＞は本発明の半導体装置の製造方
法による一実施例の工程断面図。
第２図は従来の製造方法の構造断面図。
１０１．２０１・・・・・・半導体基板１０２．２０２
・・・・・・下層金属配線１０３．２０３・・・・・・
二酸化シリコン膜１０４ °°°・°゛窒窒化シ
リコ模膜１０５ ・・・・・・ポジ型フォトレジ
ス１０６．２０６・・・・・・上層金属配線層１０７．
２０７・・・・・・オーバーコート膜ト
以
上FIGS. 1C(L) to <c> are process cross-sectional views of an embodiment of the semiconductor device manufacturing method of the present invention. FIG. 2 is a cross-sectional view of the structure of a conventional manufacturing method. 101.201...Semiconductor substrate 102.202
...Lower metal wiring 103.203...
Silicon dioxide film 104 °°°・°゛Silicon nitride film 105 . . . Positive photoresist 106. 206 . . . Upper metal wiring layer 107.
207... Overcoat film or more
Claims (1)
て、下層の配線パターンを形成した後に前記下層の配線
パターンを含む基板表面に二酸化シリコン膜を形成する
工程、前記二酸化シリコン膜を含む基板表面に窒化シリ
コン膜を形成する工程、前記二酸化シリコン膜および前
記窒化シリコン膜よりなる絶縁層に対し、前記下層の配
線と、前記絶縁層を介しより上層に形成される配線層と
の間に導通をとるために選択的に開孔部を形成する工程
を有し、前記絶縁層の開孔の際に二酸化シリコンと窒化
シリコンに対しエッッングレートが異なるエッチング条
件を用いることを特徴とする半導体装置の製造方法。In a semiconductor device having a wiring structure of at least two or more layers, a step of forming a silicon dioxide film on a substrate surface including the lower layer wiring pattern after forming a lower layer wiring pattern; a step of forming a film, in order to establish conduction between the lower layer wiring and the wiring layer formed in the upper layer via the insulating layer with respect to the insulating layer made of the silicon dioxide film and the silicon nitride film; 1. A method of manufacturing a semiconductor device, comprising the step of selectively forming an opening in the insulating layer, and using etching conditions with different etching rates for silicon dioxide and silicon nitride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17231989A JPH0336731A (en) | 1989-07-04 | 1989-07-04 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17231989A JPH0336731A (en) | 1989-07-04 | 1989-07-04 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0336731A true JPH0336731A (en) | 1991-02-18 |
Family
ID=15939709
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17231989A Pending JPH0336731A (en) | 1989-07-04 | 1989-07-04 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0336731A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9624040B2 (en) | 2010-08-25 | 2017-04-18 | Hewlett-Packard Development Company, L.P. | Substrate support |
-
1989
- 1989-07-04 JP JP17231989A patent/JPH0336731A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9624040B2 (en) | 2010-08-25 | 2017-04-18 | Hewlett-Packard Development Company, L.P. | Substrate support |
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