JPH0336151U - - Google Patents
Info
- Publication number
- JPH0336151U JPH0336151U JP9691989U JP9691989U JPH0336151U JP H0336151 U JPH0336151 U JP H0336151U JP 9691989 U JP9691989 U JP 9691989U JP 9691989 U JP9691989 U JP 9691989U JP H0336151 U JPH0336151 U JP H0336151U
- Authority
- JP
- Japan
- Prior art keywords
- mounting portion
- length
- chip mounting
- lead frame
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83194—Lateral distribution of the layer connectors
Landscapes
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第1図は本考案のリードフレームを使用した半
導体装置の模式断面図、第2図は従来のリードフ
レームを使用した半導体装置の模式断面図である
。 図中、1……リードフレーム、1A,1B……
チツプ搭載部、2……半導体チツプ、3……導電
性接着剤、3a,3b……はみ出し、4……ワイ
ヤである。
導体装置の模式断面図、第2図は従来のリードフ
レームを使用した半導体装置の模式断面図である
。 図中、1……リードフレーム、1A,1B……
チツプ搭載部、2……半導体チツプ、3……導電
性接着剤、3a,3b……はみ出し、4……ワイ
ヤである。
Claims (1)
- チツプ搭載部1Aの上面が周囲部分より突出し
ており、且つ該チツプ搭載部1Aの各辺の長さが
搭載する半導体チツプ2の対応する各辺の長さよ
り小であることを特徴とするリードフレーム。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9691989U JPH0336151U (ja) | 1989-08-19 | 1989-08-19 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9691989U JPH0336151U (ja) | 1989-08-19 | 1989-08-19 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0336151U true JPH0336151U (ja) | 1991-04-09 |
Family
ID=31646092
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9691989U Pending JPH0336151U (ja) | 1989-08-19 | 1989-08-19 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0336151U (ja) |
-
1989
- 1989-08-19 JP JP9691989U patent/JPH0336151U/ja active Pending