JPH0334473A - Manufacture of avalanche photodiode - Google Patents
Manufacture of avalanche photodiodeInfo
- Publication number
- JPH0334473A JPH0334473A JP1167048A JP16704889A JPH0334473A JP H0334473 A JPH0334473 A JP H0334473A JP 1167048 A JP1167048 A JP 1167048A JP 16704889 A JP16704889 A JP 16704889A JP H0334473 A JPH0334473 A JP H0334473A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- inp
- high concentration
- junction
- light
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 238000000034 method Methods 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 230000031700 light absorption Effects 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 6
- 238000000927 vapour-phase epitaxy Methods 0.000 claims description 6
- 240000002329 Inga feuillei Species 0.000 claims 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 abstract description 11
- 238000009792 diffusion process Methods 0.000 abstract description 4
- 238000005468 ion implantation Methods 0.000 abstract description 3
- 230000005684 electric field Effects 0.000 description 10
- 238000009826 distribution Methods 0.000 description 5
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
Landscapes
- Light Receiving Elements (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
本発明は、アバランシェ・フォトダイオードの製造方法
に関し、
有機金属気相成長法を用いて、埋め込み成長を行なわず
に、増倍領域幅を高精度で規定することができるプレー
ナ型のアバランシェ・フォトダイオードの製造方法を提
供することを目的とし、ＩｎＰ基板上に、ＩｎＰと格子
整合したＩｎＧａＡｓ層およびＩｎＧａＡｓＰ層の少な
くとも一層から成る光吸収層と、この光吸収層上のＩｎ
Ｐ増倍層とを有し、前記増倍層を含む受光部をガードリ
ング部が取り囲んだ構造を有するアバランシェ・フォト
ダイオードの製造方法において、有機金属気相成長法に
よりＩｎＰ基板上にＩｎＧａＡｓ層およびＩｎＧａＡｓ
Ｐ層の少なくとも一層とＩｎＰ層とを順次積層し、この
ＩｎＰ層成長時に濃度の低いｎ−ＩｎＰ層中に濃度の高
いＩｎＰ層を形成し、受光部のｐｎ接合位置は前記濃度
の高い層の内部または上方に形成し、ガードリング部の
ｐｎ接合位置は前記濃度の高い層の下端または下方に形
成するように構成する。[Detailed Description of the Invention] [Summary] The present invention relates to a method of manufacturing an avalanche photodiode, which uses metal organic vapor phase epitaxy to define the multiplication region width with high precision without performing buried growth. The purpose of the present invention is to provide a method for manufacturing a planar type avalanche photodiode that can be used for manufacturing a planar type avalanche photodiode. In on the layer
In the method for manufacturing an avalanche photodiode having a structure in which a guard ring part surrounds a light-receiving part including the multiplication layer, an InGaAs layer and an InGaAs layer are formed on an InP substrate by metal organic vapor phase epitaxy. InGaAs
At least one P layer and an InP layer are sequentially laminated, and during the growth of this InP layer, a high concentration InP layer is formed in the low concentration n-InP layer, and the pn junction position of the light receiving part is located at the position of the high concentration layer. The pn junction position of the guard ring portion is formed at the lower end of or below the high concentration layer.
本発明は、アバランシェ・フォトダイオード、特に、波
長１１Ｍ帯を使用する光通信システムにおける受信器の
受光素子として好適なアバランシェ・フォトダイオード
の製造方法に関する。The present invention relates to an avalanche photodiode, and more particularly, to a method of manufacturing an avalanche photodiode suitable as a light receiving element of a receiver in an optical communication system using the 11M wavelength band.
近年の光通信システムの大容量化にともない、システム
に用いられる光半導体素子の高性能化が要求されている
。アバランシェ・フォトダイオード（ＡＰＤ） は素子
内部で増幅機能を有し、高感度受信器を構成する素子と
して最適であり、大容量化に対応するため超高速ＡＰＤ
の検討がなされている。超高速化のためには素子を構成
する半導体結晶の濃度、厚さを非常に精密に制御する必
要がある。また信頼性の高い素子を作製するためには良
好なガードリング構造を有するプレーナ型のＡＰＤとす
る必要がある。2. Description of the Related Art As the capacity of optical communication systems has increased in recent years, there has been a demand for higher performance of optical semiconductor elements used in the systems. Avalanche photodiodes (APDs) have an amplification function inside the element and are ideal as elements for constructing high-sensitivity receivers.
are being considered. In order to achieve ultrahigh speed, it is necessary to control the concentration and thickness of the semiconductor crystals that make up the device very precisely. Further, in order to manufacture a highly reliable device, it is necessary to use a planar type APD having a good guard ring structure.
従来ＡＰＤは液相エピタキシャル法（ＬＰＥ法）で作製
され、ＬＰＥ法の利点である埋め込み成長技術を生かし
た構造が実現されている。第３図に従来構造のＡＰＤの
断面図を示した。同図において、ｎ＝−ＩｎＰ基板３１
（基板面は（１１１） Ａ面）、ｎ−ＩｎＰバッファ
ー層３２、ｎ −１ｎＧａＡｓ光吸収層３３、ｎ−Ｉｎ
ＧａＡｓＰ層３４、メルトバック時ニ残留させたｎ−Ｉ
ｎＰ増倍層３５、ｎ−−ＩｎＰ層３６、ｐ−ＩｎＰ層３
８、ｐ＝−ＩｎＰ層３９ 、ＡｕＺｎのｐ側電極４０
、ＡｕＧｅのｎ側電極４１ 、Ｓｉｎ、保護膜４２、再
成長界面４３、受光部Ａおよびガードリング部Ｂを示し
た。この構造では受光部で均一な増倍を起こさせるため
、受光部のみに濃度の高い（ｎ＝２〜３ ＸＩＯ”ａｍ
−”） ｎ−ＩｎＰ層を埋め込み、ガードリング部は低
濃度（ｎ＝５×１０１５ｃＩ］］−３）としである。ま
た、接合を形成するｐ領域を受光部はＣｄ拡散による階
段接合、ガードリング部をＢｅイオン打込みによる傾斜
型接合としてプレーナ型としている。ＬＰＥ法では光吸
収層のＩｎＧａＡｓ上に増倍層ＩｎＰを成長させるため
基板として［ｎＰの（１１１） Ａ面を用い、かつＩｎ
ＧａＡｓとＩｎＰの間に中間組成のＩｎＧａＡｓＰが挿
入されている。Conventionally, APDs have been fabricated by a liquid phase epitaxial method (LPE method), and a structure that takes advantage of buried growth technology, which is an advantage of the LPE method, has been realized. FIG. 3 shows a cross-sectional view of an APD with a conventional structure. In the same figure, n=-InP substrate 31
(Substrate surface is (111) A side), n-InP buffer layer 32, n-1nGaAs light absorption layer 33, n-InP
GaAsP layer 34, n-I remaining during meltback
nP multiplication layer 35, n--InP layer 36, p-InP layer 3
8, p=-InP layer 39, AuZn p-side electrode 40
, an n-side electrode 41 of AuGe, a protective film 42 of Sin, a regrowth interface 43, a light receiving part A, and a guard ring part B. In this structure, in order to cause uniform multiplication in the light receiving part, a high concentration is applied only to the light receiving part (n = 2 to 3 XIO"am
-'') An n-InP layer is embedded, and the guard ring part is a low concentration (n = 5 x 1015 cI] -3).In addition, the p region forming the junction is made of a step junction by Cd diffusion, and the guard ring part is a step junction by Cd diffusion. The ring part is made into a planar type as a sloped junction by Be ion implantation.In the LPE method, in order to grow the InP multiplication layer on the InGaAs light absorption layer, the (111) A plane of [nP is used as the substrate, and InGaAs is used as the substrate.
InGaAsP of intermediate composition is inserted between GaAs and InP.
高速化を実現するためには増倍領域の幅Ｗを０．２±０
．Ｏｌ−程度の精度で実現する必要がある。In order to achieve high speed, the width W of the multiplication area should be set to 0.2±0.
．． It is necessary to realize this with an accuracy on the order of Ol-.
第３図の構造では幅Ｗは増倍層厚さｄの中で濃度で規定
されるが、ＬＰＥ法では濃度の精度は±２０％程度であ
る上、厚さの制御性も±０．１４程度であり、高速化に
必要な精度が得られない。この問題を解決するため、制
御性に優れた有機金属気相成長法（ＭＯＶＰＢ法）を用
いることが有力な手段と考えられる。しかしながら、Ｍ
ＯＶＰＢ法では埋め込み成長時の再成長界面を良好にす
ることが困難であり（ＬＰＥ法ではメルトバック法を用
いて埋め込み成長直前にわずかに再成長界面をけずりと
り清浄な表面としている）、第３図の構造をそのまま適
用して低暗電流で良好なプレーナ型ＡＰＤを製造するこ
とはできない。In the structure shown in Fig. 3, the width W is defined by the concentration within the multiplication layer thickness d, but in the LPE method, the accuracy of the concentration is about ±20%, and the controllability of the thickness is also ±0.14%. The accuracy required for speeding up cannot be obtained. In order to solve this problem, the use of metal organic vapor phase epitaxy (MOVPB method), which has excellent controllability, is considered to be an effective means. However, M
In the OVPB method, it is difficult to make the regrowth interface good during buried growth (in the LPE method, the melt-back method is used to slightly scrape off the regrowth interface just before buried growth to create a clean surface). It is not possible to manufacture a good planar APD with low dark current by applying the structure shown in the figure as is.
本発明は、有機金属気相成長法を用いて、埋め込み成長
を行なわずに、増倍領域幅を高精度で規定することがで
きるプレーナ型のアバランシェ・フォトダイオードの製
造方法を提供することを目的とする。An object of the present invention is to provide a method for manufacturing a planar type avalanche photodiode in which the width of the multiplication region can be defined with high precision using a metal organic vapor phase epitaxy method without performing buried growth. shall be.
上記の目的は、本発明によれば、ＩｎＰ基板上に、Ｉｎ
Ｐと格子整合したＩｎＧａＡｓ層またはＩｎＧａＡｓＰ
層から成る光吸収層と、この光吸収層上のＩｎＰ増倍層
とを有し、前記増倍層を含む受光部をガードリング部が
取り囲んだ構造を有するアバランシェ・フォトダイオー
ドの製造方法において、有機金属気相成長法により前記
ＩｎＰ基板上に前記ＩｎＧａＡｓ層およびＩｎＧａＡｓ
Ｐ層から成る光吸収層と前記ＩｎＰ増倍層とを１＠次積
層し、このｌｎＰ増倍層成長時に濃度の低いｎ−ＩｎＰ
層中に濃度の高いＩｎＰ層を形成し、受光部のｐｎ接合
位置は前記濃度の高い層の内部または上方に形威し、ガ
ードリング部のｐｎ接合位置は前記濃度の高い層の下端
または下方に形成することを特徴とするアバランシェ・
フォトダイオードの製造方法によって遠戚される。According to the present invention, the above object is achieved by forming an InP substrate on an InP substrate.
InGaAs layer or InGaAsP lattice matched to P
In a method for manufacturing an avalanche photodiode, the avalanche photodiode has a structure in which a light-absorbing layer consisting of a layer, an InP multiplication layer on the light-absorption layer, and a guard ring part surrounds a light-receiving part including the multiplication layer, The InGaAs layer and the InGaAs layer are formed on the InP substrate by metal organic vapor phase epitaxy.
A light absorption layer consisting of a P layer and the InP multiplication layer are laminated in the first order, and during the growth of this InP multiplication layer, n-InP with a low concentration is added.
A high concentration InP layer is formed in the layer, the pn junction position of the light receiving part is formed inside or above the high concentration layer, and the pn junction position of the guard ring part is at the bottom end or below the high concentration layer. an avalanche characterized by the formation of
It is distantly related to the method of manufacturing photodiodes.
本発明の方法は、１回の成長でブレーナ型ＡＰＤを実現
できるという利点をも有する。The method of the present invention also has the advantage that a Brehner-type APD can be realized in one growth.
増倍領域幅はアバランシェ・ブレイクダウンを起す電界
値を有する領域幅として定義される。従って増倍領域幅
を明確に規定するためには低濃度領域に非常に薄い高濃
度層を形成しそこで大きな電界降下を実現し、そことｐ
ｎ接合端との距離で決定すればよい。第４図にその概念
図を示す。これらの分布はＭＯＶＰＥ法により十分作製
可能である。The multiplication region width is defined as the region width having an electric field value that causes avalanche breakdown. Therefore, in order to clearly define the width of the multiplication region, a very thin high concentration layer is formed in the low concentration region, a large electric field drop is achieved there, and p
It may be determined based on the distance to the n-junction end. Figure 4 shows its conceptual diagram. These distributions can be sufficiently produced by the MOVPE method.
この構造を作製後ガードリング部ではスパイクドープ層
までｐ領域としてプレーナ構造を作製する。After this structure is fabricated, a planar structure is fabricated with the guard ring portion as a p region up to the spike doped layer.
以下に、実施例により本発明を更に詳しく説明する。The present invention will be explained in more detail below with reference to Examples.
本発明にしたがって、第１図に示したブレーナ型のＡＰ
Ｄを製造する手順を説明する。In accordance with the present invention, an AP of the Brehner type shown in FIG.
The procedure for manufacturing D will be explained.
ＭＯＶＰＥ法を用いて（１００） ｎ”−ＩｎＰ基板１
１上にｎ”−ＩｎＰバッファー層１２、ｎ −ＩｎＧａ
Ａｓ光吸収層１３、ｎ −１ｎＧａＡｓＰ層１４、ｎ−
ＩｎＰ層１５、ｎ層−ＩｎＰスパイクド一プ層１６、お
よびｎ −ＩｎＰ層■７を順次積層する。その後受光部
ＡにはＣｄ拡散により最上層ｎ−ＩｎＰ層中の位置Ｌｌ
にｐｎ接合を形成する。ガードリング部はＢｅをイオン
注入により打ち込みｎ”−ＩｎＰスパイクドープ層を除
去する位置Ｌ２にｐｎ接合を形成する。こうすることに
よって、受光部の外にあるガードリング部分の高濃度の
スパイクドープ層を除去することが可能である。その後
ｐ・ｎ層に各々対するＡｕＺｎのｐ側電極２０ 、Ａｕ
Ｇｅのｎ側電極２１、およびＳｉＯ□表面保護膜２２を
つけて完成する。(100) n”-InP substrate 1 using MOVPE method
1, an n”-InP buffer layer 12, an n-InGa
As light absorption layer 13, n −1nGaAsP layer 14, n−
An InP layer 15, an n-InP spiked layer 16, and an n-InP layer 7 are sequentially laminated. After that, the light receiving part A is exposed to the position Ll in the uppermost n-InP layer due to Cd diffusion.
A pn junction is formed. In the guard ring part, Be is implanted by ion implantation to form a pn junction at position L2 where the n''-InP spike doped layer is removed.By doing this, the highly concentrated spike doped layer in the guard ring part outside the light receiving part is removed. Thereafter, p-side electrodes 20 of AuZn and Au
A Ge n-side electrode 21 and a SiO□ surface protective film 22 are attached to complete the process.
本発明では、ＭＯＶＰＥ法を用いているので、増倍領域
１７の幅を±０．００１４程度の精度で規定することが
可能であり、低濃度層１７、高濃度層１６の濃度を±５
％程度の精度で制御できる。In the present invention, since the MOVPE method is used, it is possible to define the width of the multiplication region 17 with an accuracy of approximately ±0.0014, and the concentration of the low concentration layer 17 and high concentration layer 16 can be defined with an accuracy of approximately ±5.
It can be controlled with an accuracy of about %.
すなわち、本発明の方法によれば、受光部では増倍領域
幅を狭い領域に限定可能となり、かつガードリング部Ｂ
ではスパイクドープ層１６がないためｐｎ接合近傍の電
界値は第２図に示したまうに上がらず良好なプレーナ構
造が形成できる。同図中、実線が受光部の電界値、破線
がガードリング部の電界値を示す。すなわち受光部が実
線のようにブレークダウン電界に達したとき、ガードリ
ング部の電界分布は破線のように低電界となる。That is, according to the method of the present invention, the width of the multiplication region can be limited to a narrow region in the light receiving section, and the width of the multiplication region can be limited to a narrow region.
In this case, since there is no spike doped layer 16, the electric field value near the pn junction does not rise as much as shown in FIG. 2, and a good planar structure can be formed. In the figure, the solid line shows the electric field value of the light receiving part, and the broken line shows the electric field value of the guard ring part. That is, when the light receiving part reaches a breakdown electric field as shown by the solid line, the electric field distribution in the guard ring part becomes a low electric field as shown by the broken line.
本発明の方法では、このプレーナ構造を１回の成長で実
現できる。With the method of the present invention, this planar structure can be achieved in one growth.
〔発明の効果〕
本発明によればＭＯＶＰＥ法による１回の成長で良好な
プレーナ構造が実現できるため、高性能ＡＰＤが再限性
良く作製可能となる。[Effects of the Invention] According to the present invention, a good planar structure can be realized by one-time growth using the MOVPE method, so that high-performance APDs can be manufactured with good reproducibility.
第１図は、本発明の一実施例の方法により製造したＡＰ
Ｄの構造の一例を示す断面図、第２図は、本発明の方法
により製造したＡＰＤの受光部（実線〉とガードリング
部（破線〉の電界分布を模式的に示すグラフ、
第３図は、従来の方法により製造した典型的なＡＰＤの
構造を示す断面図、および
第４図（ａ）および（ｂ）は、それぞれ増倍領域を限定
するために用いる濃度分布、およびその場合の電界分布
を模式的に示すグラフである。
１１．３ｌ−ＩｎＰ基板、 １３．３３＝−ＩｎＧａＡ
ｓ光吸収層、１６・・・ｎ” ｉｎＰスパイクドープ層
、１７．３５・−ｎ−４ｎＰ増倍層、
Ａ・・・受光部、 Ｂ・・・ガードリング部。FIG. 1 shows an AP manufactured by the method of one embodiment of the present invention.
FIG. 2 is a cross-sectional view showing an example of the structure of D, and FIG. 3 is a graph schematically showing the electric field distribution in the light receiving part (solid line) and guard ring part (broken line) of the APD manufactured by the method of the present invention. , a cross-sectional view showing the structure of a typical APD manufactured by a conventional method, and FIGS. 4(a) and 4(b) respectively show the concentration distribution used to limit the multiplication region and the electric field distribution in that case. It is a graph schematically showing 11.3l-InP substrate, 13.33=-InGaA
s light absorption layer, 16...n'' inP spike doped layer, 17.35...-n-4nP multiplication layer, A... light receiving section, B... guard ring section.
Claims (1)
ｓ層またはＩｎＧａＡｓＰ層から成る光吸収層と、この
光吸収層上のＩｎＰ増倍層とを有し、前記増倍層を含む
受光部をガードリング部が取り囲んだ構造を有するアバ
ランシェ・フォトダイオードの製造方法において、有機
金属気相成長法により前記ＩｎＰ基板上に前記ＩｎＧａ
Ａｓ層またはＩｎＧａＡｓＰ層から成る光吸収層と前記
ＩｎＰ増倍層とを順次積層し、このＩｎＰ増倍層成長時
に濃度の低いｎ−ＩｎＰ層中に濃度の高いＩｎＰ層を形
成し、受光部のｐｎ接合位置は前記濃度の高い層の内部
または上方に形成し、ガードリング部のｐｎ接合位置は
前記濃度の高い層の下端または下方に形成することを特
徴とするアバランシェ・フォトダイオードの製造方法。1. InGaA lattice matched to InP on InP substrate
An avalanche photodiode comprising a light absorption layer made of an S layer or an InGaAsP layer, and an InP multiplication layer on the light absorption layer, and a guard ring part surrounds a light receiving part including the multiplication layer. In the manufacturing method, the InGa is deposited on the InP substrate by metal organic vapor phase epitaxy.
A light absorption layer consisting of an As layer or an InGaAsP layer and the above-mentioned InP multiplication layer are sequentially laminated, and when the InP multiplication layer is grown, a high concentration InP layer is formed in the low concentration n-InP layer, and the light receiving part is A method for manufacturing an avalanche photodiode, characterized in that a pn junction position is formed inside or above the high concentration layer, and a pn junction position of the guard ring portion is formed at a lower end or below the high concentration layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1167048A JP3055030B2 (en) | 1989-06-30 | 1989-06-30 | Manufacturing method of avalanche photodiode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1167048A JP3055030B2 (en) | 1989-06-30 | 1989-06-30 | Manufacturing method of avalanche photodiode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0334473A true JPH0334473A (en) | 1991-02-14 |
| JP3055030B2 JP3055030B2 (en) | 2000-06-19 |
Family
ID=15842428
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1167048A Expired - Fee Related JP3055030B2 (en) | 1989-06-30 | 1989-06-30 | Manufacturing method of avalanche photodiode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3055030B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5179431A (en) * | 1989-11-20 | 1993-01-12 | Fujitsu Limited | Semiconductor photodetection device |
-
1989
- 1989-06-30 JP JP1167048A patent/JP3055030B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5179431A (en) * | 1989-11-20 | 1993-01-12 | Fujitsu Limited | Semiconductor photodetection device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3055030B2 (en) | 2000-06-19 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |