JPH033416B2 - - Google Patents
Info
- Publication number
- JPH033416B2 JPH033416B2 JP56101657A JP10165781A JPH033416B2 JP H033416 B2 JPH033416 B2 JP H033416B2 JP 56101657 A JP56101657 A JP 56101657A JP 10165781 A JP10165781 A JP 10165781A JP H033416 B2 JPH033416 B2 JP H033416B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- power supply
- telephone
- output
- supply circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000010586 diagram Methods 0.000 description 13
- 238000004891 communication Methods 0.000 description 7
- 101100437155 Gallus gallus AVR2 gene Proteins 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 3
- 101150003970 Avr1 gene Proteins 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 230000004397 blinking Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
Landscapes
- Electronic Switches (AREA)
- Devices For Supply Of Signal Current (AREA)
Description
【発明の詳細な説明】
（発明の技術分野）
本発明は、ボタン電話装置の電源回路に関する
ものであり、特に電源接続又は電源切断時におけ
る制御対象回路のリセツト動作を行うリセツト回
路を備えた電源回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a power supply circuit for a button telephone device, and in particular to a power supply circuit equipped with a reset circuit for resetting a circuit to be controlled when the power is connected or disconnected. It is related to circuits.
（従来技術とその問題点）
リレーやモーターなどを中央処理装置（CPU）
を用いて制御しようとするシステムを考えた場
合、リレーやモーターなどの定格電圧と、CPU
の定格電圧とに差があるために、システム内に電
圧の異なつた複数の電源回路が存在している。従
来この種のシステムのリセツト回路は、電源投入
時に、CPUに供給されている電源の立上がり特
性を利用して、CPUリセツトをかけている。こ
こで、複数の電源の立上がり特性はCPUの電源
のそれとは異なるために、リセツトがかかる前に
勝手な動作をしてしまつたり、初期のリセツトが
うまくかからないといつた欠点があつた。(Conventional technology and its problems) Relays, motors, etc. are controlled by a central processing unit (CPU).
When considering a system that is to be controlled using
Because of the difference in the rated voltage of the power supply, there are multiple power supply circuits with different voltages in the system. Conventionally, the reset circuit of this type of system utilizes the startup characteristics of the power supplied to the CPU to reset the CPU when the power is turned on. However, since the start-up characteristics of multiple power supplies are different from those of the CPU power supply, there were drawbacks such as the power supply operating automatically before being reset, and the initial reset not working properly.
第１図は従来のこの種のシステムのブロツク図
で、第４図ａ、ｂはリセツト回路の具体例であ
る。第１図において、１は電源入力、２は第１の
電源回路、３はその出力、４は第１の電源回路１
の出力３から電源電流の供給をうける第２の電源
回路、５はその出力、６はリセツト回路、７はそ
の出力、８はCPU回路、９，１０はその出力、
１１は第１の電源回路２の出力３を駆動源とする
回路、１２は第２の電源回路４の出力５を駆動源
とする回路である。回路８，１１，１２が制御対
象回路であり、リセツト信号はこの制御対象回路
をリセツト制御するために用いられる。電源が電
源入力１に印加され、第１の電源回路２が立上が
り、その出力３によつて第２の電源回路４が立上
がり、その出力５がリセツト回路６及びCPU回
路８に印加される。リセツト回路６は電源立上が
りのある一定期間CPU回路８にリセツト信号７
を出力する。 FIG. 1 is a block diagram of a conventional system of this type, and FIGS. 4a and 4b are specific examples of reset circuits. In FIG. 1, 1 is the power supply input, 2 is the first power supply circuit, 3 is its output, and 4 is the first power supply circuit 1.
A second power supply circuit receives power supply current from output 3 of the circuit, 5 is its output, 6 is a reset circuit, 7 is its output, 8 is a CPU circuit, 9 and 10 are its outputs,
11 is a circuit whose driving source is the output 3 of the first power supply circuit 2, and 12 is a circuit whose driving source is the output 5 of the second power supply circuit 4. Circuits 8, 11, and 12 are circuits to be controlled, and the reset signal is used to reset control the circuits to be controlled. Power is applied to the power supply input 1, the first power supply circuit 2 is turned on, the second power supply circuit 4 is turned on by its output 3, and its output 5 is applied to the reset circuit 6 and the CPU circuit 8. The reset circuit 6 sends a reset signal 7 to the CPU circuit 8 for a certain period of time when the power is turned on.
Output.
第４図ａ、ｂはリセツト回路６の具体例を特に
詳細に示した回路であつて、１〜７は第１図の１
〜７と同じである。第４図ａは微分特性を利用
し、ｂは積分特性を利用している。ａでは５Ｖの
電源回路４の出力をC1R1で構成される微分回路
で微分し、２個のインバータIC1，IC2と２個の抵
抗R2，R3とで構成されるシユミツト回路に加え
ている。これにより５Ｖの電源出力５の立上がり
時に、出力７に正のリセツトパルスを出力してい
る、ｂはR11とC11とで構成される積分回路の出力
をインバータIC11に加えることにより、５Ｖの電
源出力５の立上がり時に出力７に正のリセツトパ
ルスを出力している。 4a and 4b are circuits showing specific examples of the reset circuit 6 in particular detail, and 1 to 7 are circuits 1 to 7 in FIG.
- Same as 7. Fig. 4a uses differential characteristics, and Fig. 4b uses integral characteristics. In a, the output of the 5V power supply circuit 4 is differentiated by a differentiating circuit composed of C 1 R 1 , and a Schmitt circuit composed of two inverters IC 1 and IC 2 and two resistors R 2 and R 3 is formed. In addition to As a result, when the 5V power supply output 5 rises, a positive reset pulse is output to the output 7 . When the power supply output 5 rises, a positive reset pulse is output to the output 7.
このような構成であるために、以下に述べるよ
うな不都合点が生じた。まず、第２の電源回路４
は、第１の電源回路２によつて駆動されるため
に、電源入力１の瞬断時に動作が不定になる場合
がある。これは出力３と出力５とが時間的にずれ
を持つているためで、瞬断があつた時第１の電源
回路２の出力３は不安定になるが、第２の電源回
路４の出力は安定しているかまたは出力３より遅
れて不安定になる場合がある。このため回路１２
は動作を継続しているのに、回路１１は動作しな
くなつてしまうようなことが起こるからである。 Due to this configuration, the following disadvantages have arisen. First, the second power supply circuit 4
Since it is driven by the first power supply circuit 2, the operation may become unstable when the power supply input 1 is momentarily cut off. This is because the outputs 3 and 5 have a time lag, and when a momentary power outage occurs, the output 3 of the first power supply circuit 2 becomes unstable, but the output of the second power supply circuit 4 is stable or may become unstable later than output 3. For this reason, circuit 12
This is because even though the circuit 11 continues to operate, the circuit 11 may stop operating.
次にリセツト回路６をCPU回路８と同じ電源
で駆動するために、リセツト動作が不完全な場合
が生じる。第４図ａ、ｂはこの種の装置に用いら
れているリセツト回路の例であり、第７図ａ、ｂ
はそれぞれ第４図ａ、ｂの動作説明図である。第
４図ａで説明すると、第７図ａの○イのように時間
t0で５Ｖが立上がり始め、t4で完全になつたとす
ると、C1R1の接続点の電位は○ロのようにt1までは
VPまで立上がり、t3で０Ｖになる微分出力とな
る。シユミツト回路の立下がり側のスレツシユホ
ールド電圧をVTMLとすると、リセツト出力７はt0
から○イと同様に立上がり、微分出力○ロがVTHLと等
しくなつたt2で０Ｖに落ちるような出力○ハとな
る。ここで○ハの電圧はピークでVRとなるが、５
Ｖに達していない。このためCPU回路８のリセ
ツトが不完全となる場合がある。また、５Ｖが立
上がるまでの時間t4が微分定数τ＝C1×R1よも長
い場合、微分出力VPはVTHLを越えない場合が起
こり、リセツト動作ができない場合がある。ま
た、第４図ｂでは、第７図ｂの○イのように時間t0
で５Ｖが立上がり始め、t2で完全になつたとする
と、C1の充電電位は○ロのようになる。このとき
インバータIC11のスレツユホールド電圧をVTHと
すると、この出力７はt0からは○イと同様に立上が
り、○ロがVTHと等しくなつたt1で0Vに落ちるよう
な出力○ハとなる。ここで○ハの電圧はピークでVR
となるが５Ｖには達していないためにCPU回路
８のリセツト動作が不完全となる場合がある。 Next, since the reset circuit 6 is driven by the same power source as the CPU circuit 8, the reset operation may be incomplete. Figures 4a and b are examples of reset circuits used in this type of device, and Figures 7a and b are examples of reset circuits used in this type of device.
are operation explanatory diagrams of FIGS. 4a and 4b, respectively. To explain with Figure 4 a, time is shown as ○A in Figure 7 a.
If 5V starts to rise at t 0 and becomes complete at t 4 , the potential at the connection point of C 1 R 1 will be as shown in ○○ until t 1 .
The differential output rises to V P and becomes 0V at t 3 . If the threshold voltage on the falling side of the Schmitt circuit is V TML , then the reset output 7 is t 0
The output ○C rises from ○A in the same manner as ○A, and drops to 0V at t 2 when the differential output ○B becomes equal to V THL . Here, the voltage of ○C becomes V R at the peak, but 5
V has not been reached. Therefore, the reset of the CPU circuit 8 may be incomplete. Furthermore, if the time t4 until 5V rises is longer than the differential constant τ= C1 × R1 , the differential output V P may not exceed V THL and the reset operation may not be possible. In addition, in Fig. 4b, time t 0
If 5V starts to rise at t2 and becomes complete at t2 , the charging potential of C1 will be as shown in ○ro. At this time, if the threshold voltage of the inverter IC 11 is V TH , then this output 7 will rise from t 0 in the same way as ○A, and fall to 0V at t 1 when ○B becomes equal to V TH . It becomes ha. Here, the voltage of ○ha is V R at the peak
However, since the voltage does not reach 5V, the reset operation of the CPU circuit 8 may be incomplete.
また、近年マイクロコンピユータを主装置の制
御回路とボタン電話機の制御回路に用いたボタン
電話装置が提案されているが、このような複数の
制御系を有するボタン電話装置において電源接続
又は電源切断時に二つの制御系の誤動作が生じる
現象があるが、現在までこれを防止する有効な手
段は提案されていない。 In addition, in recent years, key telephone devices have been proposed that use microcomputers for the control circuit of the main device and the control circuit of the key telephone.However, in such a key telephone device having multiple control systems, when the power is connected or turned off, two Although there is a phenomenon in which malfunctions of control systems occur, no effective means for preventing this has been proposed to date.
（発明の目的）
本発明は、主装置とボタン電話機にそれぞれ個
別の制御回路を有する場合にも電源の切断時の誤
動作を防止するリセツト機能を有せしめたボタン
電話装置の電源回路を提供するものである。(Object of the Invention) The present invention provides a power supply circuit for a button telephone device that has a reset function that prevents malfunctions when the power is turned off even when the main device and the button telephone have separate control circuits. It is.
（発明の構成）
この目的を達成するために、本発明のボタン電
話装置の電源回路は、主装置には、第１の電源回
路と、該第１の電源回路から電源電流の供給をう
けるとともに電源投入時に該第１の電源回路の出
力が安定する時点より早くその出力が安定する第
２の電源回路と、前記第２の電源回路から電源電
流の供給をうける第１の制御対象回路と、前記第
１の電源回路の出力電圧を一方の入力とし他方の
入力を基準電圧として該一方の入力の電圧が該基
準電圧を越えたときに前記第１の制御対象回路へ
のリセツト信号を出力する第１のリセツト回路
と、該リセツト信号に応答して前記第１の電源回
路からボタン電話機への電源電流の供給を一時的
に停止した後再び該電源電流の供給を行う電話機
電流供給回路とを備え、前記ボタン電話機には、
前記電話機電流供給回路から電源電流を供給され
る電話機電源回路と、該電話機電源回路から電源
電流の供給をうける第２の制御対象回路と、該電
話機電源回路から該第２の制御対象回路に電源電
流が供給されたときに該第２の制御対象回路をリ
セツトする第２のリセツト回路とを備えた構成を
とつている。(Structure of the Invention) In order to achieve this object, the power supply circuit of the button telephone device of the present invention includes a main device including a first power supply circuit and a power supply current supplied from the first power supply circuit. a second power supply circuit whose output is stabilized earlier than the point at which the output of the first power supply circuit becomes stable when the power is turned on; a first controlled circuit that receives power supply current from the second power supply circuit; The output voltage of the first power supply circuit is used as one input, the other input is used as a reference voltage, and when the voltage of the one input exceeds the reference voltage, a reset signal is output to the first controlled circuit. a first reset circuit; and a telephone current supply circuit that temporarily stops supplying power current from the first power supply circuit to the button telephone in response to the reset signal and then resumes supplying the power current. The button telephone includes:
a telephone power supply circuit to which power supply current is supplied from the telephone power supply circuit; a second controlled circuit to which power supply current is supplied from the telephone power supply circuit; The second reset circuit resets the second controlled circuit when current is supplied.
以下図面により本発明を詳細に説明する。 The present invention will be explained in detail below with reference to the drawings.
第２図、第３図は本発明に用いる電源回路の具
体例を示すブロツク図で、第５図、第６図及び第
８図は、それぞれ第２図、第３図の具体的な回路
例及び動作説明用波形図である。第２図と第３図
において、１は電源入力、２は第１の電源回路、
３はその出力、４は第１の電源回路２から電源の
供給をうける第２の電源回路、５はその出力、６
はリセツト回路、７はその出力、８はCPU回路、
９，１０はその出力、１１は第１の電源回路２の
出力３を駆動源とする回路、１２は第２の電源回
路４の出力５を駆動源とする回路、１３は基準電
圧源、１４はその出力、１５は電圧比較回路、１
６はその出力、１７は別の電源入力端子、１８は
遅延回路である。リセツト回路６は電圧比較回路
１５とともに第１のリセツト回路を構成する。 2 and 3 are block diagrams showing specific examples of power supply circuits used in the present invention, and FIGS. 5, 6, and 8 are specific circuit examples of FIGS. 2 and 3, respectively. and a waveform diagram for explaining the operation. In Figures 2 and 3, 1 is a power supply input, 2 is a first power supply circuit,
3 is its output, 4 is a second power supply circuit that receives power from the first power supply circuit 2, 5 is its output, 6
is the reset circuit, 7 is its output, 8 is the CPU circuit,
9 and 10 are their outputs, 11 is a circuit whose driving source is the output 3 of the first power supply circuit 2, 12 is a circuit whose driving source is the output 5 of the second power supply circuit 4, 13 is a reference voltage source, and 14 is its output, 15 is the voltage comparison circuit, 1
6 is its output, 17 is another power input terminal, and 18 is a delay circuit. The reset circuit 6 and the voltage comparator circuit 15 constitute a first reset circuit.
第２図の具体例の動作を説明する。電源が電源
入力１に印加され、第１の電源回路２が立上が
り、その出力３により第２の電源回路４が立上が
り、その出力５がCPU回路８に印加され、電圧
比較回路１５で基準電圧源１３の出力１４と比較
され、その差に応じた出力１６を出す。リセツト
回路６は電圧比較回路１５の出力１６に応じて
CPU回路８にリセツト信号７を出力する構成に
なつている。 The operation of the specific example shown in FIG. 2 will be explained. Power is applied to the power supply input 1, the first power supply circuit 2 starts up, the second power supply circuit 4 starts up with its output 3, the output 5 is applied to the CPU circuit 8, and the voltage comparator circuit 15 converts the reference voltage source. The output 13 is compared with the output 14, and an output 16 corresponding to the difference is output. The reset circuit 6 responds to the output 16 of the voltage comparison circuit 15.
The configuration is such that a reset signal 7 is output to the CPU circuit 8.
第５図は第２図のブロツク図の具体的回路例で
あり、第８図はその動作説明用波形図である。ま
ず、電源が電源入力１に印加され、３０Ｖを出力
する第１の電源回路２の出力３が第８図○イのよう
にt0で立上がりt4で安定になるとすれば、５Ｖを
出力する第２の電源回路４の出力５は○ロのように
t0で立上がりt1で安定する。ここでトランジスタ
Q31のエミツタ電位VEとベース電位VBとを比較す
ると、エミツタ電位VEは第１の電源回路２の出
力電圧V1がツエナーダイオードZD31のツエナー
電位Vzを越えれば一定となり
VE＝VZ
となる。ここでベース電流を無視すれば、
VB＝V1×R32／R31＋R32
でるから、トランジスタQ31のベース・エミツタ
間のオン電圧をVBEとすると、
VB＜VBE＋VE
のときトランジスタQ31はオフになつており、リ
レーＴは復旧している。次に
VBVBE＋VE
のときはQ31はオンになり、従つてリレーＴは動
作する。リレーＴの接点ｔは復旧時には図の実線
側にあるから、インバータ回路IC31の入力は
“Ｌ”になつて出力は“Ｈ”になる。Ｔリレーが
動作して点線側に倒れると、R33，C31により形成
された積分回路による一定の時間遅れ後、インバ
ータ回路IC31は反転して“Ｌ”になる。また、Ｔ
リレーが動作状態から復旧すると、コンデンサ
C31の電荷はダイオードD32により急速に放電され
るので、ｔ接点動作とほぼ同時にインバータ回路
IC31の出力は“Ｈ”になる。従つて、リセツト出
力７は○ハのような出力となる。 FIG. 5 shows a specific circuit example of the block diagram of FIG. 2, and FIG. 8 is a waveform diagram for explaining its operation. First, if power is applied to the power supply input 1 and the output 3 of the first power supply circuit 2 which outputs 30V rises at t 0 and stabilizes at t 4 as shown in Figure 8 (○a), it will output 5V. The output 5 of the second power supply circuit 4 is as shown in ○○
It rises at t 0 and stabilizes at t 1 . transistor here
Comparing the emitter potential V E and base potential V B of Q 31 , the emitter potential V E becomes constant if the output voltage V 1 of the first power supply circuit 2 exceeds the Zener potential V z of the Zener diode ZD 31 . = V Z. If we ignore the base current, we get V B = V 1 × R 32 /R 31 + R 32. Therefore, if the on-voltage between the base and emitter of transistor Q 31 is V BE , then V B < V BE + V E When transistor Q 31 is turned off, relay T is restored. Next, when V B V BE +V E , Q 31 turns on, and therefore relay T operates. Since the contact point t of the relay T is on the solid line side in the figure at the time of recovery, the input of the inverter circuit IC 31 becomes "L" and the output becomes "H". When the T relay operates and falls to the dotted line side, after a certain time delay caused by the integrating circuit formed by R 33 and C 31 , the inverter circuit IC 31 is inverted and becomes "L". Also, T
When the relay recovers from operating condition, the capacitor
Since the charge on C 31 is rapidly discharged by diode D 32 , the inverter circuit is activated almost simultaneously with the t-contact operation.
The output of IC 31 becomes "H". Therefore, the reset output 7 becomes an output like ○c.
このような構成であるために、まず電源投入時
のリセツト動作が完全に行われる。すなわち、５
Ｖの出力を出す第２の電源回路４の出力○ロの安定
する時点t1は３０Ｖの出力を出す第１の電源回路
２の出力○イが安定する時点t4よりは早いため、前
記トランジスタQ31がスイツチングする電圧を
VREFとすると、３０Ｖの出力○イがVREFとなる時点
t2をt1＜t2＜t3と設定定することができる。この
ためリセツトパルス７は少なくともt1からt2の間
は5Vを維持し、R33，C31の充電時間の遅れの後
t3で０Ｖになるため、リセツトを完全に行うこと
ができる。次に、電源が瞬断した場合には、第８
図において、t5で３０Ｖの出力○イが下り始めt6で
VREFと等しくなつた時にQ31はオフになるため、
リレーＴが復旧し、前述した様に、リセツトパル
スは“Ｈ”になる。その後３０Ｖがt7で復旧し始
めt8でVREFと等しくなつた時、トランジスタQ31
がオンになり、Ｔリレーが動作するため、リセツ
トパルスはt9で“Ｌ”になる（○ハ′）。このため、
瞬断時には３０Ｖの電源で動作している回路１１
も、５Ｖで動作している回路１２もすべてリセツ
トがかかるので、動作不安定といつた状態は起こ
らない。 Because of this configuration, the reset operation is completely performed when the power is turned on. That is, 5
Since the time t1 at which the output ○B of the second power supply circuit 4 which outputs an output of V is stabilized is earlier than the time t4 when the output ○A of the first power supply circuit 2 which outputs an output of 30V is stabilized, the transistor Q 31 switches voltage
If it is V REF , the point at which the 30V output ○a becomes V REF
t 2 can be set as t 1 < t 2 < t 3 . Therefore, the reset pulse 7 maintains 5V at least from t 1 to t 2 and after the charging time delay of R 33 and C 31 .
Since it becomes 0V at t3 , a complete reset can be performed. Next, in the event of a momentary power outage,
In the figure, the 30V output ○I starts to drop at t 5 and begins to drop at t 6 .
Since Q 31 turns off when it becomes equal to V REF ,
Relay T is restored and the reset pulse becomes "H" as described above. Then, when 30V started to recover at t 7 and became equal to V REF at t 8 , transistor Q 31
is turned on and the T relay operates, so the reset pulse becomes "L" at t9 (○c'). For this reason,
Circuit 11 operating on 30V power supply during momentary power outage
Also, since all the circuits 12 operating at 5V are reset, unstable operation will not occur.
第３図は第２図の基準電圧源１３として第２の
電源回路４の出力５をとつたもので、その具体例
を第６図に示す。その動作は第３図の場合と同様
で、トランジスタQ41のエミツタ電位VEとベー電
位VEとは、
VE＝V2
VB＝V1×R42／R41＋R42＋VD
となる。ただし、VDはダイオードD41の順方向電
圧降下分である。トランジスタQ41は、ベース・
エミツタ間のオン電圧を−VBEとすると、
VB＜VE−VBE
のときオンになり
VBVE−VBE
のときオフになるので、オンのときリセツト回路
６の出力７にはV2の電位が、オフのときは０Ｖ
の電位が現れる。よつて第１図と同様な効果を得
ることができる。また第３図のような構成である
と、基準電圧を別に設ける必要がないため回路が
簡単になるといつた効果もある。 In FIG. 3, the output 5 of the second power supply circuit 4 is used as the reference voltage source 13 in FIG. 2, and a specific example thereof is shown in FIG. Its operation is similar to that shown in Fig. 3, and the emitter potential V E and base potential V E of the transistor Q 41 are V E = V 2 V B = V 1 × R 42 /R 41 + R 42 + V D. . However, V D is the forward voltage drop of the diode D41 . Transistor Q 41 has a base
If the on-voltage between the emitters is -V BE , it turns on when V B < VE - V BE and turns off when V B V E - V BE , so when it is on, the output 7 of the reset circuit 6 The potential of V 2 is 0V when it is off.
A potential appears. Therefore, the same effect as in FIG. 1 can be obtained. Further, the configuration shown in FIG. 3 has the advantage that the circuit can be simplified because there is no need to separately provide a reference voltage.
第９図は以上説明した電源回路を用いた本発明
の一実施例としてのボタン電話装置のブロツク図
であり、MEは主装置、TELは電話機のうちの一
つ、Ｌは通話路、Ｄは電源及びデータ路である。
主装置MEにおいて、COは局線入力端子、COC
は局線回路、IOCは内線回路、RCは着信信号検
出回路、TONEは音源回路、ｌはＬリレーの接
点、POWは電源入力端子、AVR１は第１の電源
回路、CPUは第１の制御対象となる中央処理装
置（制御回路）として動作するCPU回路、Ｔ−
POWは電話機電源供給回路、TRはデータ送受
信回路、BUは停電バツクアツプ電源回路、LR
はＬリレー回路、SDは停電時のＬリレーの自己
保持回路、AVR２は第２の電源回路、RESは第
１のリセツト回路、SWは例えば各入力にモノマ
ルチバイブレータを含み入力の到来後に電話機電
源供給回路Ｔ−POWへの出力を一時的にオフに
した後再送出せしめる制御をするスイツチ回路、
Ｌ−DRIVEはCPU回路CPUの出力によりＬリレ
ーを駆動するドライブ回路、Ｄはダイオードであ
る。電話機TELにおいて、ｐはＰリレーの接点、
HS1，HS2はフツクスイツチ、NETは通話回路、
Ｒは抵抗、AMPは増幅回路、SPはスピーカ、
AVR−Ｔは電話機電源回路、TRはデータ送受信
回路、RESは第２のリセツト回路、Ｐ−DRIVE
は第２の制御対象となるCPU回路CPUの出力に
よりＰリレーを駆動するドライブ回路、PRはＰ
リレー回路、LKは局線ボタン、PKは呼出ボタン
である。 FIG. 9 is a block diagram of a button telephone device as an embodiment of the present invention using the power supply circuit described above, where ME is the main device, TEL is one of the telephones, L is the communication path, and D is the It is a power and data path.
In the main device ME, CO is the station line input terminal, COC
is the office line circuit, IOC is the extension circuit, RC is the incoming signal detection circuit, TONE is the sound source circuit, l is the contact of the L relay, POW is the power input terminal, AVR1 is the first power supply circuit, and CPU is the first control target A CPU circuit that operates as a central processing unit (control circuit), T-
POW is the telephone power supply circuit, TR is the data transmission/reception circuit, BU is the power outage backup power supply circuit, LR
is the L relay circuit, SD is the L relay self-holding circuit during power outage, AVR2 is the second power supply circuit, RES is the first reset circuit, and SW includes a mono multivibrator for each input, for example, and the telephone power supply after the input arrives. A switch circuit that controls the output to the supply circuit T-POW to be temporarily turned off and then re-transmitted;
L-DRIVE is a drive circuit that drives the L relay by the output of the CPU circuit CPU, and D is a diode. In the telephone TEL, p is the contact point of the P relay,
HS 1 and HS 2 are the switch, NET is the communication circuit,
R is a resistor, AMP is an amplifier circuit, SP is a speaker,
AVR-T is the telephone power supply circuit, TR is the data transmission/reception circuit, RES is the second reset circuit, P-DRIVE
is the drive circuit that drives the P relay by the output of the CPU circuit CPU that is the second controlled object, and PR is the P relay.
Relay circuit, LK is the office line button, and PK is the call button.
動作の際に、主装置MEにおいて、電源が電源
入力端子POWに入力されると、第１の電源回路
AVR１が立上がり、第２の電源回路AVR２、Ｌ
リー回路LR、電話機電源供給回路Ｔ−POWに電
源が供給される。第２の電源回路AVR２は第１
のリセツト回路RESとCPU回路CPUに電源を供
給し、これにより第１のリセツト回路RESは第
１の制御対象であるCPU回路CPUをリセツトす
る。リセツト時に、スイツチ回路SWにより、電
話機電源供給回路Ｔ−POWによる電話機電源回
路AVR−Ｔへの電源電流の供給が一時的に停止
した後再送出されるように制御される。このリセ
ツト動作後、CPU回路CPUは自己保持回路SDよ
りＬリレーの動作状態を検知して、Ｌリレーが自
己保持中であれば、Ｌリレーを動作すべく出力を
Ｌ−DRIVEに出す。待機中のＬリレーは動作し
ており、その接点ｌは点線の位置にあり、内線回
路IOCに接続されている。主装置MEと各電話機
TELとの間のデータの授受は、〔CPU回路CPU
→データ送受信回路TR→データ路Ｄ→データ送
受信回路TR→CPU回路CPU〕の経路で双方向で
行われる。電話機TELは電話機電源供給回路Ｔ
−POWから電源が供給されると、電話機電源回
路AVR−Ｔが動作し、第２のリセツト回路RES
により第２の制御対象であるCPU回路CPUをリ
セツトする。待機中のＰリレーは動作しておら
ず、Ｐリレーの接点ｐはフツクスイツチ側にあ
る。ここで電話機TELがオフフツクすれば、ｐ
接点とフツクスイツチHS1を介して通話回路
NETが通話線Ｌに接続され、さらに接点ｌを介
して内線回路IOCに接続される。呼出ボタンPK
を操作することにより、〔CPU回路CPU→ータ送
受信回路TR〕からの呼出情報が前記データ路Ｄ
により伝送され、主装置MEではCPU回路CPU
が音源回路TONEにより呼出音を通話路Ｌに送
出する。被呼電話機（第１図において、電話機
TELは同じものが複数接続されているものの１
つを示しており、呼出電話機と被呼電話とを区別
するために被呼電話機の回路名称に’を付けて表
示する）はCPU回路CPU'が被呼状態を検出し、
ドライブ回路Ｐ−DRIVE'を駆動してＰリレー回
路PR'を動作させるとともに増幅回路AMP'を動
作状態とする。これにより被呼電話機は〔P'リレ
ーの接点p'→抵抗R'→増幅回路AMP'→スピーカ
SP'〕により呼出音が送出される。ここで被呼電
話機TEL'がオフフツクすれば、フツクスイツチ
HS'2によりCPU回路CPU'はP'リレーーを復旧
し、電話回路NET'がフツクスイツチHS'1を介し
て電話回路NET'に接続され、フツクスイツチ
HS'2の情報により主装置のCPU回路CPUは音源
回路TONEを停止するので、内線通話状態とな
る。他の電話機はＰリレーを復旧し、待機状態に
なる。内線通話は双方の電話機がオフフツクすれ
ば待機状態となる。 During operation, when power is input to the power input terminal POW in the main device ME, the first power supply circuit
AVR1 starts up and the second power supply circuit AVR2, L
Power is supplied to the Lee circuit LR and the telephone power supply circuit T-POW. The second power supply circuit AVR2 is
Power is supplied to the reset circuit RES and the CPU circuit CPU, whereby the first reset circuit RES resets the CPU circuit CPU which is the first control target. At the time of reset, the switch circuit SW controls the power supply current from the telephone power supply circuit T-POW to the telephone power supply circuit AVR-T to be temporarily stopped and then to be re-transmitted. After this reset operation, the CPU circuit CPU detects the operating state of the L relay from the self-holding circuit SD, and if the L relay is self-holding, sends an output to the L-DRIVE to operate the L relay. The standby L relay is operating, its contact l is located at the dotted line position, and is connected to the extension circuit IOC. Main device ME and each telephone
Transfer of data to and from TEL is carried out by [CPU circuit
→ data transmitting/receiving circuit TR → data path D → data transmitting/receiving circuit TR → CPU circuit CPU]. Telephone TEL is telephone power supply circuit T
- When power is supplied from POW, the telephone power supply circuit AVR-T operates and the second reset circuit RES
This resets the CPU circuit CPU which is the second control target. The P relay in standby is not operating, and the contact p of the P relay is on the switch side. If the telephone TEL goes off-hook here, p
Call circuit via contacts and switch HS 1
NET is connected to the telephone line L and further connected to the extension circuit IOC via the contact l. call button PK
, the call information from [CPU circuit CPU→data transmitting/receiving circuit TR] is transferred to the data path D.
In the main device ME, the CPU circuit CPU
sends a ringing tone to the communication path L by the tone source circuit TONE. Called telephone (in Figure 1, telephone
TEL is one of the same ones connected multiple times.
(The circuit name of the called telephone is displayed with '' added to distinguish between the calling telephone and the called telephone), the CPU circuit CPU' detects the called state, and
Drive circuit P-DRIVE' is driven to operate P relay circuit PR' and put amplifier circuit AMP' into operation. As a result, the called telephone is connected to [P' relay contact p' → resistor R' → amplifier circuit AMP' → speaker
SP'] sends out a ringing tone. If the called telephone TEL' goes off-hook, the off-hook switch will be activated.
By HS' 2 , the CPU circuit CPU' restores the P' relay, and the telephone circuit NET' is connected to the telephone circuit NET' through the telephone switch HS' 1 , and the telephone circuit NET' is connected to the telephone circuit NET' through the telephone switch HS' 1.
Based on the information from HS' 2 , the CPU circuit of the main device stops the tone generator circuit TONE, and an extension call state is established. The other telephones restore their P relays and go into standby mode. An extension call goes into a standby state when both telephones go off-hook.
局線着信があると、着信検出回路RCが動作す
る。これにより主装置MEのCPU回路CPUは音
源回路TONEを駆動するとともに電話機TELへ
局線着信状態のデータを伝送する。電話機TEL
のCPU回路CPUは、Ｐリレー及び増幅回路AMP
を動作させるので、各電話機TELから局線着信
音が送出される。電話機TELの局線ボタンLKの
操作及びオフフツクにより、電話機TELのCPU
回路CPUはＰリレーと増幅回路AMPを復旧し、
通話回路NETを通話路Ｌへ接続するとともに局
線選択データを主装置MEに伝送する。主装置
MEのCPU回路CPUは音源回路TONEを停止す
るとともにＬリレーを復旧させて、そのｌ接点を
局線回路COC側に向ける。また、オフフツクし
た以外の電話機TELはＰリレーと増幅回路AMP
とも復旧し、待機状態になる。以上の動作により
局線通話状態になる。 When there is an incoming call on the central office line, the incoming call detection circuit RC is activated. As a result, the CPU circuit CPU of the main device ME drives the tone generator circuit TONE and transmits data on the state of incoming calls to the telephone TEL. Telephone TEL
CPU circuit CPU, P relay and amplifier circuit AMP
, the central office line ring tone is sent from each telephone TEL. By operating the central line button LK of the telephone TEL and off-hook, the CPU of the telephone TEL
The circuit CPU restores the P relay and the amplifier circuit AMP,
The communication circuit NET is connected to the communication path L, and the station line selection data is transmitted to the main device ME. Main device
The ME CPU circuit CPU stops the tone source circuit TONE, restores the L relay, and directs its L contact to the office line circuit COC side. In addition, the telephone TEL other than the one that was taken off-hook is connected to the P relay and the amplifier circuit AMP.
Both will recover and go into standby mode. The above operations result in a central office line communication state.
終話はオンフツクにより電話機TELは待機状
態になり、このオンフツク情報により主装置ME
はＬリレーを動作させ、そのｌ接点が内線回路
IOC側に接続され待機状態になる。 When the call ends, the telephone TEL goes into standby mode due to the on-hook, and this on-hook information causes the main device ME to
operates the L relay, and its L contact connects to the extension circuit.
It is connected to the IOC and enters a standby state.
局線発信時の局線選択動作は、電話機TELの
局線ボタンLKの操作及びオフフツクにより、通
話回路NETはフツクスイツチHS1とｐ接点によ
り通話路Ｌに接続される。主装置MEは局線選択
情報によりＬリレーを復旧するので、ｌ接点が通
話路Ｌを局線回路COC側に接続し、局線発信が
可能な状態となる。 In selecting the central line when making a central line call, by operating the central line button LK of the telephone TEL and turning off the hook, the telephone call circuit NET is connected to the telephone line L through the telephone switch HS1 and the p-contact. Since the main device ME restores the L relay based on the office line selection information, the L contact connects the communication path L to the office line circuit COC side, and the state becomes possible for office line transmission.
ボタン電話装置には、ランプ点滅動作、ダイヤ
ル動作、保留動作、転送動作など各種機能動作が
あるが、本発明の効果の説明には不要なので省略
する。 The button telephone device has various functional operations such as a lamp blinking operation, a dialing operation, a holding operation, and a transfer operation, but these are not necessary for explaining the effects of the present invention, so they will be omitted.
（発明の効果）
以上詳細に説明したように、本発明は複数の制
御対象を有するボタン電話装置においても、複数
の電圧を比較して複数のリセツト回路を順次動作
させているので、電源の立上がり、立下がりに時
間差がある場合、あるいは電源の瞬断がある場合
などにおいてリセツトが確実になり、複数の制御
対象に対しても不定動作を防ぐことができるとい
つた利点がある。(Effects of the Invention) As explained in detail above, even in a button telephone device having a plurality of control objects, the present invention compares a plurality of voltages and sequentially operates a plurality of reset circuits. The advantage of this method is that it can be reset reliably even when there is a time lag in the fall, or when there is a momentary power outage, and unstable operation can be prevented even for a plurality of controlled objects.
第１図は従来のこの種の装置のブロツク図、第
２図、第３図は本発明装置に用いる電源回路の具
体例のブロツク図、第４図ａ、第４図ｂは従来の
リセツト回路の具体例を示す回路図、第５図、第
６図は本発明装置に用いる電源回路の具体的な回
路例を示す回路図、第７図ａ、第７図ｂはそれぞ
れ第４図ａ、第４図ｂの具体例の動作説明用波形
図、第８図は第５図の回路例の動作説明用波形
図、第９図は本発明の実施例を示すブロツク図で
ある。
FIG. 1 is a block diagram of a conventional device of this type, FIGS. 2 and 3 are block diagrams of specific examples of power supply circuits used in the device of the present invention, and FIGS. 4a and 4b are conventional reset circuits. 5 and 6 are circuit diagrams showing specific examples of the power supply circuit used in the device of the present invention, and FIGS. 7a and 7b are respectively shown in FIGS. 4a and 7b. FIG. 4b is a waveform diagram for explaining the operation of the specific example of the circuit, FIG. 8 is a waveform diagram for explaining the operation of the circuit example of FIG. 5, and FIG. 9 is a block diagram showing an embodiment of the present invention.
Claims (1)
源回路から電源電流の供給をうけるとともに電源
投入時に該第１の電源回路の出力が基準電圧を越
えて安定する時点より早くその出力が安定する第
２の電源回路と、該第２の電源回路から電源電流
の供給をうける第１の制御対象回路と、前記第１
の電源回路の出力電圧を一方の入力とし他方の入
力を前記基準電圧として該一方の入力の電圧が該
基準電圧を越えたときに前記第１の制御対象回路
へのリセツト信号を出力する第１のリセツト回路
と、該リセツト信号に応答して前記第１の電源回
路からボタン電話機への電源電流の供給を一時的
に停止した後再び該電源電流の供給を行う電話機
電流供給回路とを備え、前記ボタン電話機には、
前記電話機電流供給回路から電源電流を供給され
る電話機電源回路と、該電話機電源回路から電源
電流の供給をうける第２の制御対象回路と、該電
話機電源回路から該第２の制御対象回路に電源電
流が供給されたときに該第２の制御対象回路をリ
セツトする第２のリセツト回路とを備えたボタン
電話装置の電源回路。1 The main device includes a first power supply circuit, a power supply current is supplied from the first power supply circuit, and the main device is supplied with a power supply current from the first power supply circuit. a second power supply circuit whose output is stable; a first controlled circuit that receives power supply current from the second power supply circuit;
A first control circuit that outputs a reset signal to the first controlled circuit when the voltage of the one input exceeds the reference voltage, with the output voltage of the power supply circuit as one input and the other input as the reference voltage. a reset circuit; and a telephone current supply circuit that temporarily stops supplying power current from the first power supply circuit to the button telephone in response to the reset signal, and then resumes supplying the power current, The button telephone includes:
a telephone power supply circuit to which power supply current is supplied from the telephone power supply circuit; a second controlled circuit to which power supply current is supplied from the telephone power supply circuit; A power supply circuit for a button telephone device, comprising a second reset circuit that resets the second controlled circuit when current is supplied.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56101657A JPS583424A (en) | 1981-06-30 | 1981-06-30 | Resetting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56101657A JPS583424A (en) | 1981-06-30 | 1981-06-30 | Resetting circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS583424A JPS583424A (en) | 1983-01-10 |
| JPH033416B2 true JPH033416B2 (en) | 1991-01-18 |
Family
ID=14306445
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56101657A Granted JPS583424A (en) | 1981-06-30 | 1981-06-30 | Resetting circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS583424A (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60186727U (en) * | 1984-05-18 | 1985-12-11 | 三菱電機株式会社 | Erroneous signal output prevention device when power is turned on |
| JPS62199114A (en) * | 1986-02-27 | 1987-09-02 | Oki Electric Ind Co Ltd | Analog-digital hybrid integrated circuit |
| JPH02241113A (en) * | 1989-03-14 | 1990-09-25 | Mitsubishi Electric Corp | Integrated circuit |
| US6005423A (en) * | 1994-02-10 | 1999-12-21 | Xilinx, Inc. | Low current power-on reset circuit |
| JP2000036732A (en) | 1998-07-17 | 2000-02-02 | Mitsubishi Electric Corp | Power-on reset circuit and semiconductor device |
| JP4095778B2 (en) * | 2001-08-24 | 2008-06-04 | 株式会社東芝 | Semiconductor device and power supply voltage control method |
| JP5481921B2 (en) * | 2009-04-28 | 2014-04-23 | ミツミ電機株式会社 | Semiconductor integrated circuit |
| JP5316258B2 (en) * | 2009-06-24 | 2013-10-16 | ミツミ電機株式会社 | Semiconductor integrated circuit |
| JP6057665B2 (en) * | 2012-10-25 | 2017-01-11 | ローム株式会社 | Semiconductor devices, electronic devices, vehicles |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5616315A (en) * | 1979-07-18 | 1981-02-17 | Mitsubishi Electric Corp | Resetting circuit of digital device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5941641Y2 (en) * | 1978-03-31 | 1984-12-01 | 株式会社東芝 | Reset signal generation circuit |
-
1981
- 1981-06-30 JP JP56101657A patent/JPS583424A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5616315A (en) * | 1979-07-18 | 1981-02-17 | Mitsubishi Electric Corp | Resetting circuit of digital device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS583424A (en) | 1983-01-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4794595A (en) | Voice and data transmission system | |
| JPH033416B2 (en) | ||
| US3965306A (en) | Telephone line transfer circuit | |
| US4313037A (en) | Telephone station set with improved flash signalling | |
| JPH1014087A (en) | Television conversation system | |
| JPS63232599A (en) | Telephone system | |
| JP2511695B2 (en) | Subscriber status monitoring device | |
| JP3254359B2 (en) | TV intercom equipment | |
| JP2599801Y2 (en) | Incoming call answer detection circuit | |
| JPH0429278B2 (en) | ||
| JP3181324B2 (en) | Terminal network controller | |
| JPH0450787B2 (en) | ||
| JP2546239Y2 (en) | Telephone line disconnection device | |
| JP3215964B2 (en) | Hold system and method for push-button telephone | |
| JPH0416542Y2 (en) | ||
| JPS63105558A (en) | Controlling system for call of automatic dialing network controller | |
| JPS646618Y2 (en) | ||
| JP2642720B2 (en) | Ground signal generation circuit | |
| JPH01158861A (en) | Ring trip circuit | |
| JPH0233220B2 (en) | ||
| JPS6312603Y2 (en) | ||
| JPS6259500B2 (en) | ||
| JPH0312515B2 (en) | ||
| JPH0329348B2 (en) | ||
| JPS60259027A (en) | Cordless telephone set |