JPH0332850U - - Google Patents
Info
- Publication number
- JPH0332850U JPH0332850U JP8440890U JP8440890U JPH0332850U JP H0332850 U JPH0332850 U JP H0332850U JP 8440890 U JP8440890 U JP 8440890U JP 8440890 U JP8440890 U JP 8440890U JP H0332850 U JPH0332850 U JP H0332850U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- character
- correct
- counter
- outputs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 5
- 238000011084 recovery Methods 0.000 description 1
Landscapes
- Detection And Prevention Of Errors In Transmission (AREA)
Description
第１図は従来の回線復旧装置の一例を説明する
ための構成図、第２図ａ〜ｃは第１図の動作を説
明するための図、第３図はこの考案の一実施例に
よる回線復旧装置の構成図、第４図ａ〜ｅは同実
施例の動作を説明するための図である。
２……正誤判定回路、４……回線復旧信号出力
端、１０１……第１のカウンタ、１０２……第２
のカウンタ。
FIG. 1 is a configuration diagram for explaining an example of a conventional line restoration device, FIGS. 2 a to c are diagrams for explaining the operation of FIG. 1, and FIG. 3 is a line diagram according to an embodiment of this invention. The configuration diagrams of the recovery device and FIGS. 4a to 4e are diagrams for explaining the operation of the same embodiment. 2... Correctness determination circuit, 4... Line restoration signal output terminal, 10 1 ... First counter, 10 2 ... Second
counter.
補正 平２．９．７
実用新案登録請求の範囲を次のように補正する
。Amendment 2.9.7. The scope of claims for utility model registration is amended as follows.
【実用新案登録請求の範囲】
受信された各文字信号の正誤を判定して誤文字
信号又は正文字信号を出力する正誤判定回路と、
この正誤判定回路から出力される誤文字信号を計
数し予め設定した２以上の第１の計数値に達する
とその計数完了信号を回線復旧信号として出力す
る第１のカウンタと、上記誤文字信号を自己に対
するリセツト信号として上記正誤判定回路から出
力される正文字信号を計数して予め設定した、上
記第１の計数値より小さい２以上の第２の計数値
に達すると上記第１のカウンタに対してリセツト
信号を出力する第２のカウンタとを具備したこと
を特徴とするデイジタル文字伝送システムにおけ
る回線復旧装置。[Claims for Utility Model Registration] A correctness determination circuit that determines the correctness of each received character signal and outputs an incorrect character signal or a correct character signal;
A first counter that counts the erroneous character signals output from the correctness determination circuit and outputs the counting completion signal as a line restoration signal when a preset first count value of 2 or more is reached; When the correct character signal outputted from the correct/incorrect judgment circuit is counted as a reset signal to the self and reaches a preset second count value of 2 or more smaller than the first count value, the first counter is 1. A line restoration device for a digital character transmission system, comprising: a second counter that outputs a reset signal in response to a reset signal.
Claims (1)
信号又は正文字信号を出力する正誤判定回路と、
この正誤判定回路から出力される誤文字信号を計
数し予め設定した２以上の計数値に達するとその
計数完了信号を回線復旧信号として出力する第１
のカウンタと、上記誤文字信号を自己に対するリ
セツト信号とし上記正誤判定回路から出力される
正文字信号を計数して予め設定した２以上の計数
値に達すると上記第１のカウンタに対してリセツ
ト信号を出力する第２のカウンタとを具備したこ
とを特徴とするデイジタル文字伝送システムにお
ける回線復旧装置。 a correctness determination circuit that determines whether each received character signal is correct and outputs an incorrect character signal or a correct character signal;
A first circuit that counts the erroneous character signals output from this correct/incorrect judgment circuit and outputs the counting completion signal as a line restoration signal when a preset count value of 2 or more is reached.
The counter uses the erroneous character signal as a reset signal to itself, counts the correct character signals output from the correctness determination circuit, and when it reaches a preset count of 2 or more, sends a reset signal to the first counter. 1. A line restoration device for a digital character transmission system, comprising: a second counter that outputs .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8440890U JPH0332850U (en) | 1990-08-09 | 1990-08-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8440890U JPH0332850U (en) | 1990-08-09 | 1990-08-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0332850U true JPH0332850U (en) | 1991-03-29 |
Family
ID=31632873
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8440890U Pending JPH0332850U (en) | 1990-08-09 | 1990-08-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0332850U (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4935843A (en) * | 1972-08-07 | 1974-04-03 | ||
| JPS50159609A (en) * | 1974-06-13 | 1975-12-24 | ||
| JPS5514593A (en) * | 1978-07-18 | 1980-02-01 | Matsushita Electric Ind Co Ltd | Error detection system in digital type recording and reproducing unit |
| JPS55154850A (en) * | 1979-05-21 | 1980-12-02 | Fujitsu Ltd | Circuit control system of data transmitter |
-
1990
- 1990-08-09 JP JP8440890U patent/JPH0332850U/ja active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4935843A (en) * | 1972-08-07 | 1974-04-03 | ||
| JPS50159609A (en) * | 1974-06-13 | 1975-12-24 | ||
| JPS5514593A (en) * | 1978-07-18 | 1980-02-01 | Matsushita Electric Ind Co Ltd | Error detection system in digital type recording and reproducing unit |
| JPS55154850A (en) * | 1979-05-21 | 1980-12-02 | Fujitsu Ltd | Circuit control system of data transmitter |
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