JPH0332087A - Manufacture of quantum thin wire - Google Patents
Manufacture of quantum thin wireInfo
- Publication number
- JPH0332087A JPH0332087A JP16747089A JP16747089A JPH0332087A JP H0332087 A JPH0332087 A JP H0332087A JP 16747089 A JP16747089 A JP 16747089A JP 16747089 A JP16747089 A JP 16747089A JP H0332087 A JPH0332087 A JP H0332087A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- plane
- quantum
- well structure
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 claims abstract description 62
- 239000010409 thin film Substances 0.000 claims abstract description 23
- 239000013078 crystal Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 239000000203 mixture Substances 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 14
- 238000005530 etching Methods 0.000 abstract description 13
- 239000010408 film Substances 0.000 abstract description 3
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 239000012808 vapor phase Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は量子細線の形成方法に関し、特に数１００Å以
下の量子細線を容易に形成できる量子ｍｌ線の形成方法
に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method for forming a quantum wire, and particularly to a method for forming a quantum ml wire that can easily form a quantum wire of several hundred Å or less.
（従来の技術）
従来、量子細線により半導体レーザの発振しきい値の低
減、温度特性の改善等多くのデバイスの特性改善が図ら
れている。(Prior Art) Conventionally, quantum wires have been used to improve the characteristics of many devices, such as reducing the oscillation threshold of semiconductor lasers and improving temperature characteristics.
（発明が解決しようとする課ＩＩ）
しかしながら、従来のリソグラフィーの技術では量子効
果を生じるに必要な数１００Å以下の半導体Ａ１１ｌ線
を作製することは簡単でなく、その形成方法に関する研
究が活発になされている。(Issue II to be solved by the invention) However, with conventional lithography techniques, it is not easy to fabricate semiconductor A11l lines with a thickness of several hundred Å or less, which is necessary to produce quantum effects, and research on methods for forming them has been actively conducted. ing.
量子細線はｘ、ｙ、ｚの３次元のうち、２次元を量子化
するものであるが、１次元だけを量子化するものは多重
８Ｍよりなる量子井戸構造として気相エピタキシャル成
長によりほぼ確立されている。Quantum wires quantize two dimensions out of the three dimensions x, y, and z, but those that quantize only one dimension have been established as quantum well structures consisting of multiple 8M layers by vapor phase epitaxial growth. There is.
本発明の目的は数１００Å以下の量子細線を容易に形成
する方法を提供することにある。An object of the present invention is to provide a method for easily forming quantum wires of several hundred angstroms or less.
（課題を解決するための手段）
前述の課題を解決するために本発明の量子細線の形成方
法は、（１００）面あるいは（１００）面より数度傾い
た面を表面としく０１１〉方向に直線状にのびる逆メサ
形状の段差を有する半導体基板上に多重の薄膜半導体層
でなる量子井戸ｎｖｔを含む多重半導体薄膜をエピタキ
シャル成長する工程と、前記段差上にエピタキシャル成
長により形成され露出された単一または多重量子井戸構
造の側面を、前記単一または多１量子井戸構造を形成す
る半導体層の結晶組成の違いを利用して選択エツチング
し、前記単一または多重量子井戸構造の測面に単一また
は複数の湧を形成する工程と、前記選択エツチングを施
した半導体ウェハ上に量子ＭＡ線を形成する半導体とそ
の量子細線を被覆する半導体層をエピタキシャル成長す
る工程とを含む。(Means for Solving the Problems) In order to solve the above-mentioned problems, the method for forming a quantum wire of the present invention uses a (100) plane or a plane tilted several degrees from the (100) plane as a surface, and A step of epitaxially growing a multiple semiconductor thin film including a quantum well NVT made of multiple thin film semiconductor layers on a semiconductor substrate having an inverted mesa-shaped step extending linearly, and an exposed single or The side surfaces of the multiple quantum well structure are selectively etched by utilizing the difference in crystal composition of the semiconductor layers forming the single or multiple quantum well structure, and the side surfaces of the single or multiple quantum well structure are etched. The method includes a step of forming a plurality of wells, and a step of epitaxially growing a semiconductor for forming a quantum MA line and a semiconductor layer covering the quantum wire on the semiconductor wafer subjected to the selective etching.
（作用）
量子細線は３次元の内、２次元を量子化するものであり
、数１００Å以下に制御すべき長さは２つ（量子細線の
断面の縦と横）ある。(Function) The quantum wire quantizes two dimensions among the three dimensions, and there are two lengths (vertical and horizontal of the cross section of the quantum wire) that should be controlled to several hundred Å or less.
本発明においては、気相エピタキシャル成長等における
面方位による結晶成長の停止と選択エツチングを活用し
ている。以下、図面を用いて詳細に説明する６図を用い
た説明では、量子井戸構造が多重量子井戸ｆｉｌｌ造で
あるときについて述べる。In the present invention, stopping crystal growth based on plane orientation and selective etching in vapor phase epitaxial growth and the like are utilized. Hereinafter, in the detailed explanation using FIG. 6, a case where the quantum well structure is a multi-quantum well fill structure will be described.
単一量子井戸の場合の作用も全く同じである。The effect in the case of a single quantum well is exactly the same.
第１図（ａ）、（ｂ）には、結晶成長の工程により形成
される多重半導体膜の断面図が、第２図（ａ）〜（ｃ）
と第３図には量子、ｍｌＫが形成される部分の拡大図が
選択エツチングの工程を含めて示されている。FIGS. 1(a) and (b) show cross-sectional views of multiple semiconductor films formed by the crystal growth process, and FIGS. 2(a) to (c)
FIG. 3 shows an enlarged view of the portion where the quantum mlK is formed, including the selective etching process.
本発明の量子細線の形成工程には第１図（ａ）と（ｂ）
に示すように２回の結晶成長の工程が含まれる。The process of forming the quantum wire of the present invention is shown in FIGS. 1(a) and (b).
As shown in the figure, two crystal growth steps are included.
最初に第１図（ａ）に示すように、（１００）面あるい
は（１００）面より数度傾いた面を表面とし、＜０１１
＞方向の逆メサ形状の段差を有する半導体基板４上に多
重量子井戸構造１を第１と第２の半導体１ｍ２．３によ
り挟み込んだ多重半導体薄膜を気相エピタキシャル成長
する。このとき前記段差により前記多重半導体薄膜は分
断され段差上面では（１１１）Ｂ面が側面に現れ、多重
量子井戸Ｗ４造１は開面を露出する。第２図（ａ）にそ
のときの多重量子井戸ｖ４造１の側面部分の拡大図を示
す。First, as shown in Figure 1(a), the surface is the (100) plane or a plane tilted several degrees from the (100) plane, and <011
A multiple semiconductor thin film having a multiple quantum well structure 1 sandwiched between first and second semiconductors 1m2.3 is grown by vapor phase epitaxial growth on a semiconductor substrate 4 having an inverted mesa-shaped step in the > direction. At this time, the multiple semiconductor thin film is divided by the step, and the (111)B plane appears on the side surface on the top surface of the step, and the open surface of the multiple quantum well W4 structure 1 is exposed. FIG. 2(a) shows an enlarged view of the side surface of the multi-quantum well V4 structure 1 at that time.
多重量子井戸構造１は、第１の薄膜半導体層１０と第２
の薄膜半導体層２０が交互に積層されたものであり、そ
の厚さはそれぞれ数１００Å以下とする。その厚さの制
御は気相エピタキシャル成長により容易に行える。The multiple quantum well structure 1 includes a first thin film semiconductor layer 10 and a second thin film semiconductor layer 10.
thin film semiconductor layers 20 are alternately stacked, each having a thickness of several hundred angstroms or less. The thickness can be easily controlled by vapor phase epitaxial growth.
次に、第１の薄膜半導体７Ｗ１０と第２の薄膜半導体層
２０の結晶組成の差を利用し選択エツチングを行う、エ
ツチング後の多重量子井戸構造１の側面の形状を第２図
（ｂ）に示す、第１の薄膜半導体層１０のみがサイドエ
ツチングされ側面に幅数１００人の清が複数形成される
。深さはエツチング液のエツチングレートおよびエツチ
ング時間を制御し数１００Å以下とする。この制御は低
速度のエツチングレートを用いれば十分に制御可能であ
る。Next, selective etching is performed using the difference in crystal composition between the first thin film semiconductor 7W10 and the second thin film semiconductor layer 20. The shape of the side surface of the multiple quantum well structure 1 after etching is shown in FIG. 2(b). Only the first thin film semiconductor layer 10 shown in FIG. 1 is side-etched to form a plurality of holes several hundred widths wide on the side surface. The depth is controlled to be several hundred angstroms or less by controlling the etching rate and etching time of the etching solution. This control can be sufficiently controlled using a low etching rate.
その後、前述した選択エツチングを施した半導体ウェハ
上に２回目の気相エピタキシャル成長を行う、第１図（
ｂ）に２回目の気相エピタキシャル成長後の断面を示す
、この成長で最初に積層する半導体結晶は量子細線を形
成する半導体とする。Thereafter, a second vapor phase epitaxial growth is performed on the semiconductor wafer that has been selectively etched as described above.
b) shows a cross section after the second vapor phase epitaxial growth. The semiconductor crystal that is first stacked in this growth is a semiconductor that forms quantum wires.
前記多重量子井戸Ｉｌ造の開面でのこの半導体の成長は
サイドエツチングされた第１の薄膜半導体開面にしか起
こらず、さらにその成長もサイドエツチングされた分だ
け成長し、側面を再び平坦な（１１１）Ｂ面に復帰させ
、そこで自動的に停止する。The growth of this semiconductor on the open surface of the multi-quantum well Il structure occurs only on the side-etched first thin-film semiconductor open surface, and the growth also grows by the side-etched amount, making the side surface flat again. (111) Return to side B and automatically stop there.
段差上面および下面には当然成長が生じており、第１図
（ｂ）での第３の半導体層５となる。このときの多重量
子井戸１３ｆｌｌの曲面を拡大して第２図（ｃ）に示す
、多重量子井戸構造１の側面に形成された複数の清が半
導体により埋め込まれ、量子細線６を形成する。この状
態を第３図の拡大斜視図に示す。Naturally, growth occurs on the upper and lower surfaces of the step, forming the third semiconductor layer 5 in FIG. 1(b). The curved surface of the multiple quantum well 13fl at this time is shown in FIG. 2(c) when enlarged, and a plurality of holes formed on the side surface of the multiple quantum well structure 1 are embedded with semiconductor to form a quantum wire 6. This state is shown in the enlarged perspective view of FIG.
さらに量子細線６を形成した半導体と組成の異なる半導
体を続けて成長して第１図（ｂ）の第４の半導体層７を
形成する。Further, a semiconductor having a different composition from the semiconductor forming the quantum wire 6 is successively grown to form the fourth semiconductor layer 7 shown in FIG. 1(b).
この半導体は、初期には段差の上面と下面とに分離成長
するが、全成長層の厚さが半導体基板４に形成した段差
の高さと等しくなるにつれて側面への成長が始まり、量
子細線６は半導体中に埋め込まれ、すべての界面を半導
体へテロ接合とする量子細線が形成される６以上のよう
にして直接にリソグラフィーの技術を用いることなく量
子細線を形成することができる。Initially, this semiconductor grows separately on the top and bottom surfaces of the step, but as the thickness of the entire growth layer becomes equal to the height of the step formed on the semiconductor substrate 4, it begins to grow on the side surfaces, and the quantum wire 6 Quantum wires can be directly formed without using lithography technology as described above in which quantum wires are embedded in a semiconductor and have all interfaces as semiconductor heterojunctions.
（実施例） 以下、具体的実作例について説明する。(Example) A specific example will be explained below.
先ず、３μｍの高さの逆メサ形状の段差を形成したＧａ
Ａｓ基板４上に、Ａ ｌ ｏ、ｓ Ｇ ａｏ、ｙ Ａ
ｓでなる厚さ０．５μｍの第１の半導体層２とＡ Ｉ
ｏ、ｓ Ｇ ａｏ、ｙ Ａ ＳとＧａｏ、ｓ Ｉ ｎｏ
、ｓ Ｐよりなる多重量子井戸構造１とＡ Ｉ ｏ、ｓ
Ｇ ａｏ７Ａ ｓでなる厚さ０．５μｍの第２の半導
体層３を有機金属分解成長法（ＭＯＶＰＥ法）により順
次積層する。この成長は７０Ｔｏｒｒの減圧下において
行なわれる。このとき成長は段差の上面と下面とに分離
成長し、多重量子井戸構造１は開面が露出される。First, Ga
On the As substrate 4, A lo, s G ao, y A
The first semiconductor layer 2 with a thickness of 0.5 μm and A I
o, s Gao, y A S and Gao, s I no
, s P and A I o, s
A second semiconductor layer 3 made of Gao7As and having a thickness of 0.5 μm is sequentially laminated by a metal organic decomposition growth method (MOVPE method). This growth is performed under reduced pressure of 70 Torr. At this time, the growth occurs separately on the upper and lower surfaces of the step, and the open surface of the multi-quantum well structure 1 is exposed.
第２図（ａ）において、第１の薄膜半導体層１０はＧａ
ａ、ｓ Ｉ ｎｏ、ｓ ｐＮＪであり、第２の薄膜半導
体Ｎｌ２０はＡＩｏ、、Ｇａ０．ｔ Ａｓで、それぞれ
の膜厚は１００人とする。In FIG. 2(a), the first thin film semiconductor layer 10 is made of Ga.
a, s I no, sp NJ, and the second thin film semiconductor Nl20 is AIo, , Ga0. tAs, and each film thickness is 100 people.
次に、塩酸と水の混液によりエツチングを０℃で１０秒
行う、このエツチング液によりエツチングされる半導体
層はＧａｏ、ｓ Ｉ ｎｏ、ｓ Ｐであり、Ａ Ｉ ｏ
、ｓ Ｇａｏ７Ａｓｌはエツチングされないので、エツ
チングされる部分は多重量子井戸構造１の段差による側
面でかつ第１の薄膜半導体Ｎ１０のみである。Next, etching is performed with a mixture of hydrochloric acid and water at 0° C. for 10 seconds. The semiconductor layers etched with this etching solution are Gao, s I no, s P, and A I o
, s Gao7Asl is not etched, so the etched portion is only the side surface due to the step of the multi-quantum well structure 1 and the first thin film semiconductor N10.
その後、再び７０Ｔｏｒｒの減圧ＭＯＶＰＥ法によりＧ
ａＡｓを５００人積層し、続いてＡ Ｉｏ、ｓ Ｇａｏ
、ｙ ＡｓＦＩ３ｊ１２μｍｐ９するっここで、透過電
子顕微鏡による評価によれば、ＧａＡｓ層の前述開面で
の戒長はＧ ａ 。After that, the G
Stack 500 aAs, then A Io, s Gao
, y AsFI3j12μmp9 Here, according to an evaluation using a transmission electron microscope, the length of the GaAs layer at the above-mentioned open plane is Ga.
ｒｎａ５Ｐでなる第１の薄膜半導体層のエツチングされ
た測面にのみ戒長し、１００人〜２００人を一辺の長さ
とする台形断面を有する量子細線が形成されていること
が観測された。It was observed that a quantum wire having a trapezoidal cross section with a side length of 100 to 200 nanometers was formed, extending only on the etched surface of the first thin film semiconductor layer made of RNA5P.
（発明の効果）
以上説明したように本発明によれば、リソグラフィーを
直接量子ｌ５ＩＩＩ線の形成に用いることなく、すべて
の界面をヘテロ接合とする量子細線を形成することがで
きる。(Effects of the Invention) As described above, according to the present invention, a quantum wire in which all interfaces are heterojunctions can be formed without directly using lithography to form the quantum I5III line.
第１図（ａ）と（ｂ）は本発明の量子細線の形成方法の
中での結晶成長による半導体薄膜の積層を示す断面図、
第２図（ａ）〜（ｃ）および第３図は量子ＭＪ線影形成
部拡大図である。
１・・・多重量子井戸構造、２・・・第１の半導体層、
３・・・第２の半導体層、４・・・半導体基板、５・・
・第３の半導体層、６・・・量子４Ｉ線、７・・・第４
の半導体層、０・・・第１の薄膜半導体層、
２０・・・第２の薄膜率
導体層。FIGS. 1(a) and 1(b) are cross-sectional views showing the stacking of semiconductor thin films by crystal growth in the quantum wire forming method of the present invention;
FIGS. 2(a) to 3(c) and 3 are enlarged views of the quantum MJ line shadow forming part. 1...Multi-quantum well structure, 2...First semiconductor layer,
3... Second semiconductor layer, 4... Semiconductor substrate, 5...
・Third semiconductor layer, 6... quantum 4I line, 7... fourth
0...First thin film semiconductor layer, 20... Second thin film conductor layer.
Claims (1)
表面とし〈０１１〉方向に直線状にのびる逆メサ形状の
段差を有する半導体基板上に多重の薄膜半導体層でなる
量子井戸構造を含む多重半導体薄膜をエピタキシャル成
長する工程と、前記段差上にエピタキシャル成長により
形成され露出された単一または多重量子井戸構造の側面
を、前記単一または多重量子井戸構造を形成する半導体
層の結晶組成の違いを利用して選択エッチングし、前記
単一または多重量子井戸構造の側面に単一または複数の
溝を形成する工程と、前記選択エッチングを施した半導
体ウェハ上に量子細線を形成する半導体とその量子細線
を被覆する半導体層をエピタキシャル成長する工程とを
含むことを特徴とする量子細線の形成方法。It includes a quantum well structure consisting of multiple thin film semiconductor layers on a semiconductor substrate whose surface is a (100) plane or a plane tilted several degrees from the (100) plane and has an inverted mesa-shaped step extending linearly in the <011> direction. A step of epitaxially growing a multiple semiconductor thin film, and a step of epitaxially growing a multi-layered semiconductor thin film, and a step of forming an exposed side surface of a single or multiple quantum well structure formed by epitaxial growth on the step to detect differences in the crystal composition of the semiconductor layers forming the single or multiple quantum well structure. forming a single or multiple grooves on the side surface of the single or multiple quantum well structure, and forming a quantum wire on the selectively etched semiconductor wafer; A method for forming a quantum wire, comprising the step of epitaxially growing a semiconductor layer covering the quantum wire.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16747089A JPH0332087A (en) | 1989-06-29 | 1989-06-29 | Manufacture of quantum thin wire |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16747089A JPH0332087A (en) | 1989-06-29 | 1989-06-29 | Manufacture of quantum thin wire |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0332087A true JPH0332087A (en) | 1991-02-12 |
Family
ID=15850274
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16747089A Pending JPH0332087A (en) | 1989-06-29 | 1989-06-29 | Manufacture of quantum thin wire |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0332087A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013513960A (en) * | 2009-12-15 | 2013-04-22 | コンソルティオ デルタ ティアイ リサーチ | Thermoelectric conversion device using the Savebeck / Peltier effect, comprising parallel nanowires made of a conductive material or a semiconductor material arranged in rows and columns via an insulating material, and a method of manufacturing the same |
-
1989
- 1989-06-29 JP JP16747089A patent/JPH0332087A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013513960A (en) * | 2009-12-15 | 2013-04-22 | コンソルティオ デルタ ティアイ リサーチ | Thermoelectric conversion device using the Savebeck / Peltier effect, comprising parallel nanowires made of a conductive material or a semiconductor material arranged in rows and columns via an insulating material, and a method of manufacturing the same |
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