JPH0331086Y2 - - Google Patents
Info
- Publication number
- JPH0331086Y2 JPH0331086Y2 JP1985065541U JP6554185U JPH0331086Y2 JP H0331086 Y2 JPH0331086 Y2 JP H0331086Y2 JP 1985065541 U JP1985065541 U JP 1985065541U JP 6554185 U JP6554185 U JP 6554185U JP H0331086 Y2 JPH0331086 Y2 JP H0331086Y2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor package
- conductor pin
- printed wiring
- wiring board
- package substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004020 conductor Substances 0.000 claims description 58
- 239000000758 substrate Substances 0.000 claims description 37
- 239000004065 semiconductor Substances 0.000 claims description 32
- 239000002184 metal Substances 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 229920005989 resin Polymers 0.000 claims description 10
- 239000011347 resin Substances 0.000 claims description 10
- 239000003365 glass fiber Substances 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 6
- 239000000919 ceramic Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 239000011521 glass Substances 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 239000003822 epoxy resin Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 238000003491 array Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 1
- 229910000906 Bronze Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 239000010974 bronze Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 229910000833 kovar Inorganic materials 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【考案の詳細な説明】
〔産業上の利用分野〕
本考案は各種の半導体素子、チツプ素子などを
搭載、封止してなる導体ピンを有する半導体用パ
ツケージ基板に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor package substrate having conductor pins on which various semiconductor elements, chip elements, etc. are mounted and sealed.
本考案の半導体用パツケージ基板に半導体素子
を搭載したパツケージは高密度実装用パツケージ
として通常のプリント配線基板に実装して用いら
れる。 A package in which a semiconductor element is mounted on a semiconductor package substrate according to the present invention is used as a package for high-density mounting by being mounted on an ordinary printed wiring board.
従来、半導体素子のパツケージとしてはデユア
ルインラインパツケージ（DIP）、フラツトパツ
ケージ、チツプキヤリア、ピングリツドアレーな
どがあり、パツケージを構成をするものは、主に
プラスチツク及びセラミツクである。これらのパ
ツケージの中で、ピングリツドアレーは最近の高
集積化された半導体素子の搭載に適しており、外
部接続用端子の増加に対して十分対応できるため
高密度実装用としてコンピユーターをはじめ、各
種の用途に利用されている。従来のピングリツド
アレーはセラミツクからなる基板に回路形成後、
該基板に入出力用の導体ピンを、装着する工程に
おいて、約800℃という比較的高温で溶融する銀
ロウを介してセラミツク基板の回路と導体ピンを
固着し、電気的に接続している。
Conventionally, packages for semiconductor devices include dual in-line packages (DIPs), flat packages, chip carriers, pin grid arrays, etc., and the packages are mainly made of plastics and ceramics. Among these packages, pingrid arrays are suitable for mounting recent highly integrated semiconductor devices, and are suitable for high-density mounting in computers and other devices, as they can sufficiently handle the increase in the number of external connection terminals. It is used for various purposes. In the conventional pin grid array, after circuits are formed on a ceramic substrate,
In the process of attaching input/output conductor pins to the board, the circuits on the ceramic board and the conductor pins are fixed and electrically connected via silver solder, which melts at a relatively high temperature of approximately 800°C.
しかしながら、これらセラミツク基板にピンを
接合したパツケージは複雑な工程を得てセラミツ
ク基板に回路形成され、さらに高価な銀ロウを用
いて約800℃という高温で導体ピンを接合されな
ければならず、コスト高となる欠点があつた。
又、ロウ付けの際に用いる治工具は高温に耐えか
つ熱変形が極めて小さい材質が要求され、さらに
は治工具の加工精度を非常に高くすることが要求
されるため、これら治工具は極めて高価なものと
なり、その結果、製品コスト高になる。
However, these packages in which pins are bonded to ceramic substrates require complicated processes to form circuits on the ceramic substrate, and conductor pins must be bonded at a high temperature of approximately 800°C using expensive silver solder, resulting in high costs. There was a drawback that it was expensive.
In addition, the jigs and tools used for brazing must be made of materials that can withstand high temperatures and have extremely low thermal deformation, and are also required to have extremely high machining accuracy, making these jigs and tools extremely expensive. This results in higher product costs.
また、800℃の高温雰囲気中で変質しない導体
ピンの選定が必要となり、その種類が限定される
欠点がある。また、セラミツク基板に導体ピンを
固着後、導体ピン表面に金属メツキを施すために
金属メツキ時の取扱いが極めて面倒である。ま
た、プリント配線板の外形線に平行になるように
ガラス繊維を積層してある有機系樹脂素材からな
るプリント配線板においては、扁平部を有する導
体ピンを嵌入固着したとき、上記ガラス繊維と樹
脂硬化体との界面に剥離が生じ易いという問題が
ある（詳細は後述する）。本考案は、上記ガラス
繊維を積層したプリント配線板における、導体ピ
ン挿入時の問題点を解決することを目的とし、実
用新案登録の請求範囲に記載の半導体用パツケー
ジ基板を提供することによりその目的を達成する
ものである。 In addition, it is necessary to select conductor pins that do not deteriorate in a high-temperature atmosphere of 800°C, and there is a drawback that the types of conductor pins are limited. Furthermore, since the surface of the conductor pin is plated with metal after the conductor pin is fixed to the ceramic substrate, handling during metal plating is extremely troublesome. In addition, in a printed wiring board made of an organic resin material in which glass fibers are laminated parallel to the outline of the printed wiring board, when a conductor pin having a flat part is inserted and fixed, the glass fibers and resin There is a problem in that peeling tends to occur at the interface with the cured product (details will be described later). The purpose of the present invention is to solve the problems encountered when inserting conductor pins in the printed wiring board laminated with glass fibers, and to achieve this purpose by providing a semiconductor package substrate as claimed in the claims of the utility model registration. The goal is to achieve the following.
本考案の半導体用パツケージ基板の斜視図を第
１図に示す。第１図において、２は有機系樹脂素
材からなるプリント配線板であり、例えばガラス
エポキシ基板、ガラスポリイミド基板、ガラスト
リアジン基板などを用いる。同図において、１は
プリント配線板のスルホールに嵌入固着された入
出力用の導体ピンである。該導体ピンは金属線を
加工されてなるものであり、コバール、42アロ
イ、りん青銅、銅などの材質である。また、同図
６は半導体素子を搭載する部分であり、ザグリ加
工などで凹部が形成されている場合がある。ま
た、同図の７は常法により、プリント配線板表面
に形成された回路である。
FIG. 1 shows a perspective view of the semiconductor package substrate of the present invention. In FIG. 1, reference numeral 2 denotes a printed wiring board made of an organic resin material, such as a glass epoxy substrate, a glass polyimide substrate, a glass triazine substrate, or the like. In the figure, reference numeral 1 denotes an input/output conductor pin that is inserted and fixed into a through hole of a printed wiring board. The conductor pin is made of processed metal wire, and is made of materials such as Kovar, 42 alloy, phosphor bronze, and copper. Further, FIG. 6 shows a portion on which a semiconductor element is mounted, and a recessed portion may be formed by counterboring or the like. Further, 7 in the figure is a circuit formed on the surface of the printed wiring board by a conventional method.
第２図は本考案の半導体用パツケージ基板の上
平面図である。同図において、Ａ←→Ｂ及びＣ←→Ｄ
は基板の横方向及び縦方向を示すものである。ま
た、本図においては該基板に形成されたスルホー
ル３とスルホールに挿入固着された導体ピンの扁
平部１５の凸部方向を矢印（←→）で示している。
本図では、前記扁平部１５の扁平面がプリント配
線板２の外形線であるＡ←→Ｂ方向（横方向）とＣ
←→Ｄ方向（縦方向）のいずれにも平行にならない
ように規則正しく配列されており、１つの導体ピ
ンの扁平部の扁平面の延長線X1−X2と、該延長
線X1−X2上において前記導体ピンに隣接する導
体ピンの扁平部の扁平面の延長線Y1−Y2とが略
直交するように配置されている。 FIG. 2 is a top plan view of the semiconductor package substrate of the present invention. In the same figure, A←→B and C←→D
indicates the horizontal and vertical directions of the substrate. Further, in this figure, arrows (←→) indicate the direction of the convex portion of the through hole 3 formed in the substrate and the flat portion 15 of the conductor pin inserted and fixed in the through hole.
In this figure, the flat surface of the flat portion 15 is shown in the direction A←→B (lateral direction), which is the outline of the printed wiring board 2, and in the direction C
←→ They are arranged regularly so as not to be parallel to any of the D directions (vertical directions), and the extension line X 1 -X 2 of the flat surface of the flat part of one conductor pin and the extension line X 1 -X 2 , the extension line Y 1 -Y 2 of the flat surface of the flat portion of the conductor pin adjacent to the conductor pin is arranged to be substantially orthogonal to each other.
第３図のａ〜ｆはスルホールに嵌入固着された
扁平部１５の扁平面方向（←→）の状態をそれぞれ
示すものである。 3A to 3F respectively show the state of the flat portion 15 fitted and fixed in the through hole in the direction of the flat surface (←→).
第４図及び第６図はスルホールに嵌入固着され
た導体ピンの扁平部周辺を拡大した上平面図であ
り第５図及び第７図は、第４図、第６図のそれぞ
れに対応したスルホールと導体ピンを含む基板の
縦断面図を示している。 4 and 6 are enlarged top plan views of the periphery of the flat part of the conductor pin fitted and fixed in the through hole, and FIGS. 5 and 7 are through holes corresponding to those in FIGS. 4 and 6, respectively. and a vertical cross-sectional view of a board including conductor pins.
第５図及び第７図において４は導体ピンの扁平
部１５の下部に形成された鍔であり、この鍔４は
導体ピンをプリント配線板のスルホールに挿入す
る際の位置合せや係止の役割を果すものである。
又１５は金属線の直径方向に突出した凸状の扁平
部であり、この扁平部の幅はプリント配線板のス
ルホールの直径より大きい。又、第７図の１６は
前記凸状扁平部１５にほぼ直交する位置に形成さ
れた金属線の直径より小さい凹状扁平部である。
導体ピン１の両端部には曲面が形成されており、
プリント配線板のスルホールに導体ピンを挿入す
ることが容易である。又、金属線から加工された
導体ピン表面には予め、基板に挿入する前に金、
銀、スズ、はんだなどの金属メツキを施しておく
ことができる。該金属メツキ膜は導体ピンの腐蝕
を防止し、導体ピン表面を保護している。回路基
板のメツキと導体ピンのメツキはそれぞれ別々に
施すことができ、工程上簡単である。前記導体ピ
ン１がプリント配線板に形成されたスルホール３
に加圧挿入された場合は第５図及び第７図に示さ
れているように前記スルホール３の一部が導体ピ
ンの凸状扁平部に沿つて変形し、スルホール壁面
に導体ピンの前記凸状扁平部が完全密着し、強固
に装着される。この為、スルホールと導体ピンは
電気的にも確実に接続される。このようにして、
接合された導体ピンは嵌入固着後の振動や衝撃に
よつてスルホールから脱落したり、接合部がゆる
んだりすることはない。しかし、隣接する導体ピ
ンの凸状扁平部１５の方向が第５図に示すもので
あると、導体ピンを挿入後、前記スルホール壁の
変形した部分には第５図の断面図に示すように基
板内部において、基板の水平方向に圧縮応力が矢
印８の方向に加わる。この圧縮応力は前記導体ピ
ンの凸状扁平部周囲の基板に局部的に加わるもの
である。一方、隣接する導体ピンの凸状扁平部１
５の方向が第７図に示すものであると、前記凸状
扁平部１５にほぼ直交する位置に形成された凹状
扁平部１６では導体ピン挿入後、凹状扁平部周辺
のスルホール３の側壁は第７図の断面図に示すよ
うにほとんど変形せず、基板への圧縮応力がほと
んど生じない。この場合、基板内部に悪影響を及
ぼす圧縮応力が局所的に集中することはなく、基
板全面に圧縮応力を分散させることができる。第
４図及び第５図においては、凸状変形部１５の扁
平面が同一線上に並んだ状態を示しており、該線
上には基板内部の水平方向に圧縮応力が集中し基
板を構成する樹脂硬化体に微細なクラツクを生じ
させたり、あるいは、樹脂硬化体とガラス繊維の
界面に剥離を生じさせるため機能が低下してしま
う。第６図及び第７図においては、同一線上に隣
り合う導体ピンの凸状扁平部と凹状扁平部が交互
に配列されており、同一線上の基板内部の水平方
向に圧縮応力が集中することを緩和しており、基
板内部への悪影響は少ない。第３図のａ〜ｃにお
いては、一部の導体ピンの凸状扁平部の扁平面が
基板の外形線Ａ←→Ｂ方向（横方向）又はＣ←→Ｄ方
向（縦方向）に平行配列された状態の半導体用パ
ツケージ基板の上正面図を示している。通常、基
板内部のガラス繊維は基板外形線に平行になるよ
うに積層されており、前記導体ピンの凸状扁平部
１５の扁平面周辺はガラス繊維方向にガラス繊維
と樹脂硬化体の界面に剥離が生じやすいため、基
板の機能がそこなわれてしまう。第３図のｄ及び
ｅにおいては、導体ピンの凸状扁平部１５の扁平
面は基板外形線と平行になつていないため、凸態
扁平部１５周辺への悪影響は少ない。また、第３
図のｆにおいては、隣り合う導体ピンの凸状扁平
部１５と凹状扁平部１６が交互に配例されかつ、
外形線と凸状扁平部１５は平行になつていないた
め、より効果が大である。 In FIGS. 5 and 7, 4 is a collar formed at the bottom of the flat part 15 of the conductor pin, and this collar 4 plays a role in positioning and locking when inserting the conductor pin into the through hole of the printed wiring board. It fulfills the following.
Further, 15 is a convex flat portion projecting in the diametrical direction of the metal wire, and the width of this flat portion is larger than the diameter of the through hole of the printed wiring board. Further, reference numeral 16 in FIG. 7 is a concave flat portion formed at a position substantially perpendicular to the convex flat portion 15 and having a diameter smaller than the metal wire.
Curved surfaces are formed at both ends of the conductor pin 1,
It is easy to insert the conductor pins into the through holes of the printed wiring board. In addition, the surface of the conductor pin processed from metal wire is coated with gold or gold before inserting it into the board.
It can be plated with metal such as silver, tin, or solder. The metal plating film prevents corrosion of the conductor pin and protects the surface of the conductor pin. The plating of the circuit board and the plating of the conductor pins can be performed separately, which simplifies the process. The conductor pin 1 is formed in a through hole 3 formed in a printed wiring board.
When the through hole 3 is inserted under pressure, a part of the through hole 3 is deformed along the convex flat part of the conductor pin as shown in FIGS. The flat part fits completely and is firmly attached. Therefore, the through hole and the conductor pin are electrically connected reliably. In this way,
The bonded conductor pin will not fall out of the through hole or the bonded portion will become loose due to vibration or impact after it is inserted and fixed. However, if the direction of the convex flat portion 15 of the adjacent conductor pin is as shown in FIG. Inside the substrate, compressive stress is applied in the horizontal direction of the substrate in the direction of arrow 8. This compressive stress is locally applied to the substrate around the convex flat portion of the conductor pin. On the other hand, the convex flat portion 1 of the adjacent conductor pin
5 is as shown in FIG. 7, in the concave flat part 16 formed at a position substantially orthogonal to the convex flat part 15, after the conductor pin is inserted, the side wall of the through hole 3 around the concave flat part will be As shown in the cross-sectional view of FIG. 7, there is almost no deformation, and almost no compressive stress is generated on the substrate. In this case, compressive stress that has an adverse effect on the inside of the substrate is not locally concentrated, and the compressive stress can be dispersed over the entire surface of the substrate. 4 and 5 show a state in which the flat surfaces of the convex deformation portions 15 are lined up on the same line, and compressive stress is concentrated in the horizontal direction inside the substrate on the line, and the resin constituting the substrate is concentrated on the line. This causes fine cracks in the cured product or peeling at the interface between the cured resin and glass fibers, resulting in a decrease in functionality. In Figures 6 and 7, the convex flat parts and concave flat parts of adjacent conductor pins are arranged alternately on the same line, and compressive stress is concentrated in the horizontal direction inside the board on the same line. It has been alleviated, and there is little negative impact on the inside of the board. In a to c of FIG. 3, the flat surfaces of the convex flat portions of some of the conductor pins are arranged parallel to the board outline A←→B direction (horizontal direction) or C←→D direction (vertical direction). FIG. 3 is a top front view of the semiconductor package substrate in a state where the semiconductor package substrate is in a state where Usually, the glass fibers inside the board are stacked parallel to the board outline, and the area around the flat surface of the convex flat part 15 of the conductor pin is peeled in the direction of the glass fibers at the interface between the glass fiber and the cured resin. This tends to occur, resulting in damage to the board's functionality. In d and e of FIG. 3, since the flat surface of the convex flat part 15 of the conductor pin is not parallel to the board outline, there is little adverse effect on the vicinity of the convex flat part 15. Also, the third
In figure f, the convex flat portions 15 and concave flat portions 16 of adjacent conductor pins are arranged alternately, and
Since the outline and the convex flat portion 15 are not parallel, the effect is even greater.
第８図は２つの鍔４，５を有する導体ピンの正
面及び側面の縦断面図である。同図の導体ピンは
一般にスタンドオフピンと呼ばれるものであり、
ピングリツドアレー型パツケージ基板の４つのコ
ーナーに配置されている。前記スタンドオフピン
により、ピングリツドアレー型パツケージを通常
のプリント配線板に実装後、ピングリツドアレー
パツケージとプリント配線板との間に空間を形成
することができ、半導体素子から発生する熱を該
空間へ効率よく放散させる。また、鍔５の形状が
前記プリント配線板の方向からみて楕円形の場
合、パツケージのプリント配線板への実装方向を
示すことができる。さらに、はんだ付け時にはん
だ揚りを著しく向上させることが可能である。 FIG. 8 is a front and side longitudinal sectional view of a conductor pin having two flanges 4, 5. The conductor pin in the figure is generally called a standoff pin.
They are placed at the four corners of the pin grid array type package board. The standoff pins allow a space to be formed between the pin grid array package and the printed wiring board after mounting the pin grid array package on a normal printed wiring board, thereby dissipating the heat generated from the semiconductor element. Efficiently diffuse into the space. Further, when the shape of the collar 5 is oval when viewed from the direction of the printed wiring board, it can indicate the direction in which the package is mounted on the printed wiring board. Furthermore, it is possible to significantly improve soldering performance during soldering.
第９図は本考案の半導体用パツケージ基板の一
例であるピングリツドアレーパツケージ基板に半
導体素子をダイボンデイング、ワイヤーボンデイ
ングを経てエポキシ樹脂などで樹脂封止してなる
該ピングリツドアレーパツケージを一般のプリン
ト配線板１３に実装した状態の一例を示す断面図
である。同図において、９は半導体素子、１０は
ボンデイングワイヤー、１１はエポキシ樹脂であ
る。また、１２はエポキシ樹脂の流出防止の堰枠
である。 FIG. 9 shows a general pin grid array package, which is an example of the semiconductor package substrate of the present invention, in which a semiconductor element is die-bonded, wire bonded, and then sealed with an epoxy resin. FIG. 2 is a cross-sectional view showing an example of a state where the device is mounted on a printed wiring board 13 of the present invention. In the figure, 9 is a semiconductor element, 10 is a bonding wire, and 11 is an epoxy resin. Further, 12 is a weir frame for preventing the epoxy resin from flowing out.
以上のように、本考案によれば、外形線に平行
になるようにガラス繊維を積層したガラスエポキ
シ基板などの有機系樹脂素材の基板に、かしめと
いう極めて簡便な構成で導体ピンが嵌挿されなが
らも、導体ピンと基板の接合部の信頼性をそこな
うことがない。そのため、簡易迅速かつ強固にし
かも基板を損傷することなく経済的に安価な半導
体用パツケージ基板を提供することができる。
As described above, according to the present invention, conductor pins are inserted and inserted into a board made of an organic resin material such as a glass epoxy board on which glass fibers are laminated parallel to the outline using an extremely simple structure called caulking. However, the reliability of the joint between the conductor pin and the board is not impaired. Therefore, it is possible to provide a semiconductor package substrate that is simple, quick, strong, and economically inexpensive without damaging the substrate.
第１図は本考案の半導体用パツケージ基板の斜
視図、第２図及び第３図のａ〜ｆは、導体ピンが
嵌入固着されたプリント配線板の上平面図、第４
図、第６図は導体ピンの上平面図、第５図、第７
図は導体ピンが嵌入固着されたプリント配線板の
縦断面図、第８図はスタンドオフピンの縦断面
図、第９図は、本考案の半導体用パツケージ基板
からなるパツケージをマザーボードに実装した状
態の縦断面図を示す。
１……導体ピン、２……プリント配線板、３…
…スルホール、４……鍔、５……鍔、６……半導
体搭載用凹部、７……導体回路、８……矢印、９
……半導体素子、１０……ボンデイングワイヤ
ー、１１……封止樹脂、１２……樹脂封止枠、１
３……マザーボード、１４……はんだ、１５……
扁平部（凸部）、１６……扁平部（凹部）。
FIG. 1 is a perspective view of the semiconductor package board of the present invention, FIGS.
Figure 6 is a top plan view of the conductor pin, Figure 5, Figure 7 is a top plan view of the conductor pin.
The figure is a vertical cross-sectional view of a printed wiring board with conductor pins inserted and fixed, Figure 8 is a vertical cross-sectional view of standoff pins, and Figure 9 is a state in which a package made of the semiconductor package substrate of the present invention is mounted on a motherboard. A vertical cross-sectional view is shown. 1... Conductor pin, 2... Printed wiring board, 3...
... Through hole, 4 ... Tsuba, 5 ... Tsuba, 6 ... Semiconductor mounting recess, 7 ... Conductor circuit, 8 ... Arrow, 9
... Semiconductor element, 10 ... Bonding wire, 11 ... Sealing resin, 12 ... Resin sealing frame, 1
3...Motherboard, 14...Solder, 15...
Flat part (convex part), 16...Flat part (concave part).
Claims (1)
した有機系樹脂素材からなるプリント配線板
と、金属線の直径よりも幅の広い扁平部を持つ
導体ピンとよりなると共に、該導体ピンの扁平
部が上記プリント配線板に設けられた該扁平部
の幅よりも小さい直径のスルホールに嵌入固着
されている半導体用パツケージ基板であつて、 かつ、前記導体ピンにおける扁平部の扁平面
の延長線は、プリント配線板の外形線である横
方向と縦方向のいずれにも平行にならないよう
に嵌入固着されていることを特徴とする半導体
用パツケージ基板。 ２ 前記延長線上で隣接しあう２本の導体ピンに
おいて、一方の導体ピンがなす前記延長線と他
方の導体ピンがなす前記延長線とが、互いに略
直交するように配置されていることを特徴とす
る実用新案登録請求の範囲第１項記載の半導体
用パツケージ基板。 ３ 前記導体ピンには、その扁平部の下部近辺に
前記金属線の直径より大きい鍔が形成されてお
り、当該鍔がプリント配線板表面に係止されて
いることを特徴とする実用新案登録請求の範囲
第１項記載の半導体用パツケージ基板。 ４ 前記導体ピンには、前記鍔の下部に別の鍔が
形成されていることを特徴とする実用新案登録
請求の範囲第３項記載の半導体用パツケージ基
板。 ５ 前記別の鍔の形状は、当該半導体用パツケー
ジ基板を実装するプリント配線板の方向から見
て楕円形であることを特徴とする実用新案登録
請求の範囲第４項記載の半導体用パツケージ基
板。 ６ 前記導体ピンの両端は、曲面を形成している
ことを特徴とする実用新案登録請求の範囲第１
項記載の半導体用パツケージ基板。 ７ 前記導体ピンの表面は、プリント配線板表面
に形成された回路表面の金属層とは異なる金属
層で被覆されていることを特徴とする実用新案
登録請求の範囲第１項記載の半導体用パツケー
ジ基板。 ８ 前記半導体用パツケージ基板の形状は、ピン
グリツドアレー状であることを特徴とする実用
新案登録請求の範囲第１項、第２項、第３項、
第４項、第５項、第６項あるいは第７項記載の
半導体用パツケージ基板。[Claims for Utility Model Registration] 1. Consisting of a printed wiring board made of an organic resin material with glass fibers laminated parallel to the outline, and a conductor pin having a flat part wider than the diameter of the metal wire. and a semiconductor package substrate, wherein the flat part of the conductor pin is fitted into and fixed to a through hole provided in the printed wiring board and having a diameter smaller than the width of the flat part, and the flat part of the conductor pin A semiconductor package substrate characterized in that the extended line of the flat surface of the printed wiring board is fitted and fixed so that it is not parallel to either the horizontal direction or the vertical direction, which is the outline of the printed wiring board. 2. Two conductor pins adjacent to each other on the extension line are arranged so that the extension line formed by one conductor pin and the extension line formed by the other conductor pin are substantially perpendicular to each other. A semiconductor package substrate according to claim 1 of the utility model registration claim. 3. A request for registration of a utility model characterized in that the conductor pin has a flange larger in diameter than the metal wire formed near the bottom of the flat part, and the flange is latched to the surface of the printed wiring board. A semiconductor package substrate according to item 1. 4. The semiconductor package substrate according to claim 3, wherein the conductor pin has another flange formed at a lower part of the flange. 5. The semiconductor package board according to claim 4, wherein the shape of the other flange is elliptical when viewed from the direction of the printed wiring board on which the semiconductor package board is mounted. 6 Utility model registration claim 1, characterized in that both ends of the conductor pin form curved surfaces.
A package substrate for semiconductors as described in Section 1. 7. The semiconductor package according to claim 1, wherein the surface of the conductor pin is coated with a metal layer different from the metal layer on the surface of the circuit formed on the surface of the printed wiring board. substrate. 8. Utility model registration claims 1, 2 and 3, characterized in that the semiconductor package substrate has a pin grid array shape;
A semiconductor package substrate according to item 4, 5, 6, or 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985065541U JPH0331086Y2 (en) | 1985-04-30 | 1985-04-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985065541U JPH0331086Y2 (en) | 1985-04-30 | 1985-04-30 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61182039U JPS61182039U (en) | 1986-11-13 |
| JPH0331086Y2 true JPH0331086Y2 (en) | 1991-07-01 |
Family
ID=30597629
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985065541U Expired JPH0331086Y2 (en) | 1985-04-30 | 1985-04-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0331086Y2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0815201B2 (en) * | 1987-05-18 | 1996-02-14 | イビデン株式会社 | Semiconductor mounting board |
| US8378231B2 (en) * | 2008-07-31 | 2013-02-19 | Ibiden Co., Ltd. | Semiconductor device and method for manufacturing the same |
-
1985
- 1985-04-30 JP JP1985065541U patent/JPH0331086Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61182039U (en) | 1986-11-13 |
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