JPH03277171A - High power factor rectifying circuit - Google Patents

High power factor rectifying circuit

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Publication number
JPH03277171A
JPH03277171A JP7430390A JP7430390A JPH03277171A JP H03277171 A JPH03277171 A JP H03277171A JP 7430390 A JP7430390 A JP 7430390A JP 7430390 A JP7430390 A JP 7430390A JP H03277171 A JPH03277171 A JP H03277171A
Authority
JP
Japan
Prior art keywords
capacitor
triac
current
period
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7430390A
Other languages
Japanese (ja)
Other versions
JP2712736B2 (en
Inventor
Atsushi Okubo
温 大久保
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP2074303A priority Critical patent/JP2712736B2/en
Publication of JPH03277171A publication Critical patent/JPH03277171A/en
Application granted granted Critical
Publication of JP2712736B2 publication Critical patent/JP2712736B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PURPOSE:To improve power factor by providing a trigger pulse signal to a control element such as a triac at every zero cross point of an AC source voltage and bringing the control element into conducting state thereby shortening the unconducted interval and increasing the conduction amount. CONSTITUTION:A pulse TP having two states of H and L, produced at every zero cross point of AC input voltage Va, is a trigger pulse signal for a triac 6. When the triac 6 is conducted by the trigger pulse signal TP at the starting time point of the interval Al in an interval 1, for example, a capacitor current Icr flows through a capacitor 5 the triac 6 an AC power supply 1 a reactor 2 the capacitor 5 when the charging voltage Vcr is negative in a preceding section. Consequently, unconducted state of current la is eliminated in the intervals A1, A2 and the phase is advanced.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は高力率のコンデンサ入力形整流回路に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a high power factor capacitor input type rectifier circuit.

〔従来の技術〕[Conventional technology]

従来のこの種のコンデンサ入力形整流回路としては第3
図の回路図に例示するものが知られている。第4図は第
3図に示す回路の動作波形図である。
This is the third conventional capacitor input type rectifier circuit of this type.
The circuit shown in the circuit diagram in the figure is known. FIG. 4 is an operational waveform diagram of the circuit shown in FIG. 3.

第3図は単相全波整流の場合を示すものであり、1は交
流電源、2はリアクトル、3は交流入力端子T ml+
 TmZと直流出力端子Ta1. Ta□とを備えダイ
オードD1〜D4より成る整流ダイオードブリッジ、4
は平滑コンデンサである。なお図示符号子、−はそれぞ
れ正、負電圧極性を示す。
Figure 3 shows the case of single-phase full-wave rectification, where 1 is the AC power supply, 2 is the reactor, and 3 is the AC input terminal Tml+.
TmZ and DC output terminal Ta1. A rectifying diode bridge comprising diodes D1 to D4, 4
is a smoothing capacitor. Note that the symbols - in the drawings indicate positive and negative voltage polarities, respectively.

以下第4図に従い第3図に示す回路の動作を説明する。The operation of the circuit shown in FIG. 3 will be explained below with reference to FIG.

第4図に示す期間Iは交流電源1の電圧■、が正の期間
を示す。該期間I中の期間AIにおいて平滑コンデンサ
4の端子電圧vcは該期間Iに先立つ期間における充電
による残留電荷のため前記電源電圧■1より高く、従っ
て交流電源1から前記整流ブリッジ3への電流11の流
入はない。次に、前記期間I中の期間B+は前記両電圧
■、とV、との関係が■、〉VCの如く反転する時点よ
り開始され、従って前記電流1.は、交流電源1→リア
クトル2→ダイオードD、→平滑コンデンサ4−ダイオ
ードD4=交流電源1の如く通電する。また前記期間B
+においてはその途中から前記電圧関係がV、<V、の
如く再反転するが、前記電流1.はりアクドル2の蓄積
エネルギ放出により前記期間B+の略終了時点まで続流
する。また図示期間■は前記電圧■、が負となる期間で
あり、該期間中の各期間A2とB2とにおける動作は前
記期間Iの場合と同様に行われ、図示の如く極性反転の
電流波形が得られる。何れにせよ、例えば前記リアクト
ル2を設けず、前記期間B、或いはB8の進行途中にお
ける前記両電圧■、とvcとの電圧大小関係再反転時点
で前記電流I。
A period I shown in FIG. 4 indicates a period in which the voltage 2 of the AC power supply 1 is positive. During the period AI of the period I, the terminal voltage vc of the smoothing capacitor 4 is higher than the power supply voltage 1 due to the residual charge due to charging in the period preceding the period I, and therefore the current 11 from the AC power supply 1 to the rectifying bridge 3 There is no influx of Next, the period B+ in the period I starts from the point in time when the relationship between the voltages ■ and V is reversed as shown in ■,>VC, and therefore the current 1. The power is supplied as follows: AC power supply 1 -> reactor 2 -> diode D, -> smoothing capacitor 4 - diode D4 = AC power supply 1. Also, the period B
At +, the voltage relationship reverses again as V, <V, but the current 1. Due to the release of the stored energy of the beam accelerator 2, the current continues until approximately the end of the period B+. In addition, the illustrated period (■) is a period in which the voltage (2) is negative, and the operations in each period A2 and B2 during this period are performed in the same manner as in the period I, and the current waveform with polarity inversion as shown in the figure is can get. In any case, for example, when the reactor 2 is not provided and the voltage magnitude relationship between the two voltages (1) and VC is reversed again during the period B or B8, the current I.

が通電停止する場合に比しては、整流回路の力率改善が
図られていた。
The power factor of the rectifier circuit was improved compared to the case where the current supply was stopped.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしながら上記の如き従来技術による整流回路におい
ては、交流電源からの入力電流に関しその各周期中に第
4図に示す期間A+ 、Atの如き通電停止期間を有し
、該雨期間の存在が整流回路の力率低下の原因となって
いた。
However, in the rectifier circuit according to the prior art as described above, the input current from the AC power source has a power-off period such as the period A+ and At shown in FIG. This caused a decrease in the power factor.

以上に鑑み本発明は、前記の如き交流入力電流の通電停
止期間の短縮と通電量の増大とによりその力率の改善を
図った高力率整流回路の提供を目的とするものである。
In view of the above, it is an object of the present invention to provide a high power factor rectifier circuit that improves the power factor by shortening the period during which AC input current is not supplied and increasing the amount of current supplied.

〔課題を解決するための手段〕[Means to solve the problem]

上記目的を達成するために、本発明の高力率整流回路は
、その直流出力側に平滑コンデンサを有するコンデンサ
入力形の整流回路において、交流電源と整流ダイオード
ブリッジ間に直列にリアクトルを接続すると共に、前記
整流ダイオードブリフジの交流入力端子相互間にコンデ
ンサとトライチック等の双方向性のトリガ制御素子との
直列回路を接続し、且つ該トライチック等の制?1B素
子を交流電源電圧が零となる時点毎に1つのトリガパル
ス信号にて点弧させるものとする。
In order to achieve the above object, the high power factor rectifier circuit of the present invention is a capacitor input type rectifier circuit having a smoothing capacitor on the DC output side. , A series circuit consisting of a capacitor and a bidirectional trigger control element such as a tritic is connected between the AC input terminals of the rectifier diode bridge, and the tritic is controlled? It is assumed that the 1B element is fired by one trigger pulse signal every time the AC power supply voltage becomes zero.

〔作用〕[Effect]

前記の如くコンデンサ入力形整流回路においては、その
直流出力側の平滑コンデンサの端子電圧vcが前記整流
回路への交流入力電圧v3より高くなる期間に対応して
該整流回路への交流入力電流1.の不通状態が発生し、
該交流入力電流の波形は不連続波となる。
As described above, in the capacitor input type rectifier circuit, the AC input current 1. An outage occurred,
The waveform of the AC input current becomes a discontinuous wave.

一方前記整流回路の力率はその交流入力電圧V、と交流
入力電流1.の等価正弦波換算電流11.とのなす位相
角によって決定される。
On the other hand, the power factor of the rectifier circuit is determined by its AC input voltage V and AC input current 1. Equivalent sinusoidal current of 11. It is determined by the phase angle between

従って前記の如き整流回路の力率改善を図るためには、
前記の電圧関係v、〈vcの成立する期間においてもな
お交流電源からの交流電流11の適当量の継続通電を図
り、前記の力率改善に効果的な前記電圧V、の電圧零時
点に続く前記V、〈Vc期間における前記電流1.の確
保を行って前記等価正弦波電流1 msの前記電圧V、
に対してなす位相角の低減を図る必要がある。
Therefore, in order to improve the power factor of the rectifier circuit as described above,
An appropriate amount of alternating current 11 from the alternating current power supply is continued to be applied even during the period in which the voltage relationship v, <vc is established, and the voltage V, which is effective for improving the power factor, continues to be energized after the voltage becomes zero. The current 1 during the V, <Vc period. The voltage V of the equivalent sinusoidal current of 1 ms is ensured,
It is necessary to reduce the phase angle with respect to the

上記の如き力率改善のために、従来の整流回路において
は既述の如く交流電源と整流ブリフジ間に直列にリアク
トルを接続し、該リアクトルの蓄積エネルギの放出によ
り前記の如き交流電流I。
In order to improve the power factor as described above, in a conventional rectifier circuit, a reactor is connected in series between the AC power source and the rectifier bridge as described above, and the energy stored in the reactor is released to reduce the AC current I as described above.

の継続通電を図っていたが、本発明においては、更に前
記整流ブリフジの交流電圧入力端子相互間にコンデンサ
とトライアック等の双方向性制御素子との直列回路を接
続し、前記電圧V、の電圧零時点毎にトリガパルス信号
を与えて前記制御素子を導通状態となして前記のりアク
ドルと追加コンデンサとを直列接続状態となして前記交
流電源に接続し、前記電圧V、の電圧零時点では既に始
っていた前記V、<V。期間において適当量に選定され
た前記リアクトルと追加コンデンサとの直列回路からの
共振電流を前記交流電源に通電させ、前記の如く等価正
弦波電流1.。の前記電圧■、に対する位相角の低減を
図り、以って前記整流器力率の一層の改善を図っている
However, in the present invention, a series circuit of a capacitor and a bidirectional control element such as a triac is further connected between the AC voltage input terminals of the rectifying bridge, and the voltage of the voltage V is A trigger pulse signal is applied at each zero time point to bring the control element into a conductive state, and the glue handle and the additional capacitor are connected in series and connected to the AC power supply, so that at the time when the voltage V is zero, the control element is made conductive. The above V, which had started, <V. During the period, a resonant current from the series circuit of the reactor and the additional capacitor selected in an appropriate amount is applied to the AC power supply, and the equivalent sine wave current 1. . By reducing the phase angle with respect to the voltage (1), the rectifier power factor is further improved.

〔実施例〕〔Example〕

以下本発明の実施例を図面により説明する。第1図は本
発明の実施例を示す回路図、第2図は第1図に示す回路
の動作波形図である。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is an operating waveform diagram of the circuit shown in FIG.

なお第1図においては第3図に示す従来技術の実施例の
場合と同一機能の構成要素に対しては同一の表示符号を
附している。
In FIG. 1, the same reference numerals are given to components having the same functions as in the prior art embodiment shown in FIG. 3.

第1図は前記第3図の回路構成に対し、コンデンサ5と
トライアック6との直列接続を整流ダイオードブリッジ
3の交流入力端子7m+とT、tとの間に追加接続した
ものを示す。
FIG. 1 shows the circuit configuration of FIG. 3 in which a series connection of a capacitor 5 and a triac 6 is additionally connected between the AC input terminal 7m+ of the rectifier diode bridge 3 and T, t.

以下第2図に従い第1図に示す回路の動作を説明する。The operation of the circuit shown in FIG. 1 will be explained below with reference to FIG.

なお第2図において期間!、  ff、 A、 。In addition, in Figure 2, the period! , ff, A,.

At 、B+ 、Bt及び電圧V、、Ve更に電流■、
とはそれぞれ前記第4図の場合と同一の内容を有するも
のであり、以下特に前記コンデンサ5とトライアック6
との追加接続部につき説明する。
At , B+ , Bt and voltage V, , Ve and current ■,
have the same content as in the case of FIG.
An explanation will be given of the additional connection section.

第2図において、交流入力電圧■、の電圧零時点毎に作
られHとLの2状態をとるパルスTPは前記トライアッ
ク6に対するトリガパルス信号である0例えば今、期間
I中の期間A、の開始時点でトリガパルス信号TPによ
ってトライアック6を導通状態となせば、その充電電圧
vc、、が先行する期間において図示の如く負となされ
ている前記コンデンサ5を電源としてコンデンサ5−ト
ライアック6−交流電源1−リアクトル2−コンデンサ
5の経路でコンデンサ電流1 crが通電する。該電流
はりアクドル2とコンデンサ5とによる直列共振電流で
あり前記電圧V、の前記期間A、中の加電を受けたコン
デンサ5の充電電圧verを電源電圧として通電するが
、該電圧y crの極性反転定値化と共に図示の如く消
滅する。しかしながら前記電流1 crは交流電源1を
通過するものであり、前記期間AIにおける前記交流電
流1.を構成するものとなる。またトライアック6は前
記電流1c、、の消滅と共に自然消弧するため期間I中
のB+期間においてはコンデンサ5とトライアック6と
の前記直列接続は解除され、実質の回路構成は第3図の
場合と同一になり、従って前記B1期間における交流電
流I noは第4図に示す交流電流■1と同一波形とな
る。
In FIG. 2, a pulse TP which is generated every time the AC input voltage becomes zero and takes two states of H and L is a trigger pulse signal for the triac 6. For example, in period A of period I, If the triac 6 is brought into conduction by the trigger pulse signal TP at the start time, the charging voltage vc, . A capacitor current of 1 cr flows through the path 1-reactor 2-capacitor 5. The current is a series resonant current caused by the accelerator 2 and the capacitor 5, and the charging voltage ver of the capacitor 5 applied during the period A of the voltage V is applied as the power supply voltage. As the polarity is reversed and the value becomes constant, it disappears as shown in the figure. However, the current 1 cr passes through the AC power source 1, and the AC current 1 cr during the period AI. It will constitute the following. Furthermore, since the triac 6 naturally extinguishes as the currents 1c, , disappear, the series connection between the capacitor 5 and the triac 6 is canceled during the B+ period of period I, and the actual circuit configuration is the same as that shown in FIG. Therefore, the AC current Ino during the B1 period has the same waveform as the AC current 1 shown in FIG.

なお期間■中の各期間At 、Bzにおいても前記期間
Iの場合に準じて動作し図示の如き各部動作波形が得ら
れる。
It should be noted that during each period At and Bz during period (3), operations are performed in the same manner as in period I, and the operation waveforms of each part as shown in the figure are obtained.

前記電流1.。とI elFとの合成電流1.は交流電
源1より供給される総合の交流電流であり、該電流I、
の等価正弦波電流1.、の前記電圧■、に対してなす位
相角が本発明による整流回路の総合力率角となるもので
あるが、図示の如く期間AI+A2における電流1.の
王道状態は解消され且つ適度の電流量の通電があるため
前記電流1 meの位相は進み方向に改善されて前記電
圧■、に対する位相角は低減され、その結果所要の整流
回路総合の力率の改善がなされることになる。
Said current 1. . Combined current of IelF and IelF1. is the total alternating current supplied from the alternating current power supply 1, and the current I,
Equivalent sinusoidal current of 1. The phase angle formed with respect to the voltage . Since the classic condition of 1 is eliminated and a suitable amount of current is passed, the phase of the current 1 me is improved in the leading direction, and the phase angle with respect to the voltage 2 is reduced, resulting in the required overall power factor of the rectifier circuit. Improvements will be made.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、交流電源より直列リアクトルを介して
給電され整流ブリッジの交流入力側にてコンデンサとト
ライアック等の双方向性制御素子とから成る直列回路を
該整流ブリッジに並列に接続し、且つ交流電源電圧の零
電圧時点毎に前記制御素子にトリガパルス信号を与えて
該制御素子を導通状態となすことにより、前記交流電源
より給電される交流電流波形を改善し、簡易且つ安価に
高力率の整流回路を得ることができる。
According to the present invention, a series circuit including a capacitor and a bidirectional control element such as a triac is connected in parallel to the rectifier bridge at the AC input side of the rectifier bridge, which is supplied with power from an AC power source via a series reactor, and By applying a trigger pulse signal to the control element to bring the control element into conduction every time the AC power supply voltage reaches zero voltage, the waveform of the AC current supplied from the AC power supply is improved, and high power can be obtained easily and inexpensively. A rectifier circuit can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の実施例を示す回路図、第2図は第1図
回路の動作波形図、第3図は従来技術の実施例を示す回
路図、第4図は第3図回路の動作波形図である。 1・・・交流電源、2・・・リアクトル、3・・・整流
ダイオードブリッジ、4・・・平滑コンデンサ、5・・
・コンデンサ、6・・・トライアック、D I−D a
・・・ダイオード、TRI、 Tmz・・・交流入力端
子、T□I ’raz・・・直流出力端子。 整直タイオードブ′リッジ゛ 3 第 図 第3図
Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is an operation waveform diagram of the circuit shown in Fig. 1, Fig. 3 is a circuit diagram showing an embodiment of the prior art, and Fig. 4 is a circuit diagram of the circuit shown in Fig. 3. It is an operation waveform diagram. 1... AC power supply, 2... Reactor, 3... Rectifier diode bridge, 4... Smoothing capacitor, 5...
・Capacitor, 6...Triac, DI-D a
...Diode, TRI, Tmz...AC input terminal, T□I'raz...DC output terminal. Straightening diode bridge 3 Figure 3

Claims (1)

【特許請求の範囲】[Claims] 1)その直流出力側に平滑コンデンサを有するコンデン
サ入力形の整流回路において、交流電源と整流ダイオー
ドブリッジ間に直列にリアクトルを接続すると共に、前
記整流ダイオードブリッジの交流入力端子相互間にコン
デンサとトライアック等の双方向性のトリガ制御素子と
の直列回路を接続し、且つ該トライアック等の制御素子
を交流電源電圧が零となる時点毎に1つのトリガパルス
信号にて点弧させることを特徴とする高力率整流回路。
1) In a capacitor input type rectifier circuit that has a smoothing capacitor on its DC output side, a reactor is connected in series between the AC power supply and the rectifier diode bridge, and a capacitor and a triac, etc. are connected between the AC input terminals of the rectifier diode bridge. A series circuit is connected to a bidirectional trigger control element of the triac, and the control element such as the triac is fired by one trigger pulse signal every time the AC power supply voltage becomes zero. Power factor rectifier circuit.
JP2074303A 1990-03-23 1990-03-23 High power factor rectifier circuit Expired - Lifetime JP2712736B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2074303A JP2712736B2 (en) 1990-03-23 1990-03-23 High power factor rectifier circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2074303A JP2712736B2 (en) 1990-03-23 1990-03-23 High power factor rectifier circuit

Publications (2)

Publication Number Publication Date
JPH03277171A true JPH03277171A (en) 1991-12-09
JP2712736B2 JP2712736B2 (en) 1998-02-16

Family

ID=13543228

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2074303A Expired - Lifetime JP2712736B2 (en) 1990-03-23 1990-03-23 High power factor rectifier circuit

Country Status (1)

Country Link
JP (1) JP2712736B2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5532422A (en) * 1978-08-25 1980-03-07 Fuji Electric Co Ltd Semiconductor converter for electric vehicle
JPS5588576A (en) * 1978-12-27 1980-07-04 Fuji Electric Co Ltd Semiconductor converter

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5532422A (en) * 1978-08-25 1980-03-07 Fuji Electric Co Ltd Semiconductor converter for electric vehicle
JPS5588576A (en) * 1978-12-27 1980-07-04 Fuji Electric Co Ltd Semiconductor converter

Also Published As

Publication number Publication date
JP2712736B2 (en) 1998-02-16

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