JPH03276747A - Lead frame - Google Patents

Lead frame

Info

Publication number
JPH03276747A
JPH03276747A JP7808590A JP7808590A JPH03276747A JP H03276747 A JPH03276747 A JP H03276747A JP 7808590 A JP7808590 A JP 7808590A JP 7808590 A JP7808590 A JP 7808590A JP H03276747 A JPH03276747 A JP H03276747A
Authority
JP
Japan
Prior art keywords
island
layer
islands
power source
stitches
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7808590A
Other languages
Japanese (ja)
Inventor
Natsuko Hamada
濱田　奈津子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP7808590A priority Critical patent/JPH03276747A/en
Publication of JPH03276747A publication Critical patent/JPH03276747A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To eliminate fluctuations of a power source and to output stable characteristics of an IC by providing an island having a 2-layer structure formed by interposing to hold an insulating layer between first and second layers, hanging pins provided by connecting to the islands of the first and second layers, and bonding stitches at the peripheries of the islands of the first and second layers. CONSTITUTION:An island having a 2-layer structure formed by interposing an insulting layer 7 between the island 1 of the first layer and the island 2 of the second layer is supported by a hanging pin 8 connected to the island 1 and a hanging pin 9 connected to the island 2, and parts of the islands 1, 2 near the pins 8, 9 protrude to provide stitches 4, 6. Thus, a VCC power source and GND power source of a semiconductor chip to be placed on the islands by using the stitches 4, 6 and inner leads 3, 5 are connected, can be divided and eliminate large current capacity wirings. Accordingly, fluctuations of the power source and a decrease in characteristics due to noise are prevented to easily lay out the wirings.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はリードフレームに関する。[Detailed description of the invention] [Industrial application field] The present invention relates to lead frames.

〔従来の技術〕[Conventional technology]

従来のリードフレームは第４図に示すように、半導体チ
ップを搭載するためのアイランド１３が吊りピン１４で
支持され、アイランド１３の周囲に内部リードの１５が
配置され、吊りピン１４の隣りの内部リード３が支持体
１０で吊りピン１４に接続されている。ここで、アイラ
ンド１３と半導体チップ上のパッド電極とのボンディン
グは不可能な構造になっている。半導体チップ上のパッ
ド電極と内部リード１５はＡｕ線又はＡｌ線によって接
続されているが、電源（ＶＣＣとＧ　Ｎ　Ｄ　、、）パ
ッドは半導体チップ上の両端のどちらかに１つずつしか
なく配線の大電流容量化を必要とし、配線レイアウトが
難しい。即ち、電源のゆれによるノイズの発生の為にＩ
Ｃ特性に悪い影響を与える可能性が高くなるという問題
点がある。As shown in FIG. 4, in the conventional lead frame, an island 13 for mounting a semiconductor chip is supported by hanging pins 14, internal leads 15 are arranged around the island 13, and internal leads 15 are placed next to the hanging pins 14. A lead 3 is connected to a hanging pin 14 by a support 10. Here, the structure is such that bonding between the island 13 and the pad electrode on the semiconductor chip is impossible. The pad electrodes on the semiconductor chip and the internal leads 15 are connected by Au wires or Al wires, but there is only one power supply (VCC, GND,...) pad at either end of the semiconductor chip, and there is no wiring. requires a large current capacity, making wiring layout difficult. In other words, I
There is a problem that there is a high possibility that the C characteristics will be adversely affected.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述したリードフレームは、ＶＣＣ電源パッドとＧＮＤ
電源パッドをチップ上に１つずつしか乗せることが出来
ないので、チップ全体に電源の配線を引っばらなくては
ならないが、電源のゆれをなくす為に、基本的には配線
幅を太くする必要がある。しかし、搭載ケースのサイズ
は決定されているために、チップサイズには限度があり
電源の配線幅に充分な考慮をする必要がある。又、チッ
プサイズの限界の為に電源の配線幅にも限界があり、安
定した電源を供給することが出来ず、ＩＣの特性に悪影
響を与えるという欠点がある。The lead frame mentioned above has VCC power pad and GND
Since power pads can only be placed one at a time on the chip, the power supply wiring must be stretched across the entire chip, but in order to eliminate fluctuations in the power supply, it is basically necessary to increase the width of the wiring. There is. However, since the size of the mounting case is determined, there is a limit to the chip size, and sufficient consideration must be given to the width of the power supply wiring. Further, due to the limit of chip size, there is also a limit to the wiring width of the power supply, making it impossible to supply a stable power supply, which has the drawback of adversely affecting the characteristics of the IC.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のリードフレームは、第１層と第２層の眉間に絶
縁層を挾んで形成した２層構造のアイランドと、前記第
１層及び第２層のアイランドのそれぞれに接続して設け
た吊ピンと、前記第１層及び第２層のアイランドの周縁
部に設けたボンディング用ステッチとを有する。The lead frame of the present invention has a two-layer island formed by sandwiching an insulating layer between the eyebrows of the first layer and the second layer, and a suspension provided connected to each of the islands of the first layer and the second layer. It has a pin, and bonding stitches provided on the peripheral edges of the islands of the first layer and the second layer.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は本発明の一実施例の平面図、第２図は第１図の
部分斜視図である。FIG. 1 is a plan view of an embodiment of the present invention, and FIG. 2 is a partial perspective view of FIG. 1.

第１図及び第２図に示すように、第１層のアイランド１
と第２層のアイランド２の眉間に絶縁層７を挾んで形成
した２層構造のアイランド１に接続した吊りピン８及び
アイランド２に接続した吊すビン９により支持し、吊り
ピン８と隣りの内部リード３との間及び吊りピンつと隣
の内部リード５との間をそれぞれ支持体１０により接続
し、吊ピン８の近傍のアイランド１及び吊りピン９近傍
のアイランド２の一部を突出してステップ４及びステッ
チ６を設けている。As shown in FIGS. 1 and 2, the island 1 of the first layer
It is supported by a hanging pin 8 connected to the island 1 of a two-layer structure formed by sandwiching an insulating layer 7 between the eyebrows of the island 2 of the second layer, and a hanging bottle 9 connected to the island 2. In step 4, the lead 3 and the hanging pin 8 are connected to the adjacent internal lead 5 using supports 10, and a part of the island 1 near the hanging pin 8 and a part of the island 2 near the hanging pin 9 are protruded. and stitch 6 are provided.

このように、ステッチ４．６及び内部リード３．５を使
用してアイランド上に搭載する半導体チップの■ＣＣ電
源又はＧＮＤ電源を接続することにより、半導体チップ
上の■ＣＣ電源又はＧＮＤ電源配線の分割を可能とし、
大電流容量配線を不要にできるため電源のゆれやノイズ
による特性の低下を防止し、配線のレイアウトを容易に
することができる。In this way, by connecting the ■CC power supply or GND power supply of the semiconductor chip mounted on the island using the stitch 4.6 and the internal lead 3.5, the ■CC power supply or GND power supply wiring on the semiconductor chip can be connected. allows for division,
Since large current capacity wiring is not required, deterioration of characteristics due to power fluctuations and noise can be prevented, and wiring layout can be simplified.

第３図は本発明の第２の実施例の平面図である。FIG. 3 is a plan view of a second embodiment of the invention.

第３図に示すように、吊りピン８，９を設けた辺に挾ま
れた対向する２辺のそれぞれのアイランド１にステッチ
ｌｌａ、ｌｌｂを設け、アイランド２にステッチ１２ａ
、１２ｂを設けている以外は第１の実施例と同様の構成
を有しており、多くの電源パッドとボンディングできる
ため、電源電圧のゆれをなくし、安定した電源電圧を供
給できる利点がある。As shown in FIG. 3, stitches lla and llb are provided on each island 1 on two opposing sides sandwiched between the sides on which the hanging pins 8 and 9 are provided, and stitches 12a and 12a are provided on island 2.
, 12b are provided, and since it can be bonded to many power supply pads, it has the advantage of eliminating fluctuations in the power supply voltage and supplying a stable power supply voltage.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、第１層と第２層のアイラ
ンドの眉間に絶縁層を挾んで形成した２層構造のアイラ
ンドの第１層のアイランドと第２層のアイランドをそれ
ぞれ例えばＶＣＣ電源配線又はＧＮＤ電源配線として使
用でき、半導体チップ上の電源パッドとボンディングす
る為のステッチをアイランドの周縁部に設けることによ
り、電源のゆれをなくし、安定したＩＣの特性を出す効
果がある。これは特にハイスピードを要求されるメモリ
ＩＣにおいては重要な問題である。As explained above, the present invention has a two-layer structure in which an insulating layer is sandwiched between the eyebrows of the first and second layer islands. It can be used as wiring or GND power supply wiring, and by providing stitches on the periphery of the island for bonding with power supply pads on the semiconductor chip, it has the effect of eliminating fluctuations in the power supply and providing stable IC characteristics. This is a particularly important problem in memory ICs that require high speed.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の第１の実施例の平面図、第２図は第１
図の部分斜視図、第３図は本発明の第２の実施例の平面
図、第４図は従来のリードフレームの平面図である。 １・・・第１層のアイランド、２・・・第２層のアイラ
ンド、３・・・内部リード、４・・・ステッチ、５・・
・内部リード、６・・・ステッチ、７・・・絶縁層、８
，９・・・吊りピン、１０・・・支持体、ｌｌａ、１］
、ｂ。 １２ａ、１２ｂ・・・ステッチ、１３・・・アイランド
、１４・・・吊りピン、１５・・・内部リード。FIG. 1 is a plan view of the first embodiment of the present invention, and FIG. 2 is a plan view of the first embodiment of the present invention.
3 is a plan view of a second embodiment of the present invention, and FIG. 4 is a plan view of a conventional lead frame. 1... Island in the first layer, 2... Island in the second layer, 3... Internal lead, 4... Stitch, 5...
・Internal lead, 6... Stitch, 7... Insulating layer, 8
, 9... Hanging pin, 10... Support, lla, 1]
,b. 12a, 12b... Stitch, 13... Island, 14... Hanging pin, 15... Internal lead.

Claims (1)

【特許請求の範囲】[Claims] 　第１層と第２層の層間に絶縁層を挾んで形成した２層
構造のアイランドと、前記第１層及び第２層のアイラン
ドのそれぞれに接続して設けた吊ピンと、前記第１層及
び第２層のアイランドの周縁部に設けたボンディング用
ステッチとを有することを特徴とするリードフレーム。A two-layer island formed by sandwiching an insulating layer between the first layer and the second layer; a hanging pin connected to each of the first and second layer islands; A lead frame characterized by having a bonding stitch provided at a peripheral edge of a second layer island.
JP7808590A 1990-03-27 1990-03-27 Lead frame Pending JPH03276747A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7808590A JPH03276747A (en) 1990-03-27 1990-03-27 Lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7808590A JPH03276747A (en) 1990-03-27 1990-03-27 Lead frame

Publications (1)

Publication Number Publication Date
JPH03276747A true JPH03276747A (en) 1991-12-06

Family

ID=13652010

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7808590A Pending JPH03276747A (en) 1990-03-27 1990-03-27 Lead frame

Country Status (1)

Country Link
JP (1) JPH03276747A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996015555A1 (en) * 1994-11-10 1996-05-23 Micron Technology, Inc. Multi-layer lead frame for a semiconductor device
US5623162A (en) * 1994-10-27 1997-04-22 Nec Corporation Lead frame having cut-out wing leads
US5965936A (en) * 1997-12-31 1999-10-12 Micron Technology, Inc. Multi-layer lead frame for a semiconductor device
US6054754A (en) * 1997-06-06 2000-04-25 Micron Technology, Inc. Multi-capacitance lead frame decoupling device
US6104078A (en) * 1994-03-09 2000-08-15 Denso Corporation Design for a semiconductor device having elements isolated by insulating regions
US6114756A (en) * 1998-04-01 2000-09-05 Micron Technology, Inc. Interdigitated capacitor design for integrated circuit leadframes
US6472737B1 (en) 1998-01-20 2002-10-29 Micron Technology, Inc. Lead frame decoupling capacitor, semiconductor device packages including the same and methods

Cited By (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6104078A (en) * 1994-03-09 2000-08-15 Denso Corporation Design for a semiconductor device having elements isolated by insulating regions
US5623162A (en) * 1994-10-27 1997-04-22 Nec Corporation Lead frame having cut-out wing leads
US6307255B1 (en) 1994-11-10 2001-10-23 Micron Technology, Inc. Multi-layer lead frame for a semiconductor device
DE19581837T1 (en) * 1994-11-10 1997-10-02 Micron Technology Inc Multi-layer lead frame for a semiconductor device
US5734198A (en) * 1994-11-10 1998-03-31 Micron Technology, Inc. Multi-layer lead frame for a semiconductor device
KR100253028B1 (en) * 1994-11-10 2000-04-15 로데릭 더블류 루이스 Multi-layer lead frame for a semiconductor device
WO1996015555A1 (en) * 1994-11-10 1996-05-23 Micron Technology, Inc. Multi-layer lead frame for a semiconductor device
US6124630A (en) * 1994-11-10 2000-09-26 Micron Technology, Inc. Multi-layer lead frame for a semiconductor device
US6707136B2 (en) 1996-09-04 2004-03-16 Micron Technology, Inc. Multi-layer lead frame for a semiconductor device
US6515353B2 (en) 1996-09-04 2003-02-04 Micron Technology, Inc. Multi-layer lead frame for a semiconductor device
US6054754A (en) * 1997-06-06 2000-04-25 Micron Technology, Inc. Multi-capacitance lead frame decoupling device
US6184574B1 (en) 1997-06-06 2001-02-06 Micron Technology, Inc. Multi-capacitance lead frame decoupling device
US6310388B1 (en) 1997-06-06 2001-10-30 Micron Technology, Inc. Semiconductor die assembly having leadframe decoupling characters
US6504236B2 (en) 1997-06-06 2003-01-07 Micron Technology, Inc. Semiconductor die assembly having leadframe decoupling characters and method
US6781219B2 (en) 1997-06-06 2004-08-24 Micron Technology, Inc. Semiconductor die assembly having leadframe decoupling characters
US5965936A (en) * 1997-12-31 1999-10-12 Micron Technology, Inc. Multi-layer lead frame for a semiconductor device
US7071542B2 (en) 1998-01-20 2006-07-04 Micron Technology, Inc. Lead frame decoupling capacitor, semiconductor device packages including the same and methods
US6472737B1 (en) 1998-01-20 2002-10-29 Micron Technology, Inc. Lead frame decoupling capacitor, semiconductor device packages including the same and methods
US6515359B1 (en) 1998-01-20 2003-02-04 Micron Technology, Inc. Lead frame decoupling capacitor semiconductor device packages including the same and methods
US6717257B2 (en) 1998-01-20 2004-04-06 Micron Technology, Inc. Lead frame decoupling capacitor, semiconductor device packages including the same and methods
US6396134B2 (en) 1998-04-01 2002-05-28 Micron Technology, Inc. Interdigitated capacitor design for integrated circuit lead frames
US6531765B2 (en) 1998-04-01 2003-03-11 Micron Technology, Inc. Interdigitated capacitor design for integrated circuit lead frames and method
US6730994B2 (en) 1998-04-01 2004-05-04 Micron Technology, Inc. Interdigitated capacitor design for integrated circuit lead frames and methods
US6114756A (en) * 1998-04-01 2000-09-05 Micron Technology, Inc. Interdigitated capacitor design for integrated circuit leadframes
US6265764B1 (en) 1998-04-01 2001-07-24 Micron Technology, Inc. Interdigitated capacitor design for integrated circuit lead frames

Similar Documents

Publication Publication Date Title
US6858472B2 (en) Method for implementing selected functionality on an integrated circuit device
KR940001335A (en) Semiconductor integrated circuit device
JP2634516B2 (en) Manufacturing method of inverted IC, inverted IC, IC module
EP0590986B1 (en) Lead-on-chip lead frame
JPH03276747A (en) Lead frame
JPH02219254A (en) Semiconductor integrated circuit device
JPH10135400A (en) Semiconductor device
KR100202760B1 (en) Semiconductor device
JPH01124244A (en) Lead frame
JPH0685185A (en) Semiconductor integrated circuit device
JPH0521698A (en) Semiconductor device
JPH061801B2 (en) Lead frame
JPH0669276A (en) Semiconductor device
JPH01143246A (en) Semiconductor device
JPS59100550A (en) Semiconductor device
JPH0770666B2 (en) Package for mounting integrated circuit devices
JPH06232328A (en) Loc semiconductor device
JPH01145842A (en) Semiconductor device
JP2859360B2 (en) Semiconductor device, method of manufacturing semiconductor device, and mounting structure of semiconductor device
JP3025357B2 (en) Semiconductor device
JPH0455333B2 (en)
JPH09223758A (en) Semiconductor device
JP2522455B2 (en) Semiconductor integrated circuit device
JP3272079B2 (en) Semiconductor module
JPS6240752A (en) Semiconductor device