JPH03269265A - Power limitation detecting circuit - Google Patents
Power limitation detecting circuitInfo
- Publication number
- JPH03269265A JPH03269265A JP6891290A JP6891290A JPH03269265A JP H03269265 A JPH03269265 A JP H03269265A JP 6891290 A JP6891290 A JP 6891290A JP 6891290 A JP6891290 A JP 6891290A JP H03269265 A JPH03269265 A JP H03269265A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- output
- detected
- multiplier
- current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims abstract description 32
- 230000015556 catabolic process Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 102000004207 Neuropilin-1 Human genes 0.000 description 1
- 108090000772 Neuropilin-1 Proteins 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
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- Protection Of Static Devices (AREA)
- Emergency Protection Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
所定の制限範囲を測定電力が越えたか否かを検lJj
FJる電力制限検出回路に関し、より正確に回路破損不
具合を検出することを[1的どじ、
検出1−べさ電流を電圧に変換し”C検出する電流検出
手段と、検出すべき電圧と該電流検出手段の出力電圧と
を夫々乗りする乗算器と、該@Fi器の出力電圧と予め
設定した基準電圧とをレベル比較し、該基準電圧以上の
レベルの該乗算器の出力電圧入力時に制限検出信号を出
力する比較器とより構成する。[Detailed Description of the Invention] [Summary] Detects whether measured power exceeds a predetermined limit range.
Regarding FJ's power limit detection circuit, in order to more accurately detect circuit damage defects, we have developed a current detection means that converts the current into a voltage and detects the voltage to be detected. A multiplier that multiplies the output voltage of the current detection means and the output voltage of the @Fi device and a preset reference voltage are compared in level, and a limit is set when the output voltage of the multiplier is input at a level higher than the reference voltage. It consists of a comparator that outputs a detection signal.
本発明は電力制限検出回路に係り、特に所定の制限範囲
を測定電力が越えたか否かを検出する電力制限検出回路
に関する。The present invention relates to a power limit detection circuit, and more particularly to a power limit detection circuit that detects whether or not measured power exceeds a predetermined limit range.
増幅器の出力1〜ランジスタを破壊さ拷たり、劣化さけ
ることなく高信頼度で動作さUるために、出力]〜ラン
ジスタが安全動作領域(ASO>で動作するよう、負荷
電流などが制限範囲を越えたか否かを検出する必要があ
る。Amplifier output 1 - In order to operate with high reliability without damaging or deteriorating the transistor, the load current etc. must be within the limit range so that the transistor operates within the safe operating area (ASO). It is necessary to detect whether or not the limit has been exceeded.
第4図は従来の電流制限検出回路の一例の回路図を示り
゛。同図中、Trは増幅器の出力段のNPN1〜ランジ
スタ(以下、出力1〜ランジスタという)で、そのベー
スは入力端子1に接続され、そのコレクタは検出抵抗R
sに接続され、そのエミッタは負荷R1−に接続されて
いる9、また、検出抵抗R8の電源側端子は抵抗R1を
介して差動増幅器A1の非反転入力端子に接続され、検
出抵抗Rsと出力1〜ランジスタlrの]レクタとの接
続点は抵抗R2を介して差動増幅器A1の反転入力端子
に接続されている。更に、差動増幅器Δ1の出力端は出
力端子2に接続される一方、抵抗R4を介してA1の反
転入力端子に接続されている。また、差動増幅器A1の
非反転入力端子は抵抗R3を介して接地されている。FIG. 4 shows a circuit diagram of an example of a conventional current limit detection circuit. In the figure, Tr is an NPN1 transistor (hereinafter referred to as output 1 transistor) in the output stage of the amplifier, its base is connected to input terminal 1, and its collector is a detection resistor R.
9, whose emitter is connected to the load R1-, and the power supply side terminal of the detection resistor R8 is connected to the non-inverting input terminal of the differential amplifier A1 via the resistor R1, and the detection resistor R8 is connected to the non-inverting input terminal of the differential amplifier A1. The connection point between output 1 and the resistor of transistor lr is connected to the inverting input terminal of differential amplifier A1 via resistor R2. Further, the output terminal of the differential amplifier Δ1 is connected to the output terminal 2, and is also connected to the inverting input terminal of A1 via a resistor R4. Further, the non-inverting input terminal of the differential amplifier A1 is grounded via a resistor R3.
かかる構成の回路において、端子1に入力される情報信
号に応じて出力I・ランジスタl’rの]レクタ電流及
びエミッタ電流が変化する。出力1〜ランジスタTrの
]レクタ電流1cは負荷RLに流れるエミッタ電流と略
等しいから、検出抵抗Rsの両端には負荷R1−に流れ
る電流に比例した検出電圧Vs (= It−・Rs
)が発生り−る1゜この検出電圧Vsは抵抗R+ 、R
2を介して差動増幅器A+に入力され、ここで差動増幅
される。In a circuit having such a configuration, the rector current and emitter current of the output I/transistor l'r change depending on the information signal input to the terminal 1. Since the collector current 1c of the output 1 to the transistor Tr is approximately equal to the emitter current flowing through the load RL, a detection voltage Vs (= It-・Rs
) occurs, this detection voltage Vs is connected to the resistors R+, R
2 to the differential amplifier A+, where it is differentially amplified.
すなわら、差動増幅器A1の非反転入力端子には電源電
圧VBを抵抗R1及びR3で分圧して得たv8・R3/
(R1−(−R3)なる電圧が入力され、差動増幅器Δ
1の反転入力端子にはVB−1t−・Rsなる電圧が入
力される。従って、差動増幅器A1からは電流11−が
VB・R+ / ((R+ −1−R3)・Rs)で
表わされる基準電圧より小なるときll L IIレベ
ル、基準電圧以上のときit H11レベルの電圧Vo
が取り出され、端子2へ出力される。In other words, the non-inverting input terminal of the differential amplifier A1 has v8·R3/ which is obtained by dividing the power supply voltage VB with resistors R1 and R3.
(R1-(-R3) voltage is input, differential amplifier Δ
A voltage VB-1t-.Rs is input to the inverting input terminal of No. 1. Therefore, when the current 11- from the differential amplifier A1 is smaller than the reference voltage expressed by VB・R+/((R+ −1−R3)・Rs), it is at the ll L II level, and when it is higher than the reference voltage, it is at the it H11 level. Voltage Vo
is taken out and output to terminal 2.
従って、第4図の電流制限検出回路の電流1 +−対出
力電圧V。の特性は第5図に示す如くになり、この回路
は出力電圧Voが基準電圧以上になると、電流11−が
所定値以上流れる異常状態として検出する。Therefore, the current 1 + - versus output voltage V of the current limit detection circuit of FIG. The characteristics of the circuit are as shown in FIG. 5, and when the output voltage Vo exceeds the reference voltage, this circuit detects it as an abnormal state in which the current 11- flows beyond a predetermined value.
(発明が解決しようとする課題〕
しかるに、上記の従来回路では負荷電流TLのみしか検
出していないため、何らかの原因で電源電圧Voが負荷
変動あるいは電源性能が悪い条件下で変動する場合、電
圧が所定値以上とな′つて出力1−ランジスタTrを破
壊づるおそれがあることを検出することができない。(Problem to be Solved by the Invention) However, since the above-mentioned conventional circuit detects only the load current TL, if the power supply voltage Vo fluctuates for some reason under load fluctuations or poor power supply performance conditions, the voltage may change. It is not possible to detect that the voltage exceeds a predetermined value and may destroy the output 1 transistor Tr.
本発明は上記の点に鑑みてなされたもので、より正確に
回路破壊不具合を検出することがCきる電力制限検出回
路を提供することを目的どする。The present invention has been made in view of the above points, and an object of the present invention is to provide a power limit detection circuit that can more accurately detect circuit breakdown defects.
第1図は本発明の原理構成図を示す。同図中、11は電
流検出1段で、検出すべき電流1を電圧に変換して検出
する1、12は乗算器で、検出すべき電圧Vと電流検出
手段11の出力電圧との乗算を11なう。13は比較器
で、乗算器12の出力電圧と予め設定した基準電圧とを
レベル比較し、基準電圧以上のレベルの乗Q器12の出
力信号入力時に制限検出信号を出力する。FIG. 1 shows a basic configuration diagram of the present invention. In the figure, 11 is a single current detection stage, which converts the current 1 to be detected into a voltage and detects it, and 12 is a multiplier, which multiplies the voltage V to be detected and the output voltage of the current detection means 11. 11 Now. A comparator 13 compares the levels of the output voltage of the multiplier 12 and a preset reference voltage, and outputs a limit detection signal when the output signal of the multiplier Q device 12 whose level is higher than the reference voltage is input.
本発明では、乗算器12により、等価的に検出すべき電
流lと検出すべき電圧Vとの乗算信号、すなわち電力に
相当する信号が取り出される。従って、この乗算器12
の出力電圧を比較器13で基準電圧とレベル比較するこ
とにJ:す、検出1べき電流だけでなく、検出すべき電
圧をも含めた制限検出出力が得られる。In the present invention, the multiplier 12 extracts a multiplied signal of the current l to be equivalently detected and the voltage V to be detected, that is, a signal corresponding to electric power. Therefore, this multiplier 12
By comparing the level of the output voltage with the reference voltage by the comparator 13, a limited detection output including not only the current to be detected but also the voltage to be detected can be obtained.
第2図は本発明の一実施例の回路図を示す。同図中、第
1図及び第4図と同一構成部分には同一符号をイ4し、
その説明を省略する1、第2図において、差動増幅器A
3の非反転入力端子は抵抗R+を介して電源端子に接続
され、またその反転入力端子は抵抗R2を介して電流検
出抵抗Rsと出力トランジスタTrのコレクタとの接続
点に接続されており、更にその出力端子は乗算器12の
入力端子Yに接続されている。FIG. 2 shows a circuit diagram of an embodiment of the present invention. In the same figure, the same components as in FIGS. 1 and 4 are designated by the same reference numerals.
In FIGS. 1 and 2, the explanation of which will be omitted, the differential amplifier A
The non-inverting input terminal of No. 3 is connected to the power supply terminal via the resistor R+, and the inverting input terminal thereof is connected via the resistor R2 to the connection point between the current detection resistor Rs and the collector of the output transistor Tr. Its output terminal is connected to the input terminal Y of the multiplier 12.
乗算器12は入力端子Xに電源電圧Veが印加1)
され、入力端子X及びYの各入力電圧の乗算結果の1/
10イ8の値の電圧を出力する。乗算器12の出力端子
/は抵抗R6を介して]ンパレータA4の非反転入力端
子に接続されている。また、]ンパレータ△4の反転入
力9i:子は抵抗R7を介しU にを準電圧V ref
の電圧性に接続される一方、抵抗R5を介して出力端子
2と接続されている。The multiplier 12 applies the power supply voltage Ve to the input terminal
Outputs a voltage with a value of 10i8. The output terminal / of the multiplier 12 is connected to the non-inverting input terminal of the comparator A4 via a resistor R6. In addition, the inverting input 9i of the comparator △4 is connected to the quasi voltage V ref via the resistor R7.
It is connected to the output terminal 2 via a resistor R5.
上記の構成の回路において、負荷RLに流れる検出すべ
き電流に相当する電流ILは電流検出用抵抗RSの両端
に電圧V Sの形で検出される。従って、差動増幅器A
3の非反転入力端子には電源電圧Vnが抵抗R1を介し
て供給されると共に、その反転入力端子には(VB−V
S)なる電圧が抵抗R2を介して供給され、これにより
差動増幅器Δ3にり乗n器12の入力端子Yへ上記の検
出電圧Vsが供給される。In the circuit configured as described above, a current IL corresponding to the current to be detected flowing through the load RL is detected in the form of a voltage VS across the current detection resistor RS. Therefore, the differential amplifier A
The power supply voltage Vn is supplied to the non-inverting input terminal of No. 3 through the resistor R1, and (VB-V
A voltage S) is supplied via the resistor R2, and thereby the above-mentioned detection voltage Vs is supplied to the input terminal Y of the multiplier 12 through the differential amplifier Δ3.
乗算器12は入力端子Yに入力された検出すべき電流1
+を電圧変換した検出電圧■Sと、入力端子Xに入力さ
れる検出すべき電源電圧Vnとを乗0して、■5−VB
/10なる値の電圧を発生し、これを出力端子Zから抵
抗R6を介して]ンパレタA4の非反転入力端子に供給
する。The multiplier 12 receives the current 1 to be detected inputted to the input terminal Y.
The detection voltage ■S obtained by converting + into a voltage is multiplied by the power supply voltage Vn to be detected inputted to the input terminal X, multiplied by 0, and the result is ■5-VB.
A voltage of /10 is generated and supplied from the output terminal Z to the non-inverting input terminal of the amplifier A4 via the resistor R6.
]ンパレータA4はこの入力電圧■5−VB/10と予
め設定されている基準電圧V refとをレベル比較し
、人力型1]]が基準電圧V rcfより小4cるとき
は゛′L″レベル、vrer以上のときは’ I」”レ
ベルの出力電圧V。を発生し、出力端子2へ出力する。] Comparator A4 compares the levels of this input voltage 5-VB/10 with a preset reference voltage Vref, and when the human-powered type 1]] is smaller than the reference voltage Vrcf by 4c, the level is set to ``L'' level. When the voltage is equal to or higher than vrer, an output voltage V of the level 'I' is generated and output to the output terminal 2.
従って、本実施例の入出力特性は第3図に示J如くにな
り、基準電圧Vref ’ (=10− Vrc4
)以上の電圧が乗算器121こり取り出されたときは、
11 HI+レベルの制限検出信号が端子2へ出力され
る。上記の乗算器12の出力電圧は、検出すべぎ電流I
Lと検出1−べき電源電圧VBの積、すなわち電力に応
じた値であるから、本実施例にJ:れば電力制限検出が
行なえ、よって電流ILが小ざいにも拘らず電源電圧V
Bの変動が大きい場合にも、制限検出ができる。Therefore, the input/output characteristics of this embodiment are as shown in FIG. 3, and the reference voltage Vref' (=10-Vrc4
) or more is extracted from the multiplier 121,
11 A limit detection signal of HI+ level is output to terminal 2. The output voltage of the multiplier 12 is the current to be detected I
Since it is the product of L and detection 1 - power supply voltage VB, that is, a value that corresponds to the power, in this embodiment, if J:, power limit detection can be performed, and therefore, even though the current IL is small, the power supply voltage V
Limit detection can be performed even when the fluctuation of B is large.
上述の如く、本発明によれば、電流及び電圧の両方を含
めた制限検出出力を得ることができるため、電流が比較
的小さいにも拘らず′、fi源電汗が人なる変動をして
出力トランジスタを破壊するおそれがあるにうな場合も
検出することができ、電圧による回路破壊不具合を防ぐ
保護回路どして使用することができる等の特長を右する
ものである。As described above, according to the present invention, it is possible to obtain a limited detection output that includes both current and voltage. It has the advantage of being able to detect cases where there is a risk of destroying the output transistor, and being able to be used as a protection circuit to prevent circuit damage caused by voltage.
13は比較器 を示す。13 is a comparator shows.
Claims (1)
(11)と、 検出すべき電圧と該電流検出手段(11)の出力電圧と
を夫々乗算する乗算器(12)と、該乗算器(12)の
出力電圧と予め設定した基準電圧とをレベル比較し、該
基準電圧以上のレベルの該乗算器(12)の出力電圧入
力時に制限検出信号を出力する比較器(13)と、 よりなることを特徴とする電力制限検出回路。[Claims] A current detection means (11) that converts the current to be detected into a voltage and detects it; and a multiplier (12) that multiplies the voltage to be detected and the output voltage of the current detection means (11), respectively. ), and a comparator that compares the output voltage of the multiplier (12) with a preset reference voltage and outputs a limit detection signal when the output voltage of the multiplier (12) is input at a level higher than the reference voltage. (13) A power limit detection circuit characterized by comprising the following.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6891290A JPH03269265A (en) | 1990-03-19 | 1990-03-19 | Power limitation detecting circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6891290A JPH03269265A (en) | 1990-03-19 | 1990-03-19 | Power limitation detecting circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03269265A true JPH03269265A (en) | 1991-11-29 |
Family
ID=13387342
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6891290A Pending JPH03269265A (en) | 1990-03-19 | 1990-03-19 | Power limitation detecting circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03269265A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2009066274A1 (en) * | 2007-11-20 | 2009-05-28 | Ferfics Limited | Power delivery circuit monitoring |
JP2012137375A (en) * | 2010-12-27 | 2012-07-19 | Sharp Corp | Power meter |
-
1990
- 1990-03-19 JP JP6891290A patent/JPH03269265A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2009066274A1 (en) * | 2007-11-20 | 2009-05-28 | Ferfics Limited | Power delivery circuit monitoring |
US8570025B2 (en) | 2007-11-20 | 2013-10-29 | Ferfics Limited | Power delivery circuit with load current estimation based on monitoring nodes not on the power delivery path |
JP2012137375A (en) * | 2010-12-27 | 2012-07-19 | Sharp Corp | Power meter |
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