JPH0326022A - D/a converter - Google Patents
D/a converterInfo
- Publication number
- JPH0326022A JPH0326022A JP16045789A JP16045789A JPH0326022A JP H0326022 A JPH0326022 A JP H0326022A JP 16045789 A JP16045789 A JP 16045789A JP 16045789 A JP16045789 A JP 16045789A JP H0326022 A JPH0326022 A JP H0326022A
- Authority
- JP
- Japan
- Prior art keywords
- current
- terminal
- wiring
- current wiring
- coefficient
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000006243 chemical reaction Methods 0.000 abstract description 10
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 3
- 230000008094 contradictory effect Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
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- Analogue/Digital Conversion (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明はディ・゛クタル入力に応じたｔｖ．．を出力
ずる電流出力形Ｄ／Ａ変換器に関するものである．〔従
来の技術〕
従来、この種のＤ／Ａ変換器は、その基本構成を第４図
に示すように、出力端子１と、任意ビットのディジタル
量Ｄｉｎを入力するためのディジタル入力端子２と、電
流変換部３と、この電流変換部３の電流変換出力と出力
端子１とを接続するための複数の切換スイッチ５１〜５
，（ただし、ｎは任意の整数で、この例ではｎ＝４であ
る）とから戊っている．
ここで、電流変換部３は、第５図に示すように、複数の
ＭＯＳ電界効果トランジスタ（以下、ＭＯＳトランジス
タ）３１ｌ〜３１．１から戒り、これら各ＭＯＳ｝ラン
ジスタ３１，〜３１．のゲート電極にはそのバイアス端
子３０より一定のバイアス電圧が与えられており、ソー
ス電極９１〜９，ｌは定電位供給端子４を介して接地さ
れている．そして、各ＭＯＳ｝ランジスタ３１１〜３１
７のドレイン端子８，〜８７は電流変換部３の出力端子
であり、各切換スイッチ５１〜５，％を介して出力端子
ｌに接続されている。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention provides a TV system that responds to digital input. ．． This relates to a current output type D/A converter that outputs . [Prior Art] Conventionally, this type of D/A converter has an output terminal 1 and a digital input terminal 2 for inputting a digital quantity Din of arbitrary bits, as shown in FIG. , a plurality of changeover switches 51 to 5 for connecting the current conversion unit 3 and the current conversion output of the current conversion unit 3 to the output terminal 1.
, (where n is any integer; in this example, n=4). Here, as shown in FIG. 5, the current conversion unit 3 is configured to operate from a plurality of MOS field effect transistors (hereinafter referred to as MOS transistors) 31l to 31.1, and to each of these MOS transistors 31, to 31.1. A constant bias voltage is applied to the gate electrode from the bias terminal 30, and the source electrodes 91 to 9,l are grounded via the constant potential supply terminal 4. And each MOS} transistors 311 to 31
Drain terminals 8, .about.87 of 7 are output terminals of the current converter 3, and are connected to the output terminal 1 via respective changeover switches 51.about.5,%.
このようなＤ／Ａ変換器によると、ディジタル量Ｄ！，
１をディジタル入力端子２に入力すると、そのディジタ
ル量に応じて各切換スイッチ５１〜５、が選沢的にオン
，オフ制御されることにより、人力されたディジタル量
Ｄいに応じた出力電流が出力端子１から得られる。According to such a D/A converter, the digital quantity D! ，
1 is input to the digital input terminal 2, each of the changeover switches 51 to 5 is selectively controlled on and off according to the digital quantity, so that the output current according to the manually inputted digital quantity D is controlled. It is obtained from output terminal 1.
従来のＤ／Ａ変換器は以上のように構成されているので
、第６図に示すような第１の電流配線６の持つ配線抵抗
１０，〜１０．による電圧降下により、ＭＯＳ｝ランジ
スタ３１１〜３１，％のドレイン端子８，〜８ｎの電位
が場所によって異なる。Since the conventional D/A converter is configured as described above, the wiring resistance 10, to 10. of the first current wiring 6 as shown in FIG. Due to the voltage drop caused by this, the potentials of the drain terminals 8 and 8n of the MOS transistors 311 to 31,% differ depending on the location.
即ち、ＭＯＳトランジスタのドレイン・ソース間電圧が
場所によって異なってしまう。また、第２の電流配線７
の持つ配線抵抗１１＋〜１１７による電圧降下によって
ＭＯＳ｝ランジスタ３１＋〜３１７のソースの電位が場
所によって異なる。即ち、ＭＯＳ｝ランジスタのゲート
・ソース間電圧が場所によって異なってしまう。これに
より、電流変換部を構戒するＭＯＳ｝ランジスタ３１，
〜３１，，のバイアス条件が場所によって様々となり、
Ｄ／Ａ変換器出力の直線性劣化の原因となるという問題
点があった．
第１の電流配線による電圧降下が原因となって生ずるＭ
ＯＳトランジスタの場所によって異なる電流出力分布お
よび、第２の電流配線による電圧降下が原因となって生
ずるＭＯＳトランジスタの場所によって異なる電流出力
分布の傾向を第７図に、またＭＯＳ｝ランジスタ単体で
の電気的特性によるドレイン・ソース間電圧■。と出力
電流Ｉ１および，ゲート・ソース間電圧ＶＣ＋３と出力
電流Ｉ１との関係を第８図に示した．
本発明は上記のような問題点を解消するためになされた
もので、ディジタル入力に応じた電流を出力するための
電流変換部を構成する各制御素子の場所によって異なる
バイアス条件を解消することができ、優れた直線性を有
するＤ／Ａ変換器を得ることを目的とする。That is, the voltage between the drain and source of the MOS transistor differs depending on the location. In addition, the second current wiring 7
The potential of the sources of the MOS transistors 31+ to 317 differs depending on the location due to the voltage drop caused by the wiring resistances 11+ to 117. That is, the voltage between the gate and source of the MOS transistor differs depending on the location. As a result, the MOS} transistor 31, which controls the current conversion section,
~31,, the bias conditions vary depending on the location,
This had the problem of causing deterioration in the linearity of the D/A converter output. M caused by the voltage drop due to the first current wiring
Figure 7 shows the current output distribution that varies depending on the location of the OS transistor and the tendency of the current output distribution that varies depending on the location of the MOS transistor caused by the voltage drop due to the second current wiring. Drain-source voltage due to physical characteristics■. Figure 8 shows the relationship between output current I1, gate-source voltage VC+3, and output current I1. The present invention has been made to solve the above-mentioned problems, and it is possible to eliminate bias conditions that differ depending on the location of each control element that constitutes a current converter for outputting a current according to a digital input. The object of the present invention is to obtain a D/A converter that can be used in a conventional manner and has excellent linearity.
本発明に係るＤ／Ａ変換器は、ディジタル量を入力する
ためのディジタル入力端子と、出力端子と、２つの導通
端子及び１つの制御端子を有し、導通端子間に流れる電
流が制御端子に印加されるバイアス電圧．及び導通端子
間電圧によって制御される制御素子を複数個備えた電流
変換部と、制御素子の第１の導通端子群と出力端子間と
を入力ディジタル量に応じて接続する切換スイッチと、
切換スイッチと前記出力端子とを共通接続する第１の電
流配線と、制御素子の第２の導通端子と共通接続される
第２の電流配線と、該第２の電流配線に所定の電位を与
えるための定電位供給端子とを備え、電流変換部を構戒
する制御素子単体の電気的特性のうち第１の導通端子と
第２の導通端子間の電圧変化が該導通端子間を流れる電
流量に与える電流変化率を第１の係数、制御素子におけ
る制御端子と第２の導通端子間の電圧変化が該制御素子
の導通端子間を流れる電流量に与える電流変化率を第２
の係数としたとき、第１の電流配線と第２の電流配線を
同じシート抵抗の材質で構戊するのであれば、第１の電
流配線幅と第２の電流配線幅の比を、上記第１の係数と
第２の係数の比に等しくし、また第１の電流配線と第２
の電流配線を同じ配線幅で構成するのであれば、第ｌの
電流配線に用いる材質のシート抵抗と第２の電流配線に
用いる材質のシート抵抗の比を、上記第２の係数と第１
の係数の比に等しくし、かつ、前記出力端子と前記定電
位供給端子とをレイアウト上、相対向する位置に設けた
ものである。The D/A converter according to the present invention has a digital input terminal for inputting a digital quantity, an output terminal, two continuity terminals, and one control terminal, and a current flowing between the continuity terminals is connected to the control terminal. Bias voltage applied. and a current converter including a plurality of control elements controlled by the voltage between the conduction terminals, and a changeover switch that connects the first conduction terminal group of the control element and the output terminal according to the input digital amount.
A first current wiring that commonly connects the changeover switch and the output terminal, a second current wiring that is commonly connected to the second conduction terminal of the control element, and applying a predetermined potential to the second current wiring. Among the electrical characteristics of the single control element controlling the current converter, the change in voltage between the first conduction terminal and the second conduction terminal determines the amount of current flowing between the conduction terminals. The first coefficient is the rate of change in current given to the current flow rate, and the second coefficient is the rate of change in current given to the amount of current flowing between the conduction terminals of the control element due to the voltage change between the control terminal and the second conduction terminal in the control element.
If the first current wiring and the second current wiring are made of materials with the same sheet resistance, the ratio of the first current wiring width to the second current wiring width is equal to the ratio of the coefficient of 1 and the coefficient of the second, and the first current wire and the second
If the current wirings are constructed with the same wiring width, the ratio of the sheet resistance of the material used for the lth current wiring to the sheet resistance of the material used for the second current wiring is determined by the above second coefficient and the sheet resistance of the material used for the first current wiring.
, and the output terminal and the constant potential supply terminal are provided at opposing positions in the layout.
本発明におけるＤ／Ａ変換器においては、電流変換部を
構戒する制御素子の第１の導通端子に共通接続された第
１の電流配線における電圧降下による出力電流分布によ
り、前記制御素子の第２の導通端子に共通接続された第
２の電流配線における電圧降下による出力電流分布を相
殺することで、前記制御素子の場所によって異なる出力
電流を解消することが可能となり、Ｄ／Ａ変換器の直線
性を向上できる．
〔実施例〕
以下、本発明の一実施例を図について説明する。In the D/A converter according to the present invention, the output current distribution due to the voltage drop in the first current wiring commonly connected to the first conduction terminal of the control element that controls the current conversion section By canceling out the output current distribution due to the voltage drop in the second current wiring commonly connected to the two conduction terminals, it is possible to eliminate the output current that differs depending on the location of the control element, and the D/A converter Linearity can be improved. [Example] Hereinafter, an example of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例によるＤ／Ａ変換器を示す基
本的な構成図である。第１図においで、１は出力端子、
２は任意ビットのディジタル量Ｄ．，，を入力するため
のディジタル入力端子、３は入力されたディジタルＩＤ
Ｉ．に応じた出力電流を得るための電流変換部、４は電
流変換部３を横戊する制御素子の一方の導通端子９１〜
９．に所定の電位を与えるための定電位供綺端子、５，
〜５ｏは入力ディジタル量Ｄ！Ｒにより制御される切換
スイッチ、６は一方が電流変換部３を構戒する制御素子
の第１の導道端子８Ｉ〜８，，と切換スイッチ５１〜５
１を介して共通接続され、他方が出力端子１に接続され
た第１の電流配線、７は一方が電流変換部３を構成する
制御素子の第２の導通端子９，〜９７に共通接続され、
他方が定電位供給端子４に接続された第２の電流配線で
ある。FIG. 1 is a basic configuration diagram showing a D/A converter according to an embodiment of the present invention. In Figure 1, 1 is the output terminal;
2 is a digital quantity D.2 of arbitrary bits. , , digital input terminal for inputting , 3 is the input digital ID
I. 4 is one conduction terminal 91 of a control element that crosses the current converter 3.
9. a constant potential supply terminal for applying a predetermined potential to; 5;
~5o is the input digital amount D! A changeover switch 6 is controlled by R, and 6 is a first conductive terminal 8I-8 of a control element, one of which is connected to the current converter 3, and a changeover switch 51-5.
A first current wiring 7 is commonly connected through 1 and the other is connected to the output terminal 1, and 7 is commonly connected to the second conduction terminals 9, to 97 of the control element constituting the current converter 3. ,
The other is a second current wiring connected to the constant potential supply terminal 4.
ここで、電流変換部３は第２図に示すように従来の電流
変換部と同様に各ゲート端子に共通接続されるバイアス
端子３０によって出力電流を制御されるＭＯＳ｝ランジ
スタ３１，〜３１，ｌから横或されている．そしてこの
ＭＯＳ｝ランジスタ３１＋〜３１、のドレイン端子（第
１の導通端子）８１〜８．１は前記切換スイッチ５Ｉ〜
５７及び前記第１の電流配線６を介して出力端子１に接
続され、前記ＭＯＳ｝ランジスタのソース端子（第２の
導通端子）９１〜９，，は前記第２の電流配線７を介し
て前記定電位供給端子４に接続され、該定電位供給端子
４はグランド電位に接地される．次に上記実施例のＤ／
Ａ変換器の動作について説明する．任意ビットのディジ
タル量ＤＬｎをディジタル入力端子２に入力すると、そ
のディジタル量Ｄ．に応じた数だけ切換スイッチ５１〜
５，，をオン状態にする。このとき、第３図にも示した
ように、第１の電流配線６′の持つ配線抵抗での電圧降
下により出力端子１より遠いＭＯＳトランジスタほどド
レイン端子の電位が低くなる傾向があり、また第２の電
流配線７の持つ配線抵抗での電圧降下により定電位供給
端子４より遠いＭＯＳトランジスタほどソースの電位が
高くなる傾向がある。Here, as shown in FIG. 2, the current converter 3 includes MOS transistors 31, to 31, l whose output current is controlled by a bias terminal 30 commonly connected to each gate terminal, similar to the conventional current converter. It has been stolen from. The drain terminals (first conduction terminals) 81 to 8.1 of the MOS} transistors 31+ to 31 are connected to the changeover switches 5I to 31.
57 and the output terminal 1 via the first current wiring 6, and the source terminals (second conduction terminals) 91 to 9 of the MOS transistors are connected to the output terminal 1 via the second current wiring 7. It is connected to a constant potential supply terminal 4, and the constant potential supply terminal 4 is grounded to the ground potential. Next, D/ of the above example
The operation of the A converter will be explained. When a digital quantity DLn of arbitrary bits is input to the digital input terminal 2, the digital quantity D. The number of selector switches 51 to 51 corresponds to
5. Turn on. At this time, as shown in FIG. 3, due to the voltage drop due to the wiring resistance of the first current wiring 6', there is a tendency that the farther the MOS transistor is from the output terminal 1, the lower the potential of the drain terminal. Due to the voltage drop due to the wiring resistance of the current wiring 7 of No. 2, the source potential of the MOS transistor tends to be higher as the distance from the constant potential supply terminal 4 increases.
このとき、第１の電流配線抵抗によるＭＯＳトランジス
タの場所に依存したドレイン端子の電位分布がもたらす
ＭＯＳトランジスタの場所に依存した出力電流分布と、
前記第２の電流配線抵抗によるＭＯＳＩ−ランジスタの
場所に依存したソース端子の電位分布がもたらすＭＯＳ
トランジスタの場所に依存した出力電流分布は第７図に
も示したよは次式で表わすことができる。At this time, an output current distribution depending on the location of the MOS transistor caused by the potential distribution of the drain terminal depending on the location of the MOS transistor due to the first current wiring resistance,
MOS caused by the potential distribution of the source terminal depending on the location of the MOSI-transistor due to the second current wiring resistance.
The output current distribution depending on the location of the transistor, as shown in FIG. 7, can be expressed by the following equation.
β：電流増幅率
Ｖｒ，ｌ：ＩＬきい値電圧
■６，：ゲート・ソース間電圧
ｖ０：ドレイン・ソース間電圧
■，；バイボーラでいうアーリー電圧（第８図参照）ま
た、ＭＯＳ｝ランジスタにおけるゲート・ソース間電圧
，ドレイン・ソース間電圧と出力ｔ流の関係を第８図に
示した。（１）弐及び第８図からもわかるように、第１
の電流配線抵抗によるＭＯＳトランジスタの場所に依存
したドレイン端子の電位分布がもたらすＭＯＳ｝ランジ
スタの場所に依存した出力電流分布と、第２の電流配線
抵抗によるＭＯＳ｝ランジスタの場所に依存したソース
端子の電位分布がもたらすＭＯＳ｝ランジスタの場所に
依存した出力電流分布の傾向は相反するものではあるが
、電流変化の絶対量は全く異なるものである。β: Current amplification factor Vr, l: IL threshold voltage ■6,: Gate-source voltage v0: Drain-source voltage ■,; Early voltage in bibolar terms (see Figure 8) Also, gate in MOS transistor - Figure 8 shows the relationship between source voltage, drain-source voltage, and output t current. (1) As can be seen from Figure 2 and Figure 8, the first
The potential distribution of the drain terminal depending on the location of the MOS transistor due to the current wiring resistance of Although the trends in the output current distribution depending on the location of the MOS transistor caused by the potential distribution are contradictory, the absolute amount of current change is completely different.
本発明においては、ＭＯＳトランジスタのドレイン・ソ
ース間電圧の電圧変化による出力電流変化率を第１の係
数、ＭＯＳ｝ランジスタのゲートソース間電圧の電圧変
化による出力電流変化率を第２の係数としたとき、第１
の′ｇ１流配線と第２の電流配線を同じ材質（同じシー
ト抵抗）で構成するのであれば、第１の電流配線幅と第
２の電流配線幅との比を、
（第１の電流配線幅／第２の電流配線幅）＝（第１の係
数／第２の係数）
とし、第１の電流配線と第２の電流配線を同じ配線幅で
構戒するのであれば、第１の電流配線に用いる材質のシ
ート抵抗と第２の電流配線に用いる材質のシート抵抗と
の比を、
（第１の電流配線のシート抵抗／第２の電流配線のシー
ト抵抗）＝（第２の係数／第１の係数）とし、かつ出力
端子１と定電位供給端子４とをレイアウト上相対向する
位置に設けている。In the present invention, the rate of change in output current due to a change in the voltage between the drain and source of the MOS transistor is used as the first coefficient, and the rate of change in output current due to the change in the voltage between the gate and source of the MOS transistor is used as the second coefficient. time, 1st
If the first current wiring and the second current wiring are made of the same material (same sheet resistance), the ratio of the first current wiring width to the second current wiring width is (first current wiring width/second current wiring width) = (first coefficient/second coefficient), and if the first current wiring and the second current wiring are to be made with the same wiring width, then the first current wiring The ratio of the sheet resistance of the material used for the wiring and the sheet resistance of the material used for the second current wiring is expressed as (sheet resistance of the first current wiring/sheet resistance of the second current wiring) = (second coefficient/ (first coefficient), and the output terminal 1 and constant potential supply terminal 4 are provided at opposing positions in the layout.
従って、
（第１の電流配線における電圧降下／第２の電流配線に
おける電圧降下）一（第２の係数／第１の係数）となり
、これにより、第ｌの電流配線抵抗によるＭＯＳ｝ラン
ジスタの場所に依存したドレイン端子の電位分布がもた
らすＭＯＳ｝ランジスタの場所に依存した出力電流分布
と、第２の電流配線抵抗によるＭＯＳＩ−ランジスタの
場所に依存したソース端子の電位分布がもたらすＭＯＳ
｝ランジスタの場所に依存した出力電流分布とは傾向の
みでなく、絶対量的にも相反するものとなり、電流変換
部を構成するＭＯＳ｝ランジスタの場所に依存した出力
電流の違いを解消することができる。Therefore, (voltage drop in the first current line/voltage drop in the second current line) - (second coefficient/first coefficient), and thereby the location of the MOS} transistor due to the resistance of the lth current line MOS caused by the potential distribution of the drain terminal depending on the location of the transistor} output current distribution depending on the transistor location and MOSI caused by the second current wiring resistance - MOS caused by the potential distribution of the source terminal depending on the location of the transistor
}The output current distribution that depends on the location of the transistor is contradictory not only in terms of tendency but also in absolute quantity. can.
以上のように、本発明にかかるＤ／Ａ変換器によれば、
ディジタル量を入力するためのディジタル入力端子と、
出力端子と、２つの導通端子及び１つの制御端子を有し
、導通端子間に流れる電流が前記制′４ＦＪ端子に印加
されるバイアス電圧によって制御される制御素子を複数
個備えた電流変換部と、制御素子の第１の導通端子と前
記出力端子間とを入力ディジタル量に応じて接続する切
換スイッチとを備え、さらに切換スイッチと出力端子と
を共通接続する第１の電流配線、制御素子の第２の導通
端子と共通接続される第２の電流配線、および該第２の
電流配線に所定の電位を与えるための定電位供給端子を
備え、電流変換部を構成する制御素子単体の電気的特性
のうち、第１の導通端子と第２の導通端子間の電圧変化
が該導通端子間を流れる電流量に与える電流変化率を第
１の係数とし、制御素子における制ＩｌＩ端子と第２の
導道端子間の電圧変化が該制御素子の導通端子間を流れ
る電流量に与える電流変化率を第２の係数としたとき、
第１の電流配線と第２の電流配線を同じシート抵抗を有
する同じ材質で構戒するのであれば、第ｌの電流配線幅
と第２の電流配線幅の比を、第１の係数と第２の係数の
比に等しくし、また第１の電流配線と第２の電流配線を
同じ線幅で構戊するのであれば、第ｌの電流配線に用い
る材質のシート抵抗と第２の電流配線に用いる材質のシ
ート抵抗との比を、第２の係数と第１の係数の比に等し
くしたので、第１の電流配線抵抗による場所に依存した
第１の導通端子の電位分布がもたらす制御素子の場所に
依存した出力電流分布と、同じく第２の導通端子の電位
分布がもたらす制御素子の場所に依存した出力電流分布
とを相殺し、解消することができ、直線性の優れたＤ／
Ａ変換器が得られる効果がある。As described above, according to the D/A converter according to the present invention,
a digital input terminal for inputting digital quantities;
a current converter comprising a plurality of control elements having an output terminal, two conduction terminals and one control terminal, and a current flowing between the conduction terminals is controlled by a bias voltage applied to the control terminal; , a changeover switch that connects the first conduction terminal of the control element and the output terminal according to the input digital amount, and further includes a first current wiring that commonly connects the changeover switch and the output terminal, A second current wiring that is commonly connected to the second conduction terminal, and a constant potential supply terminal for applying a predetermined potential to the second current wiring, and the electrical Among the characteristics, the rate of change in current that the voltage change between the first conduction terminal and the second conduction terminal gives to the amount of current flowing between the conduction terminals is the first coefficient, and the ratio between the control IlI terminal and the second conduction terminal in the control element is When the second coefficient is the current change rate that the voltage change between the conductive terminals gives to the amount of current flowing between the conductive terminals of the control element,
If the first current wiring and the second current wiring are made of the same material with the same sheet resistance, the ratio of the lth current wiring width to the second current wiring width is determined by the first coefficient and the second current wiring width. 2, and if the first current wiring and the second current wiring are configured with the same line width, the sheet resistance of the material used for the first current wiring and the second current wiring Since the ratio of the sheet resistance of the material used in The output current distribution that depends on the location of the control element and the output current distribution that also depends on the location of the control element caused by the potential distribution of the second conduction terminal can be canceled out and eliminated.
This has the effect of providing an A converter.
第１図は本発明の一実施例によるＤ／Ａ変換器を示す図
、第２図は第１図に示したＤ／Ａ変換器における電流変
換部の構成例を示した図、第３図は第１図に示したＤ／
Ａ変換器における寄生配線抵抗を示した図、第４図は従
来のＤ／Ａ変換器を示した図、第５図は第４図に示した
従来のＤ／Ａ変換における電流変換部の構成例を示した
図、第６図は第５図に示した従来のＤ／Ａ変換器におけ
る寄生配線抵抗を示した図、第７図は第１の電流配線の
持つ配線抵抗に起因する電流変換部を構戒する制御素子
の場所に依存した出力電流分布と、第２の電流配線の持
つ配線抵抗に起因する電流変換部を構成する制御素子の
場所に依存した出力電流分布を示した図、第８図は電流
変換部の一構成要素であるＭＯＳトランジスタにおける
Ｖｏｓ（ドレイン・ソース間電圧），ＶＧＳ（ゲート・
ソース間電圧）と出力電流（ドレイン電流）■，との関
係を示した図である。
１は出力端子、２はディジタル入力端子、３は電流変換
部、４は定電位供給端子、５，〜５７は切換スイッチ、
６は第１の電流配線、７は第２の電流配線、８１〜８７
は第１の導通端子、９１〜９ｎは第２の導通端子、３０
はバイアス端子、３１．〜３１，はＭＯＳ｝ランジスタ
、１０１〜１０７は第１の電流配線における配線抵抗、
１１１〜１ｌ，，は第２の電流配線における配線抵抗で
ある．
なお図中同一符号は同一又は相当部分を示す。FIG. 1 is a diagram showing a D/A converter according to an embodiment of the present invention, FIG. 2 is a diagram showing an example of the configuration of a current converter in the D/A converter shown in FIG. 1, and FIG. is D/ shown in Figure 1.
Figure 4 shows the parasitic wiring resistance in the A converter, Figure 4 shows the conventional D/A converter, and Figure 5 shows the configuration of the current converter in the conventional D/A converter shown in Figure 4. A diagram showing an example, FIG. 6 is a diagram showing parasitic wiring resistance in the conventional D/A converter shown in FIG. 5, and FIG. 7 is a diagram showing current conversion due to wiring resistance of the first current wiring. A diagram showing an output current distribution depending on the location of a control element constituting the current conversion section and an output current distribution depending on the location of the control element constituting the current conversion section due to the wiring resistance of the second current wiring, Figure 8 shows Vos (drain-source voltage) and VGS (gate-source voltage) in a MOS transistor, which is a component of the current converter.
FIG. 3 is a diagram showing the relationship between source voltage) and output current (drain current). 1 is an output terminal, 2 is a digital input terminal, 3 is a current converter, 4 is a constant potential supply terminal, 5 and 57 are changeover switches,
6 is the first current wiring, 7 is the second current wiring, 81 to 87
is the first conduction terminal, 91 to 9n are the second conduction terminals, 30
is a bias terminal, 31. 〜31, is a MOS} transistor, 101 to 107 are wiring resistances in the first current wiring,
111~1l,, is the wiring resistance in the second current wiring. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
子と、 出力端子と、 ２つの導通端子及び１つの制御端子を有し、前記導通端
子間に流れる電流が前記制御端子に印加されるバイアス
電圧、及び導通端子間電圧によって制御される制御素子
を複数個備えた電流変換部と、 前記制御素子の第１の導通端子と前記出力端子間とを入
力ディジタル量に応じて接続する切換スイッチと、 前記切換スイッチと前記出力端子とを共通接続する第１
の電流配線、前記制御素子の第２の導通端子と共通接続
される第２の電流配線、および該第２の電流配線に所定
の電位を与える定電位供給端子とを備え、 前記電流変換部を構成する制御素子単体の電気的特性の
うち、第１の導通端子と第２の導通端子間の電圧変化が
該導通端子間を流れる電流量に与える電流変化率を第１
の係数とし、前記制御素子における制御端子と第２の導
通端子間の電圧変化が該制御素子の導通端子間を流れる
電流量に与える電流変化率を第２の係数としたとき、 上記第１の電流配線と上記第２の電流配線を同じシート
抵抗を有する材質で構成したときは上記第１の電流配線
幅と第２の電流配線幅との比を、上記第１の係数と第２
の係数の比に等しくし、あるいは上記第１の電流配線と
第２の電流配線を同じ線幅で構成したときは上記第１の
電流配線に用いる材質のシート抵抗と第２の電流配線に
用いる材質のシート抵抗との比を、上記第２の係数と第
１の係数の比に等しくし、 前記出力端子と前記定電位供給端子とをレイアウト上、
相対向する位置に設けたことを特徴とするＤ／Ａ変換器
。(1) A bias voltage having a digital input terminal for inputting a digital quantity, an output terminal, two conduction terminals and one control terminal, and a current flowing between the conduction terminals is applied to the control terminal; and a current converter including a plurality of control elements controlled by a voltage between conduction terminals; a changeover switch that connects a first conduction terminal of the control element and the output terminal according to an input digital amount; A first connecting the selector switch and the output terminal in common.
a current wiring, a second current wiring that is commonly connected to the second conduction terminal of the control element, and a constant potential supply terminal that applies a predetermined potential to the second current wiring, Among the electrical characteristics of the single control element constituting the control element, the rate of change in current that a change in voltage between the first conduction terminal and the second conduction terminal gives to the amount of current flowing between the conduction terminals is expressed as
and the second coefficient is the current change rate that the voltage change between the control terminal and the second conduction terminal of the control element gives to the amount of current flowing between the conduction terminals of the control element. When the current wiring and the second current wiring are made of materials having the same sheet resistance, the ratio of the first current wiring width to the second current wiring width is determined by the first coefficient and the second current wiring width.
or when the first current wiring and the second current wiring are configured with the same line width, the sheet resistance of the material used for the first current wiring and the coefficient used for the second current wiring. The ratio of the sheet resistance of the material is made equal to the ratio of the second coefficient to the first coefficient, and the output terminal and the constant potential supply terminal are arranged in a layout such that:
A D/A converter characterized in that the D/A converters are provided at opposing positions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1160457A JPH0834431B2 (en) | 1989-06-22 | 1989-06-22 | D / A converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1160457A JPH0834431B2 (en) | 1989-06-22 | 1989-06-22 | D / A converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0326022A true JPH0326022A (en) | 1991-02-04 |
| JPH0834431B2 JPH0834431B2 (en) | 1996-03-29 |
Family
ID=15715353
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1160457A Expired - Lifetime JPH0834431B2 (en) | 1989-06-22 | 1989-06-22 | D / A converter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0834431B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011512091A (en) * | 2008-02-08 | 2011-04-14 | ウードゥヴェ セミコンダクターズ | Integrated circuit containing a number of identical basic circuits fed in parallel |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61173524A (en) * | 1985-01-28 | 1986-08-05 | Mitsubishi Electric Corp | Digital and analog converter |
| JPS63309027A (en) * | 1987-06-11 | 1988-12-16 | Matsushita Electric Ind Co Ltd | Current source circuit |
-
1989
- 1989-06-22 JP JP1160457A patent/JPH0834431B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61173524A (en) * | 1985-01-28 | 1986-08-05 | Mitsubishi Electric Corp | Digital and analog converter |
| JPS63309027A (en) * | 1987-06-11 | 1988-12-16 | Matsushita Electric Ind Co Ltd | Current source circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011512091A (en) * | 2008-02-08 | 2011-04-14 | ウードゥヴェ セミコンダクターズ | Integrated circuit containing a number of identical basic circuits fed in parallel |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0834431B2 (en) | 1996-03-29 |
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