JPH0325967A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0325967A JPH0325967A JP16141889A JP16141889A JPH0325967A JP H0325967 A JPH0325967 A JP H0325967A JP 16141889 A JP16141889 A JP 16141889A JP 16141889 A JP16141889 A JP 16141889A JP H0325967 A JPH0325967 A JP H0325967A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- film
- amorphous
- semiconductor substrate
- formed over
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 22
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 239000012535 impurity Substances 0.000 claims abstract description 7
- 238000004544 sputter deposition Methods 0.000 claims description 10
- 239000003990 capacitor Substances 0.000 abstract description 16
- 230000015556 catabolic process Effects 0.000 abstract description 11
- 230000007423 decrease Effects 0.000 abstract description 7
- 230000003647 oxidation Effects 0.000 abstract description 6
- 238000007254 oxidation reaction Methods 0.000 abstract description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 5
- 239000011574 phosphorus Substances 0.000 abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052681 coesite Inorganic materials 0.000 abstract description 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 2
- 239000000377 silicon dioxide Substances 0.000 abstract description 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 2
- 229910052682 stishovite Inorganic materials 0.000 abstract description 2
- 229910052905 tridymite Inorganic materials 0.000 abstract description 2
- 229920005591 polysilicon Polymers 0.000 abstract 1
- 239000000126 substance Substances 0.000 abstract 1
- 238000007740 vapor deposition Methods 0.000 abstract 1
- 230000000052 comparative effect Effects 0.000 description 6
- 230000007547 defect Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 5
- 238000005259 measurement Methods 0.000 description 5
- 238000009413 insulation Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
この発明は半導体装置の製造方法に関し、更に詳しくは
ＭＯＳＬＳ Ｉなどの半導体装置におけるキャパシタ絶
縁膜の形成方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a capacitor insulating film in a semiconductor device such as a MOS LSI.
（ロ）従来の技術
従来この種形成方法として、キャパシタ絶縁膜を半導体
基仮上に配設された多結晶ンリコン層の表面を熱酸化し
て形成するようにしたものが提案されている。(B) Prior Art Conventionally, as a forming method of this type, a method has been proposed in which a capacitor insulating film is formed by thermally oxidizing the surface of a polycrystalline silicon layer disposed on a temporary semiconductor substrate.
すなわち、第５図において、まず、半導体基仮ｌ上に酸
化膜２を形成し、続いて、全面に多拮晶シリコン（以下
ポリＳ＋と言う）層３を形成し［第５図（ａ）参照］、
次に、ポリＳｔ層３に不純物をドープして低抵抗化をお
こなった後、熱酸化によりポリＳｉ層の表面にＳｔＯｅ
のキャパシタ絶禄膜４を形成する［第５図（ｂ）参照］
。That is, in FIG. 5, first, an oxide film 2 is formed on the semiconductor substrate 1, and then a polyantagonistic silicon (hereinafter referred to as polyS+) layer 3 is formed on the entire surface [FIG. 5(a)] reference],
Next, after doping the polySt layer 3 with impurities to lower its resistance, the surface of the polySi layer is coated with StOe by thermal oxidation.
Form a capacitor insulation film 4 [see FIG. 5(b)]
.
（ハ）発明が解決しようとする課題
しかし、キャパシタ絶縁ＷＡ４の下地としてのポリＳｉ
層３は、その結晶粒界により絶縁膜形成領域である表面
にも凹凸を有するから、その表面を酸化してなるＳｉｎ
．のキャパシタ絶縁膜４は、膜質が悪く、かつポリＳｉ
層３と８１０，膜４との界面に形成される凹凸部で、電
圧を印加した際に電界集中が生じてキャパシタ絶縁膜４
の絶縁耐性の低下を招くおそれがある。(c) Problems to be solved by the invention However, poly-Si as a base for capacitor insulation WA4
Layer 3 also has irregularities on its surface, which is an insulating film formation region, due to its crystal grain boundaries.
．． The capacitor insulating film 4 has poor film quality and is made of poly-Si.
When a voltage is applied, electric field concentration occurs in the uneven portion formed at the interface between layer 3 and 810 and film 4, causing capacitor insulating film 4
This may lead to a decrease in insulation resistance.
一方、上記問題を解決するため、下地層として非結晶シ
リコン（以下アモルファスＳｉと言う）を使用し、これ
が多結晶化しない温度、すなわち、５８０℃以下のｌｚ
度でアモルファスＳｔ上に熱酸化によりＳｉＯｚ膜を形
成するようにしたらのち提案されていろ［特開昭６３−
４６７０号公報コ。On the other hand, in order to solve the above problem, amorphous silicon (hereinafter referred to as amorphous Si) is used as the underlayer, and it is heated at a temperature at which it does not become polycrystalline, that is, 580°C or less.
It was later proposed that a SiOz film be formed on amorphous St by thermal oxidation at
Publication No. 4670.
しかし、この方法を用いても、やはり膜質を良好にする
のは難しく絶縁破壊耐圧が低下し、しかも下地がアモル
ファスＳｉであるから膜厚の制御が難しい。However, even if this method is used, it is still difficult to improve the film quality and the dielectric breakdown voltage decreases, and furthermore, since the base is amorphous Si, it is difficult to control the film thickness.
この発明はキャパシタ絶縁膜の絶縁耐圧の低下を防止で
きる半導体装置の製造方法を提供することを目的とする
ものである。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that can prevent a decrease in dielectric strength of a capacitor insulating film.
（二）課題を解決するための手段
この発明は、半導体基板上に、その全面に、熱酸化膜を
介して非結晶シリコン層を形威し、これに不純物を注入
した後、非結晶シリコン層の全面に、化学的気相蒸着法
（ＣＶＤ法）またはスパツタ法を用いて絶縁層を形成す
ることを特徴とする半導体装置の製造方法である。(2) Means for Solving the Problems This invention forms an amorphous silicon layer on the entire surface of a semiconductor substrate through a thermal oxide film, implants impurities into this, and then forms an amorphous silicon layer. This method of manufacturing a semiconductor device is characterized in that an insulating layer is formed on the entire surface of the semiconductor device using a chemical vapor deposition method (CVD method) or a sputtering method.
すなわち、この発明は、アモルファスＳｉ層の表面が平
坦であることを利用して半導体基板上にアモルファスＳ
ｉ層を形成し、絶ａ膜をアモルファスＳｔ層全面に熱酸
化を除く成膜方法、すなわち、ＣＶＤ法やスパッタ法に
より形成するようにしたものである。That is, the present invention utilizes the flat surface of the amorphous Si layer to deposit amorphous Si on a semiconductor substrate.
An i-layer is formed, and an insulating film is formed on the entire surface of the amorphous St layer by a film-forming method that excludes thermal oxidation, that is, a CVD method or a sputtering method.
この発明において、アモルファスＳｉ層全面に絶縁膜を
形或するには、減圧ＣＶＤ法（ ＣｈｅｍｉｃａｌＶａ
ｐｏｒ Ｄｅｐｏｓｔｉｏｎ ：化学的気相蒸着法）や
常圧ＣＶＤ法、あるいはプラズマＣＶＤ法などのＣＶＤ
技術を用いておこなったり、あるいはスパッタ法を用い
ておこなうのが好ましい。これら戊膜方法はすべて周知
の技術である。In this invention, in order to form an insulating film on the entire surface of the amorphous Si layer, a low pressure CVD method (Chemical Vapor Deposition) is used.
por Deposition: CVD such as chemical vapor deposition (chemical vapor deposition), normal pressure CVD, or plasma CVD
It is preferable to carry out using a technique or a sputtering method. All of these membrane methods are well known techniques.
そして、これら成膜方法のうち、減圧ＣＶＤ法を用いる
のがより好ましく、それによって膜厚の均一性が良好な
絶縁膜を得ることができるとともに、大量処理（いわゆ
る、スループブトが良好）が可能である等の利点を有す
る。Among these film-forming methods, it is more preferable to use the low-pressure CVD method, which makes it possible to obtain an insulating film with good film thickness uniformity, and also enables mass processing (so-called good throughput). It has certain advantages.
この減圧ＣＶＤ法を用いて、半導体基板上に配設された
アモルファスＳｉ層上に、例えば、絶縁膜としてＳｉＯ
ｚのＨＴＯ膜を形成するには、ＳｉＨ４とＬＯとを反応
ガスとして、０． ３ 〜ｌ． ｌＴｏｒｒの圧力下、
１１１０〜８６０℃の温度で成長させることにより行う
ものである。Using this low pressure CVD method, for example, SiO2 is deposited as an insulating film on an amorphous Si layer disposed on a semiconductor substrate.
To form a HTO film of 0.z, SiH4 and LO are used as reaction gases. 3 ~l. Under pressure of lTorr,
This is done by growing at a temperature of 1110 to 860°C.
この際、ＨＴＯ膜は、下地のアモルファスＳＩ層に結晶
化か生じない状態で形成される。At this time, the HTO film is formed without crystallizing the underlying amorphous SI layer.
この発明において、絶縁膜は、Ｓ ｉＯｔＨやＳｉ，Ｎ
４膜あるいはＡＩｔｏｓ膜などの単膜構造でも、下地の
アモルファスＳｔ層上に！ＩＩ；ｔｏ！膜、Ｓｉ，Ｎ４
膜を順次積層してなる二膜構造でも良く、あるいはＳｉ
Ｏｚ膜、３ｉＪ４膜およびＳｉｎ．膜を順次積層してな
る三膜構造のような多膜積層構造でも良く、必要に応じ
て上記構造を選択すれば良い。そして、絶縁膜の層厚も
ｌ００〜ｓｏｏＡが好ましいが、これも必要に応じて選
択される。In this invention, the insulating film is made of SiOtH, Si, N
Even with a single-film structure such as 4-film or AItos film, it can be placed on the underlying amorphous St layer! II;to! Film, Si, N4
A two-layer structure consisting of sequentially laminated films may be used, or a Si
Oz film, 3iJ4 film and Sin. A multi-layered structure such as a three-layered structure in which films are sequentially stacked may be used, and the above structure may be selected as necessary. The thickness of the insulating film is also preferably 100 to sooA, but this is also selected as necessary.
この発明において、アモルファスＳｔは、公知の方法に
より半導体基板上に形成される。例えば、Ｓ ｉ ８
４とＰＨ．とを反応ガスとして用いた減圧ＣＶＤ法によ
り５８０℃以下の温度で低抵抗のための不純物としての
リンをドープしたアモルファスＳｉ層が形成される。In this invention, amorphous St is formed on a semiconductor substrate by a known method. For example, S i 8
4 and PH. An amorphous Si layer doped with phosphorus as an impurity for low resistance is formed at a temperature of 580° C. or lower by a low pressure CVD method using as a reaction gas.
（ホ）作用
半導体基板上にアモルファスＳｉ層をＩＭＬた後これに
不純物をドーブし、続いて、アモルファスＳＩｌ上に公
知のＣＶＤ法またはスパッタ法を用いて絶縁膜を形成す
るようにしたので、欠陥密度の少ない膜質の良好な絶律
層を形戒でき、電圧が印加された際の絶縁破壊耐圧の低
下を防止できる。また、ＣＶＤ法やスパッタ法を用いて
いることから、膜厚の制御を容易にできる。(e) After IMLing an amorphous Si layer on a working semiconductor substrate, it is doped with impurities, and then an insulating film is formed on the amorphous SIl using a known CVD method or sputtering method. It is possible to form an insulating layer with low density and good film quality, and it is possible to prevent a decrease in dielectric breakdown voltage when a voltage is applied. Furthermore, since the CVD method or sputtering method is used, the film thickness can be easily controlled.
（へ）実施例 以下図に示す実施例にもとづいてこの発明を詳述する。(f) Example The present invention will be described in detail below based on embodiments shown in the figures.
なお、これによってこの発明は限定を受けるものではな
い。Note that this invention is not limited by this.
第１図（ｄ）において、高集積のダイナミックＲＡＭの
スタックトキャパシタ型セルのキャパンタは、半導体基
仮ｌ上に、その熱酸化膜２を介してリンがドープされた
アモルファスＳｔ層８、キャパシタ絶縁膜としてのＳｉ
ＯｚのＨＴＯ膜９およびポリＳｉ層１０を順次積層して
なる。In FIG. 1(d), a capantor of a stacked capacitor type cell of a highly integrated dynamic RAM is formed by forming an amorphous St layer 8 doped with phosphorus on a semiconductor substrate 1 through a thermal oxide film 2, and a capacitor insulating layer 8. Si as a film
It is formed by sequentially stacking an Oz HTO film 9 and a poly-Si layer 10.
以下、製造方法について説明する。The manufacturing method will be explained below.
まず、半導体基坂１上にその熱酸化膜２を形成した後、
公知の方法を用いて３０００大の膜厚を有するアモルフ
ァスＳｉ層８ａを形成する［第１図（ａ）参照］。First, after forming the thermal oxide film 2 on the semiconductor substrate 1,
An amorphous Si layer 8a having a thickness of 3000 mm is formed using a known method [see FIG. 1(a)].
続いて、アモルファスＳｉ層８ａにリンを１．８Ｘ １
０”ａＩＩ１−’ドーブして低抵抗化されたアモルファ
スＳｉ層８を形威する［第ｌ図（ｂ）参照］。Subsequently, phosphorus was applied to the amorphous Si layer 8a at a rate of 1.8×1.
The amorphous Si layer 8 is doped with 0"aII1-' to have a low resistance [see FIG. 1(b)].
次に、全面に減圧ＣＶＤ法を用いて膜厚１５０人のＳｉ
ｆｔキャパシタ絶縁膜としてのＨＴＯ膜９を形成する［
第ｌ図（ｃ）参照］。Next, the entire surface was coated with a Si film with a thickness of 150 nm using the low pressure CVD method.
Form an HTO film 9 as a ft capacitor insulating film [
See Figure l(c)].
さらに、ＨＴＯ膜９の全面に膜厚４５００人のポリＳ
ｉ ｉｌ ｌ Ｏを形成する［第１図（ｄ）参照］。こ
のようにしてキャパシタが完戊する。Furthermore, the entire surface of the HTO film 9 is coated with polyS with a film thickness of 4,500 people.
i il l O is formed [see FIG. 1(d)]. In this way, the capacitor is completely discharged.
次に、このようにして得られたＨＴＯ膜の膜厚（入）一
平均耐圧（メガボルト／ｃｒｎ）特性および膜厚一欠陥
密度（ａｍ−’）特性をそれぞれ第２図における曲線（
本実施例はＡ、比較例はＢで示す）および（本実施例は
Ｃ，比較例はＤで示す）で示す。Next, the film thickness (input)/average breakdown voltage (megavolt/crn) and film thickness/defect density (am-') characteristics of the HTO film obtained in this manner are determined by the curves shown in FIG.
The present example is indicated by A, the comparative example is indicated by B) and (the present example is indicated by C, and the comparative example is indicated by D).
第２図において、ＣＶＤ法やスパッタ法によってそれぞ
れアモルファスＳｉ層とポリＳｔｌ上に形成されたＨＴ
Ｏ膜の平均耐圧特性を示す曲線ＡとＢとを比較してもア
モルファスＳｔ層８上に形成されたＨＴＯ模りの方（曲
線Ａ）が平均耐性にすぐれ、かつ欠陥密度特性を示す曲
線ＣとＤとを比較しても本実施例の方が欠陥密度ら少な
いことがわかる。In Fig. 2, HT is formed on the amorphous Si layer and polyStl by CVD method and sputtering method, respectively.
Even when comparing curves A and B showing the average breakdown voltage characteristics of the O film, the HTO pattern formed on the amorphous St layer 8 (curve A) has better average resistance, and curve C showing the defect density characteristics Comparing D and D, it can be seen that this example has a lower defect density.
さらに、ＨＴＯ膜を、膜厚を１５０人に設定してアモル
ファスＳｉ層８上およびポリＳｔ層上にそれぞれ形成し
た時の耐圧ヒストグラムを第３図（ａ）および（ｂ）に
示す。Further, FIGS. 3(a) and 3(b) show breakdown voltage histograms when the HTO film was formed on the amorphous Si layer 8 and the polySt layer, respectively, with the film thickness set to 150.
第３図（ａ）は本願を、第３図（ｂ）は比較例を示し、
第３図（ａ）の（Ｉ）と第３図（ｂ）の（ＩＦ）を比較
すると本願の（Ｉ）の方がＦＲＥＱＵＥＮＣＹが高く、
良好な膜質を有するＨＴＯ膜が形或しされていることが
わかる。また、（ＩＩ［） （ＩＶ）はそれぞれ２回目
の測定で永久破壊した部分を示す、ここで本願の（ＩＩ
Ｉ）と比較例の（ＩＭ）を比較すると、（Ｉ［Ｉ）の方
がＦＲＥＱＵＥＮＣＹが低くなっており、これは０〜Ｉ
（ＭＹ／ｃ＋＋＋）のものは２四目の測定では、すべて
永久破壊していろらののＦＲＥＱＵＥＮＣＹとしては低
いことから本願の（ＩＩＩ）の方がＯＶ）より良質のＨ
ＴＯ膜質を有するものであるということがわかる。FIG. 3(a) shows the present application, FIG. 3(b) shows a comparative example,
Comparing (I) in Figure 3(a) and (IF) in Figure 3(b), (I) in the present application has a higher FREQUENCY.
It can be seen that an HTO film with good film quality was formed. In addition, (II[) and (IV) respectively indicate the parts that were permanently destroyed in the second measurement.
Comparing I) and the comparative example (IM), (I[I) has a lower FREQUENCY, which is between 0 and I
(MY/c+++) were all permanently destroyed in the 24th measurement, and the FREQUENCY of Irono was low, so (III) of the present application is of better quality than OV).
It can be seen that it has TO film quality.
なお、これら測定は、第４図に示すように電極而積Ｓの
パターンを４ｘｘ”のものでおこない、判定電流を１μ
Ａに設定し、この際、１ （ＭＹ／ｃｍ）以下で判定電
流に達するチップを永久破壊したものである。These measurements were carried out using a pattern of electrode volume S of 4xx'' as shown in Figure 4, and a judgment current of 1μ.
A, and in this case, the chip that reached the judgment current at 1 (MY/cm) or less was permanently destroyed.
また、上記ＦＲＥＱＵＥＮＣＹは、ウエハ面内の８６ｉ
ｉｔ所の測定点において、所定のＢＲＥＡＫＤＯＷＮ
Ｆｉｅｌｄ（絶縁破壊電圧）がどれほどであったかとい
う割合（％）を示す。In addition, the above FREQUENCY is 86i within the wafer plane.
At the measurement point at it, the predetermined BREAKDOWN
It shows the percentage (%) of the Field (dielectric breakdown voltage).
このように本実施例によれば、従来の熱酸化によるキャ
パシタ絶縁膜形成はもとより、さらに、ＣＶＤ法による
ＨＴＯ膜の作成においても、下地にアモルファスＳｉ層
８を用いた方が下地のポリＳｉＦ！のものより電界集中
による耐圧の低下を回避できる優れた膜質を有するキャ
パシタ絶縁膜を得ることができる。As described above, according to this embodiment, it is better to use the amorphous Si layer 8 as the base when forming a capacitor insulating film by conventional thermal oxidation, and even when creating an HTO film by the CVD method. It is possible to obtain a capacitor insulating film having superior film quality that can avoid a decrease in breakdown voltage due to electric field concentration.
（ト）発明の効果
以上のようにこの発明によれば、半導体基反上にアモル
ファスＳｉ層を堆積した後これに不純物をドープし、続
いて、アモルファスＳｉ上に公知のＣＶＤ法またはスパ
ッタ法を用いて絶縁膜を形成するようにしたので、欠陥
密度の少ない膜質の良好な絶縁層を形成でき、電圧が印
加された際の絶縁破壊耐圧の低下を防止できる効果があ
る。また、ＣＶＤ法やスパッタ法を用いることから、膜
厚の制御を容易にできるＭ点を有する。(g) Effects of the Invention As described above, according to the present invention, an amorphous Si layer is deposited on a semiconductor substrate and then doped with impurities, and then a known CVD method or sputtering method is applied to the amorphous Si layer. Since the insulating film is formed by using the insulating film, it is possible to form an insulating layer with a low defect density and good film quality, which has the effect of preventing a decrease in dielectric breakdown voltage when a voltage is applied. Furthermore, since the CVD method or the sputtering method is used, there is an M point that allows easy control of the film thickness.
第１図はこの発明の一実施例を説明するための製造工程
説明図、第２図はＨＴＯ膜の膜厚対平均耐圧、および膜
厚対欠陥密度のそれぞれの特性を上記実施例と比較例と
を比枝して示す特性図、第３図（ａ）は上記実施例にお
けるＨＴＯＨの絶縁耐圧破壊の程度を示す特性図、第３
図（ｂ）は上記実施例との比較を示す比較例の第３図（
ａ）相当図、第４図は測定に用いた電極パターンを示す
構成説明図、第５図は従来例を示す製造工程説明図であ
る。
■・・・・・・半導体基仮、２・・・・・・Ｓｉの熱酸
化膜、８・・・・・リンドーブされたアモルファスＳｔ
層、９・・・・・・ＳｔｏｗのＨＴ○膜。
枠理人 社団十 川 ポ
ｌ−！士白；２５冫５上ミ７どヌ１
（Ｃ）
（ｄ）
ＦＲＥＱＬＩＥＩ’ｌＪｃＹ （ ％ ）第
２
図
ＦＲＦ−ＱＵＥＮＣＹ （ 九）Fig. 1 is a manufacturing process explanatory diagram for explaining one embodiment of the present invention, and Fig. 2 shows the characteristics of the HTO film thickness vs. average withstand voltage and film thickness vs. defect density in a comparative example with the above example. FIG. 3(a) is a characteristic diagram showing the degree of dielectric strength breakdown of HTOH in the above example.
Figure (b) is Figure 3 of a comparative example (
a) Corresponding diagram, FIG. 4 is a configuration explanatory diagram showing the electrode pattern used for measurement, and FIG. 5 is a manufacturing process explanatory diagram showing a conventional example. ■... Semiconductor base temporary, 2... Si thermal oxide film, 8... Phosphorus doped amorphous St
Layer 9...Stow's HT○ film. Frame Rijin Togawa Pol-! Shihaku; 25 冫 5 上Mi 7 どnu 1 (C) (d) FREQLIEI'lJcY (%) Fig. 2 FRF-QUENCY (9)
Claims (1)
結晶シリコン層を形成し、これに不純物を注入した後、
非結晶シリコン層の全面に、化学的気相蒸着法（ＣＶＤ
法）またはスパッタ法を用いて絶縁層を形成することを
特徴とする半導体装置の製造方法。1. After forming an amorphous silicon layer on the entire surface of the semiconductor substrate via a thermal oxide film and implanting impurities into it,
Chemical vapor deposition (CVD) is applied to the entire surface of the amorphous silicon layer.
1. A method for manufacturing a semiconductor device, comprising forming an insulating layer using a sputtering method or a sputtering method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16141889A JPH0325967A (en) | 1989-06-23 | 1989-06-23 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16141889A JPH0325967A (en) | 1989-06-23 | 1989-06-23 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0325967A true JPH0325967A (en) | 1991-02-04 |
Family
ID=15734723
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16141889A Pending JPH0325967A (en) | 1989-06-23 | 1989-06-23 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0325967A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5225378A (en) * | 1990-11-16 | 1993-07-06 | Tokyo Electron Limited | Method of forming a phosphorus doped silicon film |
| JP2007163256A (en) * | 2005-12-13 | 2007-06-28 | Sus Corp | Instrument positioning device, and rotation mechanism for instrument positioning device |
-
1989
- 1989-06-23 JP JP16141889A patent/JPH0325967A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5225378A (en) * | 1990-11-16 | 1993-07-06 | Tokyo Electron Limited | Method of forming a phosphorus doped silicon film |
| JP2007163256A (en) * | 2005-12-13 | 2007-06-28 | Sus Corp | Instrument positioning device, and rotation mechanism for instrument positioning device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5279985A (en) | Semiconductor device and method of fabrication thereof | |
| JPH05206473A (en) | Improved dielectric formed on deposited semiconductor | |
| JPH05110024A (en) | Semiconductor device and manufacture thereof | |
| JPH11177051A (en) | Thin-film capacitor and its manufacture | |
| JPH01225149A (en) | Capacitor and manufacture thereof | |
| JP3739809B2 (en) | Thin film transistor manufacturing method | |
| TW200425344A (en) | Method for forming a metal oxide film | |
| JP2000004018A (en) | Method of forming ultra-thin crystalline silicon nitride for gate dielectric on silicon (111) | |
| TWI279891B (en) | Method of manufacturing a flash memory cell | |
| US5001527A (en) | Semiconductor device with thin insulation film | |
| WO1999032691A1 (en) | Insulating material, substrate covered with an insulating film, method of producing the same, and thin-film device | |
| JPH05167008A (en) | Manufacturing method of semiconductor element | |
| JPH0325967A (en) | Manufacture of semiconductor device | |
| JPH0645521A (en) | Manufacture of semiconductor element | |
| JP2000196035A (en) | Manufacture of capacitor of memory device | |
| KR950012555B1 (en) | Memory cell capacitor | |
| EP0418468B1 (en) | Method for producing an ultra-thin dielectric for microelectronics applications | |
| JPH0922884A (en) | Manufacture of semiconductor element | |
| JPH04294532A (en) | Method for forming tungsten silicide film | |
| JPH021124A (en) | Manufacture of dielectric film | |
| JPS5951549A (en) | Manufacture of integrated circuit device | |
| JP3064363B2 (en) | Method of forming Si thin film | |
| JPH08335703A (en) | Thin-film transistor and its manufacture | |
| JPS61120469A (en) | Manufacture of electrode wiring | |
| JPH01292860A (en) | Semiconductor device and manufacture thereof |