JPH03257948A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH03257948A JPH03257948A JP2057190A JP5719090A JPH03257948A JP H03257948 A JPH03257948 A JP H03257948A JP 2057190 A JP2057190 A JP 2057190A JP 5719090 A JP5719090 A JP 5719090A JP H03257948 A JPH03257948 A JP H03257948A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- silicon substrate
- thermal oxide
- deposited
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000005468 ion implantation Methods 0.000 claims abstract description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 14
- 229910052710 silicon Inorganic materials 0.000 abstract description 14
- 239000010703 silicon Substances 0.000 abstract description 14
- 239000013078 crystal Substances 0.000 abstract description 10
- 239000012535 impurity Substances 0.000 abstract description 5
- 238000005530 etching Methods 0.000 abstract description 4
- 239000001301 oxygen Substances 0.000 abstract description 3
- 229910052760 oxygen Inorganic materials 0.000 abstract description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 2
- 238000009826 distribution Methods 0.000 abstract description 2
- 238000002513 implantation Methods 0.000 abstract description 2
- 238000002955 isolation Methods 0.000 abstract description 2
- 238000000206 photolithography Methods 0.000 abstract description 2
- 230000002950 deficient Effects 0.000 abstract 1
- 239000006185 dispersion Substances 0.000 abstract 1
- 238000000407 epitaxy Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 20
- 238000001312 dry etching Methods 0.000 description 7
- 150000004767 nitrides Chemical class 0.000 description 7
- 238000007796 conventional method Methods 0.000 description 5
- 230000007547 defect Effects 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- -1 oxygen ions Chemical class 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Landscapes
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 産業上の利用分野 本発明は半導体装置の製造方法に関するものである。[Detailed description of the invention] Industrial applications The present invention relates to a method of manufacturing a semiconductor device.
従来の技術
近年、単一の半導体基板に多数の機能素子を組み込む集
積回路技術が発達している。このような集積回路におけ
る高集積度を促進するための一手段として局部酸化ＬＯ
ＧＯＳ （ＬｏｃａｌＯｘｉｄａｔｉｏｎ ｏｆ ５ｉ
ｌｉｃｏｎ）法がある。ＬＯＣＯ３法には素子の微細化
につれて種々の問題点が生じることか知られている。こ
のためＬＯＣＯ８法に変わる方法として改良ＬＯＣＯ８
法、溝分離法。BACKGROUND OF THE INVENTION In recent years, integrated circuit technology that incorporates a large number of functional elements on a single semiconductor substrate has been developed. Local oxidation LO is a means to promote high density in such integrated circuits.
GOS (Local Oxidation of 5i
licon) law. It is known that various problems arise in the LOCO3 method as elements become smaller. Therefore, as an alternative to the LOCO8 method, the improved LOCO8 method is
method, groove separation method.
選択エピタキシャル法が提案されている。ここではエピ
タキシャル法について述べる。第２図、第３図は従来の
選択エピタキシャルを用いた分離構造を持つ半導体装置
の製造方法を示す断面図である。A selective epitaxial method has been proposed. Here, we will discuss the epitaxial method. FIGS. 2 and 3 are cross-sectional views showing a conventional method of manufacturing a semiconductor device having an isolation structure using selective epitaxial method.
第２図、第３図において、１は半導体基板、２は素子形
成領域、３は酸化膜、４は素子である。In FIGS. 2 and 3, 1 is a semiconductor substrate, 2 is an element formation region, 3 is an oxide film, and 4 is an element.
次に半導体装置の製造方法を説明する。第２図は半導体
基板ｌを酸化膜３をマスクにドライエツチングし、さら
に酸化膜３、窒化膜を堆積させ、ドライエツチングによ
って窒化膜、酸化膜３底面部を除去し、ウェル形成のた
めのイオン注入を行った後、選択エピタキシャル成長に
よって素子形成領域２を形成する方法である。Next, a method for manufacturing a semiconductor device will be explained. FIG. 2 shows that a semiconductor substrate 1 is dry-etched using an oxide film 3 as a mask, then an oxide film 3 and a nitride film are deposited, the bottoms of the nitride film and oxide film 3 are removed by dry etching, and ions are used to form a well. In this method, after implantation, the element forming region 2 is formed by selective epitaxial growth.
第３図は半導体基板１上に分厚い酸化膜３を堆積し、ド
ライエツチングで素子形成する所定領域の酸化膜３を除
去し、ウェル形成用のイオン注入を行った後、選択エピ
タキシャル成長によって素予形成領域２を堆積する方法
である。FIG. 3 shows that a thick oxide film 3 is deposited on a semiconductor substrate 1, the oxide film 3 is removed in a predetermined area where elements are to be formed by dry etching, ions are implanted for forming wells, and then preliminary formation is performed by selective epitaxial growth. This is the method for depositing region 2.
発明が解決しようとする課題
第２図の従来方法では側壁の酸化膜３を残すために窒化
膜をマスクにドライエツチングされるが酸化膜３と窒化
膜のエツチングレートが興なるため窒化膜が酸化膜３よ
り出っ張った形となり、この状態で選択エピタキシャル
成長を行い、素子形成領域２を形成すると窒化膜で影に
なる部分には単結晶が成長しないでボイドが形成される
。また、酸化膜３に接する部分の結晶は側壁の酸化膜３
によって歪められるため転位等の結晶欠陥を生じる。こ
れらのことは素子４を形成したときにリーク電流が大き
くなる等素子特性を劣化させる誘因になる。Problems to be Solved by the Invention In the conventional method shown in FIG. 2, dry etching is performed using the nitride film as a mask in order to leave the oxide film 3 on the sidewalls, but since the etching rate of the oxide film 3 and the nitride film increases, the nitride film is oxidized. The shape protrudes from the film 3, and when selective epitaxial growth is performed in this state to form the element forming region 2, a void is formed in the portion shaded by the nitride film without the single crystal growing. In addition, the crystal in the part that is in contact with the oxide film 3 is the oxide film 3 on the side wall.
This causes crystal defects such as dislocations to occur. These factors cause deterioration of device characteristics, such as an increase in leakage current when the device 4 is formed.
第３図の従来方法ではドライエツチングによって酸化膜
３をエツチングするが酸化膜３の形状がテーパー形状や
逆テーパー形状あるいは中細り形状であるとエピタキシ
ャル成長を行い、素子形成領域２を形成した場合、上記
第２図の従来方法と同様にボイドが発生したり、結晶欠
陥を生じることになる。このため酸化膜３を完全に垂直
にエツチングする必要があるが、ドライエツチングでそ
のような形状を実現することが困難で、再現性に乏しい
。In the conventional method shown in FIG. 3, the oxide film 3 is etched by dry etching, but when the shape of the oxide film 3 is tapered, reverse tapered, or tapered, epitaxial growth is performed to form the element forming region 2. Similar to the conventional method shown in FIG. 2, voids and crystal defects occur. For this reason, it is necessary to etch the oxide film 3 completely vertically, but it is difficult to achieve such a shape by dry etching, and reproducibility is poor.
また、両方法ともに共通して酸化１１３に隣接した部分
ではエピタキシャル成長層に含まれる不純物は酸化膜３
の中に拡散するため隣接部分のエピタキシャル成長層の
不純物濃度が低くなり素子４の電気的特性を劣化させる
。In addition, in both methods, impurities contained in the epitaxial growth layer are removed from the oxide film 3 in the area adjacent to the oxide 113.
As the impurity diffuses into the epitaxial growth layer, the impurity concentration in the adjacent epitaxial growth layer decreases, deteriorating the electrical characteristics of the element 4.
課題を解決するための手段
本発明の半導体装置の製造方法は上記課題を解決するた
めに半導体基板の所定領域をエツチングし、イオン注入
によってエツチング部の深い領域に絶縁層を形成した後
、エピタキシャル成長によってエツチング部を埋め込む
方法である。Means for Solving the Problems In order to solve the above problems, the method for manufacturing a semiconductor device of the present invention etches a predetermined region of a semiconductor substrate, forms an insulating layer deep in the etched region by ion implantation, and then performs epitaxial growth. This is a method of embedding an etched part.
作用
本発明の半導体装置の製造方法によればエピタキシャル
層が絶縁層に接して成長しない。Effect: According to the method of manufacturing a semiconductor device of the present invention, the epitaxial layer does not grow in contact with the insulating layer.
実施例
第１図は本発明の半導体装置の製造方法を説明するため
の工程断面図を示す。Embodiment FIG. 1 shows process cross-sectional views for explaining the method of manufacturing a semiconductor device of the present invention.
半導体基板として、結晶方位（１００）のシリコン基板
５に熱酸化膜６を４０００Ａ堆積した後、ホトリソグラ
フィーを用いて所定領域にレジストパターンを形成し、
レジストをマスクにフレオン系ガスによるドライエツチ
ングを行って、熱酸化膜６に窓７を開ける。さらに熱酸
化膜６とレジストをマスクにフレオン系ガスを用いてシ
リコン基板５を深さ２μｍドライエツチングする（第１
図ａ）。After depositing a thermal oxide film 6 of 4000A on a silicon substrate 5 with crystal orientation (100) as a semiconductor substrate, a resist pattern is formed in a predetermined area using photolithography.
Using the resist as a mask, dry etching is performed using Freon gas to open windows 7 in the thermal oxide film 6. Furthermore, using the thermal oxide film 6 and the resist as masks, the silicon substrate 5 is dry-etched to a depth of 2 μm using Freon gas (the first
Diagram a).
この後、レジストを除去し、シリコン基板５表面の熱酸
化膜６の上から、エツチング部のシリコン基板５の露出
面がイオン注入によって欠陥が発生しないように熱酸化
膜を４００Ａ堆積する。この後、酸素によるイオン８注
入を行いエツチング部の深さ方向に絶縁層（ここでは酸
化層〉９を形成する（第１図ｂ）。イオン注入条件は加
速電圧１００ｋｅ″Ｖ、 ドーズ量５Ｘ１０１６／ｃｊ
で行った。Thereafter, the resist is removed, and a thermal oxide film of 400 Å is deposited on the thermal oxide film 6 on the surface of the silicon substrate 5 to prevent defects from occurring on the exposed surface of the silicon substrate 5 at the etched portion due to ion implantation. After this, ion implantation using oxygen is performed to form an insulating layer (in this case, an oxide layer) 9 in the depth direction of the etched area (Fig. 1b). The ion implantation conditions are an acceleration voltage of 100 ke''V and a dose of 5 x 1016/ cj
I went there.
この後、選択エピタキシャルを用いてシリコン単結晶１
０を埋め込む（第１図Ｃ）。選択エピタキシャル成長条
件はガス系にＳ １Ｈ２ｃ １２ ＨＣ１−Ｈ２、シ
リコン基板５温度９５０℃、ガス圧力５０Ｔｏ ｒ ｒ
である。After this, silicon single crystal 1 is formed using selective epitaxial technique.
Embed 0 (Figure 1C). Selective epitaxial growth conditions are S1H2C12HC1-H2 gas system, silicon substrate 5 temperature 950°C, gas pressure 50Torr.
It is.
この後、選択エピタキシャル層とエツチング領域以外の
基板にプレーナー技術を用いて素子１１を形成する（第
１図ｄ）。Thereafter, a device 11 is formed using a planar technique on the substrate other than the selective epitaxial layer and the etched region (FIG. 1d).
ここでは第１図ａで熱酸化膜６の厚さを４００ＯＡにし
ているが、この厚さは絶縁層９形威時にエツチング領域
以外の部分にイオンが注入されることを防ぐためのもの
であるためイオンの加速電圧を変えて絶縁層９形威領域
の深さを変えるとそれにつれて変化させる必要がある。Here, the thickness of the thermal oxide film 6 is set to 400 OA in FIG. Therefore, if the depth of the insulating layer 9 shape region is changed by changing the ion accelerating voltage, it is necessary to change the depth accordingly.
ここで絶縁層９を形成するために酸素イオンを用いたが
窒素イオンを用いて窒化層を形成しても良い。Although oxygen ions were used to form the insulating layer 9 here, a nitride layer may be formed using nitrogen ions.
また、ここでは選択エピタキシャル成長を用いたが、単
にエピタキシャル成長を行った後、表面にレジストを筒
布、平坦化してレジストとシリコン基板５のエツチング
レートが一定となるドライエツチング条件でエツチング
し、シリコン単結晶１０の埋め込み部表面を平坦化する
エッチバックを用いても良い。In addition, although selective epitaxial growth was used here, after simply performing epitaxial growth, a resist was coated on the surface, and the silicon substrate 5 was etched under dry etching conditions such that the etching rate of the resist and the silicon substrate 5 was constant. Etch-back may be used to flatten the surface of the buried portion 10.
発明の効果
本発明の半導体装置の製造方法を用いることによって、
エピタキシャル層の界面は半導体層であるため不純物分
布の乱れがなく素子を形成したときにも素子の閾値電圧
のばらつきやリーク電流がない。Effects of the Invention By using the method for manufacturing a semiconductor device of the present invention,
Since the interface of the epitaxial layer is a semiconductor layer, there is no disturbance in impurity distribution, and there is no variation in threshold voltage or leakage current of the device even when the device is formed.
また、エピタキシャル層は絶縁層に接していないため結
晶欠陥はなく、ボイドの発生もない。Furthermore, since the epitaxial layer is not in contact with the insulating layer, there are no crystal defects and no voids are generated.
エツチング領域内に半導体基板が露出しているため、エ
ピタキシャル成長によるボイドの発生はなく、エピタキ
シャル成長で半導体単結晶を埋め込むことができ、信頼
性の高い分離が可能である。Since the semiconductor substrate is exposed within the etching region, no voids are generated due to epitaxial growth, and semiconductor single crystals can be buried by epitaxial growth, allowing highly reliable separation.
第１図は本発明の一実施例である半導体装置の製造方法
を示す工程断面図、第２図、第３図は従来の半導体装置
の製造方法を示す工程断面図である。
１・・・・・・半導体基板、２・・・・・・素子形成領
域、３・・・・・・酸化膜、４，１１・・・・・・素子
、５・・・・・・シリコン基板、６・・・・・・熱酸化
膜、７・・・・・・窓、８・・・・・・イオン、９・・
・・・・絶縁層、ｌＯ・・・・・・シリコン単結晶。FIG. 1 is a process sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIGS. 2 and 3 are process sectional views showing a conventional method for manufacturing a semiconductor device. 1... Semiconductor substrate, 2... Element formation region, 3... Oxide film, 4, 11... Element, 5... Silicon Substrate, 6... thermal oxide film, 7... window, 8... ion, 9...
...Insulating layer, lO...Silicon single crystal.
Claims (1)
溝にイオン注入によって前記溝の底面より深い領域に絶
縁体層を形成する工程と、前記溝をエピタキシャル成長
膜によって埋め込む工程を備えた半導体装置の製造方法
。A semiconductor device comprising: forming a groove in an element formation region of a semiconductor substrate; forming an insulating layer in a region deeper than the bottom of the groove by ion implantation into the groove; and filling the groove with an epitaxial growth film. manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2057190A JPH03257948A (en) | 1990-03-08 | 1990-03-08 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2057190A JPH03257948A (en) | 1990-03-08 | 1990-03-08 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03257948A true JPH03257948A (en) | 1991-11-18 |
Family
ID=13048569
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2057190A Pending JPH03257948A (en) | 1990-03-08 | 1990-03-08 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03257948A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7265017B2 (en) | 2003-07-31 | 2007-09-04 | Kabushiki Kaisha Toshiba | Method for manufacturing partial SOI substrates |
-
1990
- 1990-03-08 JP JP2057190A patent/JPH03257948A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7265017B2 (en) | 2003-07-31 | 2007-09-04 | Kabushiki Kaisha Toshiba | Method for manufacturing partial SOI substrates |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA1159966A (en) | Process of forming recessed dielectric regions in a monocrystalline silicon substrate | |
| US4104086A (en) | Method for forming isolated regions of silicon utilizing reactive ion etching | |
| US4755477A (en) | Overhang isolation technology | |
| JPH1174460A (en) | Manufacture of device | |
| JPS6340337A (en) | Method of isolating integrated circuit | |
| JPS598346A (en) | Integrated circuit completely isolated with dielectric and method of forming same | |
| JPS58118113A (en) | Method of producing semiconductor device | |
| EP0068275B1 (en) | Method for producing semiconductor devices including the use of reactive ion etching | |
| JPH0237745A (en) | Manufacture of semiconductor device | |
| US4775644A (en) | Zero bird-beak oxide isolation scheme for integrated circuits | |
| JPH0582441A (en) | Silicon carbide bipolar semiconductor device and its manufacture | |
| KR0140655B1 (en) | Device isolation method of semiconductor apparatus | |
| JPH03257948A (en) | Manufacture of semiconductor device | |
| KR0179555B1 (en) | Isolation method of semiconductor device | |
| JPH0684938A (en) | Manufacture of semiconductor device | |
| JPH07297174A (en) | Manufacture of semiconductor device | |
| JPH0257701B2 (en) | ||
| JPH02174140A (en) | Manufacture of semiconductor device | |
| JPS6231492B2 (en) | ||
| JPH079930B2 (en) | Method for manufacturing semiconductor device | |
| KR0167600B1 (en) | Element isolation method of semiconductor apparatus | |
| EP0233248A1 (en) | Dielectric isolation structure for integrated circuits | |
| JPS62254444A (en) | Manufacture of semiconductor device | |
| JP2563206B2 (en) | Method for manufacturing semiconductor integrated circuit device | |
| JPS5893343A (en) | Forming method for isolation region of semiconductor integrated circuit |